Gate drive circuit, display panel and display device

Abstract

The invention discloses a gate drive circuit, a display panel and a display device. The gate drive circuit comprises a pull-up module and an output module. The pull-up module is used for generating a cascade control signal based on the clock signal; the first end of the output module is connected with a clock signal, and the output module is used for generating a scanning signal based on the clock signal and outputting the scanning signal at the second end of the output module. When the clock signal is changed from a high level to a low level, the voltage drop rate of the scanning signal is slower than that of the clock signal, the voltage drop rate of the scanning signal can be improved by making the second conduction impedance smaller than the first conduction impedance, the falling edge time of the output scanning signal is shortened, and the reliability of the scanning signal is improved. Therefore, the limitation of the falling edge time on the GOE time of the Data signal of the pixel circuit is reduced, the charging time of the Data signal is prolonged, and the high-brush display effect of the display panel in a heavy load state is guaranteed.

Description

Technical Field

[0001] This application belongs to the technical field of display devices, and particularly relates to a gate driving circuit, a display panel, and a display device. Background Art

[0002] Currently, a liquid crystal panel is one of the important components of a liquid crystal display device. The liquid crystal panel includes pixel units arranged in rows and columns. When the liquid crystal panel is working, the row driving circuit can provide a gate driving signal to the pixel circuit corresponding to the pixel units in units of one row of pixel units, complete the row scanning of the liquid crystal panel, and realize the function of displaying an image on the liquid crystal panel. Common row driving circuits include two types: a gate on array (GOA) driving circuit and a chip on film (COF) driving circuit. Due to the advantages of narrow border and low cost of the GOA driving circuit, it is widely used in display devices.

[0003] However, the falling edge time of the scanning signal output by the existing GOA driving circuit is relatively long, and in the heavy load state, the gate output enable (GOE) time is relatively long, which affects the high refresh performance of the liquid crystal panel. Summary of the Invention

[0004] The purpose of this application is to provide a gate driving circuit, a display panel, and a display device, aiming to solve the problem of the relatively long falling edge time of the scanning signal existing in the traditional display panel.

[0005] A first aspect of an embodiment of this application provides a gate driving circuit, which is applied to a display panel. The display panel includes a plurality of cascaded gate driving circuits; the gate driving circuit includes: a pull-up module, which is used to generate a cascading control signal based on a clock signal; an output module; a first end of the output module is connected to the clock signal, and the output module is used to generate and output a scanning signal at a second end of the output module based on the clock signal; the gate driving circuit is used to set the conduction impedance between the first end and the second end of the output module to a first conduction impedance according to the cascading control signal output by the next-level gate driving circuit when the clock signal is at a high level; at the falling edge of the scanning signal, set the conduction impedance between the first end and the second end of the output module to a second conduction impedance according to the cascading control signal output by the next-level gate driving circuit, and the second conduction impedance is less than the first conduction impedance.

[0006] In one embodiment, the pull-up module includes a charging unit, a bootstrap capacitor, and a first switching device, and the output module includes a second switching device; an output terminal of the charging unit is connected to a first terminal of the bootstrap capacitor and a control terminal of the first switching device, a first terminal of the first switching device is configured to receive the clock signal, a second terminal of the bootstrap capacitor is connected to a second terminal of the first switching device, the charging unit is configured to pull up the voltage of the first terminal of the bootstrap capacitor to a charging voltage before the clock signal provides a high-level pulse during a scanning period, and the first terminal of the bootstrap capacitor is configured to output the cascaded control signal; the first switching device is configured to turn on when a voltage difference between a voltage of the control terminal of the first switching device and a voltage of the first terminal of the first switching device is greater than a conduction threshold, and a voltage difference between the charging voltage and a voltage of a low level of the clock signal is greater than the conduction threshold; a first terminal of the second switching device is configured to receive the clock signal, a control terminal of the second switching device is configured to receive the cascaded control signal output by a next-stage gate driving circuit, and a second terminal of the second switching device is configured to output the scanning signal to a pixel circuit in the display panel; the second switching device is configured to turn on when a voltage difference between a voltage of the control terminal of the second switching device and a voltage of the first terminal of the second switching device is greater than the conduction threshold.

[0007] In one embodiment, the charging unit includes a third switching device, a first terminal of the third switching device is configured to receive the charging voltage, a second terminal of the third switching device is connected to the first terminal of the bootstrap capacitor, and a control terminal of the third switching device is configured to receive a charging control signal, and the charging control signal is configured to control the third switching device to turn on before the clock signal provides a high-level pulse.

[0008] In one embodiment, a second terminal of the first switching device of an n-th stage gate driving circuit is configured to be connected to a charging unit of an (n + X)-th stage gate driving circuit and output the charging control signal to the charging unit of the (n + X)-th stage gate driving circuit.

[0009] In one embodiment, the gate driving circuit further includes a pull-down module; the pull-down module is connected to the first terminal of the bootstrap capacitor and is configured to pull down the voltage of the first terminal of the bootstrap capacitor to a low level after the clock signal changes from a high level to a low level during the scanning period.

[0010] In one embodiment, the gate driving circuit further includes a pull-down holding module; the pull-down holding module is connected to the first terminal of the bootstrap capacitor and is configured to keep the voltage of the first terminal of the bootstrap capacitor at a low level before a next scanning period after the voltage of the first terminal of the bootstrap capacitor is pulled down to a low level.

[0011] In one embodiment, the gate driving circuit further includes a reset module. The reset module is respectively connected to the first end of the boost capacitor, the second end of the first switching device, and the second end of the second switching device. The reset module is configured to pull down the voltages at the first end of the boost capacitor, the second end of the first switching device, and the second end of the second switching device to a low level according to an initialization signal.

[0012] In one embodiment, both the first switching device and the second switching device include N-channel transistors.

[0013] A second aspect of the embodiments of the present application provides a display panel, including a plurality of cascaded gate driving circuits as described above. Among them, the nth-level gate driving circuit is configured to generate and output a scanning signal applied to the pixel circuit in the nth row of the display panel based on a clock signal during a corresponding scanning period.

[0014] A third aspect of the embodiments of the present application provides a display device, including the display panel as described above.

[0015] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: when the clock signal changes from a high level to a low level, the voltage drop rate of the scanning signal is slower than that of the clock signal. By making the second conduction impedance smaller than the first conduction impedance, the voltage drop rate of the scanning signal can be increased, the falling edge time of the output scanning signal can be reduced, and further the limitation of the falling edge time on the GOE time of the Data signal of the pixel circuit can be reduced, the charging time of the Data signal can be increased, and the high refresh rate display effect of the display panel in a heavy load state can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a gate driving circuit provided by an embodiment of the present application; Figure 2 is a waveform diagram of a clock signal, a cascaded control signal, and a charging control signal provided by an embodiment of the present application; Figure 3 is a waveform diagram of a scanning signal and a Data signal provided by an embodiment of the present application; Figure 4 is a waveform diagram of the voltage difference between the control end and the first end of the first switching device and the second switching device provided by an embodiment of the present application; Figure 5 is a specific circuit diagram of a gate driving circuit provided by an embodiment of the present application; Figure 6 is a schematic diagram of a display panel provided by an embodiment of the present application; Figure 7 is a schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer and more understandable, the following further details this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0018] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0019] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to this application.

[0020] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0021] Figure 1 The schematic diagram of the gate driving circuit provided by an embodiment of this application is shown. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A gate driving circuit 10 can be applied to a display panel.

[0022] Among them, the display panel includes a plurality of cascaded gate driving circuits 10. Among them, the nth-stage gate driving circuit 10 is used to generate and output a scanning signal Gn applied to the pixel circuit of the nth row in the display panel based on the clock signal CKn during the corresponding scanning period. n is a positive integer. It can be understood that the structures of the respective gate driving circuits 10 are the same. For the convenience of description, in the subsequent embodiments, the nth-stage gate driving circuit 10 is taken as an example.

[0023] It should be noted that the scanning period specifically corresponds to the scanning signals that each gate driving circuit 10 needs to output. During the scanning period, the corresponding clock signal only includes one high-level pulse. The gate driving circuit 10 usually needs to output a scanning signal with the same high-level pulse based on one high-level pulse of the clock signal during the corresponding scanning period. There is a phase difference between the scanning signals output by different gate driving circuits 10. When the corresponding pixel circuit receives the scanning signal, the pixel circuit will receive the corresponding Data signal and adjust its own light-emitting parameters according to the received Data signal when the voltage of the scanning signal is greater than the set threshold. By providing scanning signals with different phases to each row of pixel circuits, each row of pixel circuits can obtain the corresponding part of the Data signal from the continuous Data signal, realizing the progressive scanning of the display panel.

[0024] It can be understood that if the gate driving circuit 10 of the nth stage and the gate driving circuit 10 of the n + 1th stage are to output scanning signals Gn and Gn+1 with a preset phase difference, the phase difference between the clock signal CKn corresponding to the gate driving circuit 10 of the nth stage and the clock signal CKn+1 corresponding to the gate driving circuit 10 of the n + 1th stage should also be the preset phase difference. Exemplarily, in some embodiments, the clock signal CK1 of the gate driving circuit 10 of the 1st stage to the clock signal CK8 of the gate driving circuit 10 of the 8th stage are as Figure 2 shown.

[0025] As Figure 1 shown, the gate driving circuit 10 of the nth stage includes: a pull-up module 100 and an output module 200.

[0026] The pull-up module 100 is used to generate a cascade control signal PUn based on the clock signal CKn.

[0027] The first end of the output module 200 is used to access the clock signal CKn, and the output module 200 is used to generate and output a scanning signal Gn at the second end of the output module 200 based on the clock signal CKn.

[0028] The gate driving circuit 10 is used to set the conduction impedance between the first end and the second end of the output module 200 to a first conduction impedance according to the cascade control signal PUn+1 output by the next-stage gate driving circuit 10 when the clock signal CKn is at a high level. At the falling edge of the scanning signal Gn, the conduction impedance between the first end and the second end of the output module 200 is set to a second conduction impedance according to the cascade control signal PUn+1 output by the next-stage gate driving circuit 10 (i.e., the gate driving circuit 10 of the n + 1th stage), and the second conduction impedance is less than the first conduction impedance.

[0029] It should be noted that when the clock signal CKn changes from high level to low level, the voltage drop rate of the scan signal Gn is slower than that of the clock signal CKn. By making the second conduction impedance smaller than the first conduction impedance, the voltage drop rate of the scan signal Gn can be increased, the falling edge time of the output scan signal Gn can be reduced, and further the limitation of the falling edge time on the GOE time of the Data signal can be reduced, the charging time of the Data signal can be increased, and the high refresh rate display effect of the display panel in the heavy load state can be ensured. Specifically, setting the GOE time is mainly used to avoid the Data signal supplied to the pixel circuit of the next row being incorrectly read when the voltage of the scan signal Gn has not dropped below the set threshold, resulting in an abnormal final display screen. The longer the falling edge time, the greater the limitation on the GOE time.

[0030] Exemplarily, in some embodiments, the waveforms of the scan signal Gn output by the gate driving circuit 10 of the nth stage and the corresponding Data signal are as Figure 3 shown.

[0031] It should be noted that the shorter the falling edge time Tf of the scan signal Gn, the shorter the GOE time of the Data signal can be. The gate driving circuit 10 of this embodiment can improve the high refresh rate performance of the display panel in the case of heavy load of the display panel.

[0032] In one embodiment, as Figure 5 shown, the pull-up module 100 includes a charging unit 110, a bootstrap capacitor C1, and a first switching device Q1, and the output module 200 includes a second switching device Q2.

[0033] The output terminal of the charging unit 110 is connected to the first end of the bootstrap capacitor C1 and the control terminal of the first switching device Q1. The first end of the first switching device Q1 is used to access the clock signal CKn. The second end of the bootstrap capacitor C1 is connected to the second end of the first switching device Q1. The charging unit 110 is used to pull up the voltage of the first end of the bootstrap capacitor C1 to the charging voltage before the clock signal CKn provides a high-level pulse during the scan period. The first end of the bootstrap capacitor C1 is used to output the cascaded control signal PUn.

[0034] The first switching device Q1 is configured to conduct when the voltage difference between the voltage at the control terminal of the first switching device Q1 and the voltage at the first end of the first switching device Q1 is greater than the conduction threshold, and the voltage difference between the charging voltage and the voltage of the low level of the clock signal CKn is greater than the conduction threshold.

[0035] The first terminal of the second switching device Q2 is used to access the clock signal CKn, the control terminal of the second switching device Q2 is used to access the cascading control signal PUn output by the next-stage gate driving circuit 10 (i.e., the gate driving circuit 10 of the (n + 1)-th stage), and the second terminal of the second switching device Q2 is used to output the scanning signal Gn for the pixel circuit in the display panel.

[0036] The second switching device Q2 is configured to turn on when the voltage difference between the voltage at the control terminal of the second switching device Q2 and the voltage at the first terminal of the second switching device Q2 is greater than the conduction threshold.

[0037] Specifically, the charging unit 110 can be connected to the high-level trace, and charge the first terminal of the bootstrap capacitor based on the voltage VGH of the high-level signal on the high-level trace. The voltage VGH of the high-level signal in the high-level trace is the charging voltage.

[0038] Exemplarily, in some embodiments, the waveforms of the clock signal CKn, the cascading control signal PUn, the scanning signal Gn, the voltage difference between the voltage at the control terminal and the voltage at the first terminal of the first switching device Q1, the voltage difference between the voltage at the control terminal and the voltage at the first terminal of the second switching device Q2, and the cascading control signal PUn+1 of the gate driving circuit 10 of the n-th stage are as Figure 4 shown.

[0039] It can be understood that when the voltage at the first terminal of the bootstrap capacitor C1 turns on the first switching device Q1, after the clock signal CKn changes from low level to high level, the voltage at the second terminal of the first switching device Q1 is the same as the voltage at the first terminal of the first switching device Q1, thereby generating the charging control signal Tn. Similarly, based on the cascading control signal PUn+1, the second switching device Q2 can be controlled to turn on to generate the scanning signal Gn. At the same time, since the bootstrap capacitor C1 has an energy storage function, the voltage at the first terminal of the bootstrap capacitor C1 will rise due to the rise of the voltage at the second terminal of the bootstrap capacitor C1. When the clock signal CKn is at a high level, the voltage of the cascading control signal PUn will become the sum of the charging voltage and the high-level voltage of the clock signal CKn.

[0040] Since the control terminal of the second switching device Q2 is connected to the first end of the bootstrap capacitor of the gate driving circuit 10 of the (n + 1)-th stage, the cascaded control signal PUn+1 lags behind the cascaded control signal PUn. When the clock signal CKn changes from a high level to a low level, the voltage difference between the voltage at the control terminal of the first switching device Q1 and the voltage at the first end of the first switching device Q1 decreases to the charging voltage, and the voltage difference between the voltage at the control terminal of the second switching device Q2 and the voltage at the first end of the second switching device Q2 is equal to the sum of the charging voltage and the high-level voltage of the clock signal CKn+1 minus the low-level voltage of the clock signal CKn. This voltage difference is much greater than the conduction threshold, thereby reducing the on-resistance of the second switching device Q2, achieving the conversion of the on-resistance from the first on-resistance to the second on-resistance, increasing the rate of voltage drop of the scanning signal Gn, reducing the falling-edge time of the output scanning signal Gn, further reducing the GOE time of the Data signal of the pixel circuit, and increasing the charging time of the Data signal.

[0041] In some embodiments, both the first switching device Q1 and the second switching device Q2 can be N-type transistors. In some embodiments, the first switching device Q1 and the second switching device Q2 can also be P-type transistors, and the specific types of the first switching device Q1 and the second switching device Q2 can be set according to actual requirements.

[0042] In one embodiment, as Figure 5 shown, the charging unit 110 includes a third switching device Q3. The first end of the third switching device Q3 is used to connect to a charging voltage, the second end of the third switching device Q3 is connected to the first end of the bootstrap capacitor C1, and the control terminal of the third switching device Q3 is used to connect to a charging control signal. The charging control signal is used to control the third switching device Q3 to conduct before the clock signal provides a high-level pulse.

[0043] Specifically, the third switching device Q3 is configured to conduct when the voltage difference between the voltage at the control terminal of the third switching device Q3 and the first end of the third switching device Q3 is greater than the conduction threshold.

[0044] When the third switching device Q3 conducts, the charging voltage can charge the first end of the bootstrap capacitor until the voltage at the first end of the bootstrap capacitor C1 is equal to the charging voltage. Specifically, the charging control signal can be configured according to the corresponding clock signal CKn, so that the charging unit 110 charges the first end of the bootstrap capacitor C1 only when the clock signal CKn is at a low level.

[0045] The first end of the third switching device Q3 can be connected to a high-level trace, and the first end of the bootstrap capacitor is charged based on the voltage VGH of the high-level signal in the high-level trace. The voltage VGH of the high-level signal in the high-level trace is the charging voltage.

[0046] In one embodiment, the second terminal of the first switching device Q1 of the gate driving circuit 10 of the nth stage is used to be connected to the charging unit 110 of the gate driving circuit 10 of the (n + X)th stage, and is used to output a charging control signal Tn to the charging unit 110 of the gate driving circuit 10 of the (n + X)th stage. Correspondingly, the control terminal of the first switching device Q1 of the gate driving circuit 10 of the nth stage receives the charging control signal Tn-X output by the gate driving circuit 10 of the (n - X)th stage.

[0047] It can be understood that X is a positive integer, and the specific value of X is related to the phase difference between the clock signals of each gate driving circuit 10.

[0048] Exemplarily, as Figure 2 shown, X can be equal to 4, that is, the gate driving circuit 10 of the 5th stage receives the charging control signal T1 output by the gate driving circuit 10 of the 1st stage, and the charging control signal T5 output by the gate driving circuit 10 of the 5th stage is used to be provided to the gate driving circuit 10 of the 9th stage.

[0049] By using the charging control signals output by other gate driving circuits 10, the control of each charging unit 110 can be completed without adding too many signal sources and controllers.

[0050] In one embodiment, the gate driving circuit 10 further includes a pull-down module 300. The pull-down module 300 is connected to the first terminal of the bootstrap capacitor C1, and is used to pull down the voltage of the first terminal of the bootstrap capacitor C1 to a low level (that is, pull down the cascaded control signal PUn to a low level) after the clock signal CKn changes from a high level to a low level during the scanning period.

[0051] Through the pull-down module 300, the electric energy stored in the bootstrap capacitor C1 can be quickly released, so as to avoid the situation that the first terminal of the bootstrap capacitor continuously maintains a high voltage, resulting in the continuous conduction of the first switching device Q1 and the second switching device Q2 after the end of the scanning period, and causing the scanning signal Gn to be abnormal.

[0052] Specifically, the display panel further includes a low-level trace, and the low-level trace is used to provide a low-level signal VSS. The specific voltage of the low-level signal VSS can be set according to actual requirements. Specifically, the low-level signal VSS provided by the low-level trace can be -6V. The pull-down module 300 includes a fourth switching device Q4. The first terminal of the fourth switching device Q4 is connected to the first terminal of the bootstrap capacitor C1, the second terminal of the fourth switching device Q4 is connected to the low-level trace, and the control terminal of the fourth switching device Q4 is used to access a pull-down reset signal Reset. The pull-down reset signal Reset is used to control the fourth switching device Q4 to conduct after the clock signal CKn changes from a high level to a low level during the corresponding scanning period.

[0053] In one embodiment, the gate driving circuit 10 further includes a pull-down holding module 400. The pull-down holding module 400 is connected to the first end of the boost capacitor C1, and is configured to keep the voltage at the first end of the boost capacitor C1 at a low level after the voltage at the first end of the boost capacitor C1 is pulled down to the low level and before the next scanning period.

[0054] The pull-down holding module 400 is configured to keep the cascaded control signal PUn at a low level before the next scanning period, so as to avoid the first switching device Q1 and the second switching device Q2 from being turned on.

[0055] Specifically, the display panel further includes a high-level trace, which can be used to provide a high-level signal VGH and charge the first end of the boost capacitor through the high-level signal VGH. The pull-down holding module 400 includes a fifth switching device Q5, a sixth switching device Q6, a seventh switching device Q7, an eighth switching device Q8, a ninth switching device Q9, and a tenth switching device Q10.

[0056] The first end of the fifth switching device Q5 is connected to the control node of the pull-down holding module 400, the second end of the fifth switching device Q5 is connected to the low-level trace, and the control end of the fifth switching device Q5 is connected to the control end of the third switching device Q3.

[0057] The first end of the sixth switching device Q6 is configured to receive the high-level signal VGH, the second end of the sixth switching device Q6 is connected to the control node, and the control end of the sixth switching device Q6 is connected to the first end of the sixth switching device Q6. The first end of the seventh switching device Q7 is connected to the control node, the second end of the seventh switching device Q7 is connected to the low-level trace, and the control end of the seventh switching device Q7 is connected to the first end of the boost capacitor.

[0058] The first end of the eighth switching device Q8 is connected to the second end of the first switching device Q1, the first end of the ninth switching device Q9 is connected to the second end of the second switching device Q2, the first end of the tenth switching device Q10 is connected to the first end of the boost capacitor, the second ends of the eighth switching device Q8, the ninth switching device Q9, and the tenth switching device Q10 are all connected to the low-level trace, and the control ends of the eighth switching device Q8, the ninth switching device Q9, and the tenth switching device Q10 are all connected to the control node.

[0059] Exemplarily, as Figure 5 shown, taking the gate driving circuit 10 of the 5th stage as an example (i.e., letting n be 5), the scanning period specifically includes stages t1 - t3.

[0060] In stage t1, as Figure 2As shown, the clock signal CK5 is at a low level, and the charge control signal T1 is at a high level, so that the third switching device Q3 and the fifth switching device Q5 are turned on simultaneously. While charging the first end of the bootstrap capacitor C1, the voltage of the control node is also pulled down to a low level. The high level at the first end of the bootstrap capacitor C1 turns on the first switching device Q1 and the seventh switching device Q7, and the low level of the control node turns off the eighth switching device Q8, the ninth switching device Q9, and the tenth switching device Q10.

[0061] The cascade control signal PU6 provided by the gate drive circuit 10 of the sixth stage also controls the second switching device Q2 to turn on after the first switching device Q1 is turned on and after a short delay.

[0062] At this time, both the charge control signal T5 and the scan signal G5 are at a low level.

[0063] In the t2 stage, the clock signal CK5 provides a high-level pulse. The clock signal CK5 is first at a high level and then becomes low, and the charge control signal T1 is first at a low level and then becomes high.

[0064] The voltage of the cascade control signal PU5 first rises to the sum of the charging voltage and the high-level voltage of the clock signal CK5, and then drops back to the charging voltage.

[0065] Since the first switching device Q1 and the second switching device Q2 are continuously turned on, the voltages of the charge control signal T5 and the scan signal G5 are equal to the high-level voltage of the clock signal CK5.

[0066] It should be noted that when the clock signal CK5 changes from a high level to a low level, the charge control signal T5 and the scan signal G5 also change from a high level to a low level. Since the voltage at the control end of the second switching device Q2 is the cascade control signal PU6 of the gate drive circuit 10 of the sixth stage, at this time, the voltage difference between the control end and the first end of the second switching device Q2 is equal to the sum of the charging voltage and the high-level voltage of the clock signal CK6 minus the low-level voltage of the clock signal CK5, thereby improving the conduction ability of the second switching device Q2 by reducing the on-resistance of the second switching device Q2 and reducing the falling edge time of the scan signal Gn.

[0067] In the t3 stage, the clock signal CK5 is at a low level. The fourth switching device Q4 is controlled by the pull-down reset signal Reset to pull down the voltage of the first end of the bootstrap capacitor C1, which can turn off the first switching device Q1 and the second switching device Q2, so that the charge control signal T5 and the scan signal G5 remain at a low level.

[0068] After the cascaded control signal PU5 becomes low, the voltage of the control node is pulled up to high level by the sixth switching device Q6, so that the eighth switching device Q8, the ninth switching device Q9, and the tenth switching device Q10 are turned on simultaneously, thereby maintaining the voltages of the cascaded control signal PU5, the charging control signal T5, and the scanning signal G5 at low level.

[0069] In one embodiment, as Figure 5 shown, the gate driving circuit 10 further includes a reset module 500. The reset module 500 is respectively connected to the first end of the bootstrap capacitor C1, the second end of the first switching device Q1, and the second end of the second switching device Q2, and is configured to pull down the voltages of the first end of the bootstrap capacitor C1, the second end of the first switching device Q1, and the second end of the second switching device Q2 to low level according to the initialization signal CLR.

[0070] It should be noted that pulling down the voltages of the first end of the bootstrap capacitor C1, the second end of the first switching device Q1, and the second end of the second switching device Q2 to low level by the reset module 500 can discharge the residual charge of the gate driving circuit 10 after each gate driving circuit 10 outputs the scanning signal Gn of a frame of picture. In particular, in the case of abnormal power-off and stop of the display panel, the charge in the bootstrap capacitor C1 and the charge at the second end of the second switching device Q2 can be discharged to avoid the influence of the residual charge on the output of the scanning signal Gn.

[0071] Specifically, the reset module 500 includes: an eleventh switching device Q11, a twelfth switching device Q12, a thirteenth switching device Q13, and a fourteenth switching device Q14.

[0072] The first ends of the eleventh switching device Q11, the twelfth switching device Q12, the thirteenth switching device Q13, and the fourteenth switching device Q14 are respectively connected to the first end of the bootstrap capacitor, the second end of the first switching device Q1, the second end of the second switching device Q2, and the control node. The second ends of the eleventh switching device Q11, the twelfth switching device Q12, the thirteenth switching device Q13, and the fourteenth switching device Q14 are all connected to the low-level trace. The control ends of the eleventh switching device Q11, the twelfth switching device Q12, the thirteenth switching device Q13, and the fourteenth switching device Q14 are all configured to receive the initialization signal CLR. The initialization signal CLR can control the eleventh switching device Q11, the twelfth switching device Q12, the thirteenth switching device Q13, and the fourteenth switching device Q14 to be turned on simultaneously, thereby pulling down the voltages of the first end of the bootstrap capacitor, the second end of the first switching device Q1, the second end of the second switching device Q2, and the control node to low level and discharging the charge in the bootstrap capacitor C1.

[0073] In one embodiment, both the first switching device Q1 and the second switching device Q2 include N-channel transistors.

[0074] Specifically, the first ends of the first switching device Q1 and the second switching device Q2 correspond to the source electrodes of the N-channel transistors, the second ends of the first switching device Q1 and the second switching device Q2 correspond to the drain electrodes of the N-channel transistors, and the control ends of the first switching device Q1 and the second switching device Q2 correspond to the gate electrodes of the N-channel transistors.

[0075] In one embodiment, the third switching device Q3 includes an N-channel transistor.

[0076] Specifically, the first end of the third switching device Q3 corresponds to the source electrode of the N-channel transistor, the second end of the third switching device Q3 corresponds to the drain electrode of the N-channel transistor, and the control end of the third switching device Q3 corresponds to the gate electrode of the N-channel transistor.

[0077] In some embodiments, the fourth switching device Q4, the fifth switching device Q5, the sixth switching device Q6, the seventh switching device Q7, the eighth switching device Q8, the ninth switching device Q9, the tenth switching device Q10, the eleventh switching device Q11, the twelfth switching device Q12, the thirteenth switching device Q13, and the fourteenth switching device Q14 are all N-channel transistors.

[0078] Figure 6 The schematic diagram of a display panel provided by an embodiment of the present application is shown. For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A display panel 20 includes a plurality of gate driving circuits 10 cascaded as in any one of the above embodiments and a plurality of pixel circuits 21 corresponding to each of the gate driving circuits 10 one by one. The gate driving circuit 10 is connected to the corresponding pixel circuit 21. The nth-stage gate driving circuit 10 is configured to generate and output a scan signal applied to the nth-row pixel circuit 21 based on a clock signal within a corresponding scan period.

[0079] Since the display panel 20 includes the gate driving circuit 10 of any one of the above embodiments, the display panel 20 has the beneficial effects of the gate driving circuit 10 of any one of the above embodiments, which will not be elaborated herein.

[0080] In some embodiments, the display panel 20 may specifically be a liquid crystal display panel.

[0081] Figure 7 The schematic diagram of a display device provided by an embodiment of the present application is shown. For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A display device 30 includes a display panel 20 as in any of the above embodiments.

[0082] Since the display device 30 includes the display panel 20 of any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 of any of the above embodiments, which will not be elaborated here.

[0083] In some embodiments, the display device 30 may specifically be a smart device such as a mobile phone or a computer.

[0084] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the division of the above functional modules is used as an example. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0085] It should be understood that the devices and methods disclosed in several embodiments provided in the present application can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device. In addition, some features can be ignored or not executed. In addition, the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0086] The units described as separate components can be physically separated or not. The components shown as units can be one physical unit or multiple physical units. That is, they can be located in one place, or can be distributed to multiple different places. Part or all of the units can be selected according to actual needs to achieve the purpose of this solution.

[0087] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit; can also exist physically separately; can also be that some units are integrated in one unit and some units exist physically separately. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0088] It should be noted that all or part (for example, part or all of any feature) of the above various embodiments provided in the present application can be arbitrarily and mutually combined or used in combination.

[0089] The above content is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate driving circuit, characterized in that, Applied to a display panel, the display panel includes a plurality of cascaded gate driving circuits; The gate driving circuit includes: A pull-up module, the pull-up module is used to generate a cascading control signal based on a clock signal; An output module; a first end of the output module is connected to the clock signal, and the output module is used to generate and output a scan signal at a second end of the output module based on the clock signal; The gate driving circuit is used to set the conduction impedance between the first end and the second end of the output module to a first conduction impedance according to the cascading control signal output by the next-level gate driving circuit when the clock signal is at a high level; at the falling edge of the scan signal, set the conduction impedance between the first end and the second end of the output module to a second conduction impedance according to the cascading control signal output by the next-level gate driving circuit, and the second conduction impedance is less than the first conduction impedance.

2. The gate driving circuit according to claim 1, wherein The pull-up module includes a charging unit, a bootstrap capacitor and a first switching device, and the output module includes a second switching device; An output end of the charging unit is connected to a first end of the bootstrap capacitor and a control end of the first switching device. A first end of the first switching device is used to connect to the clock signal. A second end of the bootstrap capacitor is connected to a second end of the first switching device. The charging unit is used to pull up the voltage of the first end of the bootstrap capacitor to a charging voltage before the clock signal provides a high-level pulse during a scan period, and the first end of the bootstrap capacitor is used to output the cascading control signal; The first switching device is configured to conduct when the voltage difference between the voltage at the control end of the first switching device and the voltage at the first end of the first switching device is greater than a conduction threshold, and the voltage difference between the charging voltage and the low-level voltage of the clock signal is greater than the conduction threshold; A first end of the second switching device is used to connect to the clock signal, a control end of the second switching device is used to connect to the cascading control signal output by the next-level gate driving circuit, and a second end of the second switching device is used to output the scan signal for a pixel circuit in the display panel; The second switching device is configured to conduct when the voltage difference between the voltage at the control end of the second switching device and the voltage at the first end of the second switching device is greater than the conduction threshold.

3. The gate driving circuit according to claim 2, wherein The charging unit includes a third switching device. A first end of the third switching device is used to connect to the charging voltage. A second end of the third switching device is connected to a first end of the bootstrap capacitor. A control end of the third switching device is used to connect to a charging control signal, and the charging control signal is used to control the third switching device to conduct before the clock signal provides a high-level pulse.

4. The gate driving circuit according to claim 3, wherein A second end of the first switching device of the nth-level gate driving circuit is used to connect to a charging unit of the (n + X)th-level gate driving circuit and is used to output the charging control signal to the charging unit of the (n + X)th-level gate driving circuit.

5. The gate driving circuit according to any one of claims 2 to 4, characterized in that, The gate driving circuit further includes a pull-down module; the pull-down module is connected to the first end of the boost capacitor and is configured to pull down the voltage at the first end of the boost capacitor to a low level after the clock signal changes from a high level to a low level during the scanning period.

6. The gate driving circuit according to claim 5, wherein The gate driving circuit further includes a pull-down holding module; the pull-down holding module is connected to the first end of the boost capacitor and is configured to keep the voltage at the first end of the boost capacitor at a low level before the next scanning period after the voltage at the first end of the boost capacitor is pulled down to a low level.

7. The gate driving circuit according to claim 5, wherein The gate driving circuit further includes a reset module, the reset module is respectively connected to the first end of the boost capacitor, the second end of the first switching device, and the second end of the second switching device, and the reset module is configured to pull down the voltages at the first end of the boost capacitor, the second end of the first switching device, and the second end of the second switching device to a low level according to an initialization signal.

8. The gate driving circuit according to claim 2, wherein Both the first switching device and the second switching device include N-channel transistors.

9. A display panel, characterized in that, It includes a plurality of cascaded gate driving circuits as described in any one of claims 1 to 8, wherein the nth-stage gate driving circuit is configured to generate and output a scanning signal applied to the pixel circuit of the nth row in the display panel based on a clock signal during a corresponding scanning period.

10. A display device, characterized in that, It includes a display panel as described in claim 9.

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