Noise reduction circuit, gate drive circuit and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit, a gate driving circuit and a display panel, and the noise reduction circuit comprises a noise reduction control unit, a threshold compensation unit and a noise reduction execution unit. The noise reduction control unit is used for outputting a noise reduction signal at the non-scanning time of the scanning stage of the current-stage gate driving module under the action of the noise reduction control signal output by the noise reduction control end and the voltage on the driving control node; the threshold compensation unit is used for compensating the noise reduction signal according to the threshold voltage of a transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; the noise reduction control signal is compensated through the threshold compensation unit according to the threshold voltage of the transistor in the noise reduction execution unit, the problem of unstable noise reduction caused by threshold voltage drift of the noise reduction transistor is solved, and the noise reduction stability of the noise reduction circuit is improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a noise reduction circuit, a gate driving circuit, and a display panel. Background Art

[0002] TFT-LCD (Thin-Film Transistor Liquid Crystal Display) realizes image display by controlling the light transmittance of pixels in the display area. Specifically: under the action of an external voltage, the liquid crystal molecules inside a single pixel deflect, thereby changing the light transmittance and presenting colors; the display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel states frame by frame.

[0003] GOA (Gate Driver on Array) is a key circuit for TFT-LCD to realize progressive scanning. However, the noise reduction circuit for noise reduction processing of each key node is the core module for the reliable operation of GOA. However, the noise reduction transistors in the noise reduction circuit are in a biased state with a positive gate-source voltage (Vgs) for a long time during operation, which easily causes the threshold voltage (Vth) of the noise reduction transistors to drift, resulting in unstable noise reduction and abnormal GOA output signals, affecting the display effect of the display panel.

[0004] Therefore, how to improve the instability of noise reduction caused by the threshold voltage drift of the noise reduction transistors is the problem to be solved currently in the baseband. Summary of the Invention

[0005] Embodiments of the present application provide a noise reduction circuit, a gate driving circuit, and a display panel. By compensating the noise reduction control signal according to the threshold voltage of the transistors in the noise reduction execution unit through a threshold compensation unit, the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistors is improved, and the noise reduction stability of the noise reduction circuit is enhanced.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate driving circuit. The gate driving circuit includes N cascaded gate driving modules. The nth gate driving module includes at least a driving control node, a driving output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: a noise reduction control unit, a threshold compensation unit, and a noise reduction execution unit; a first control end of the noise reduction control unit is connected to a noise reduction control end, a second control end of the noise reduction control unit is connected to the driving control node, and the noise reduction control unit is configured to output a noise reduction signal during a non-scanning time of a scanning stage of the current-stage gate driving module under the action of a noise reduction control signal output by the noise reduction control end and a voltage on the driving control node; the threshold compensation unit is respectively connected to an output end of the noise reduction control unit and the noise reduction execution unit, and the threshold compensation unit is configured to compensate the noise reduction signal according to a threshold voltage of a transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; an output end of the noise reduction execution unit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal, and the noise reduction execution unit is configured to perform noise reduction processing on voltages on the driving control node, the driving output terminal, and the stage transmission output terminal according to the noise reduction compensation signal.

[0007] Optionally, the noise reduction control unit includes: a first transistor, a control end of the first transistor is connected to the noise reduction control end, and a first end of the first transistor is connected to the control end of the first transistor; a second transistor, a control end of the second transistor is connected to a second end of the first transistor, and a first end of the second transistor is connected to the first end of the first transistor; a third transistor, a control end of the third transistor is connected to the driving control node of the nth gate driving module, a first end of the third transistor is connected to the second end of the first transistor, and a second end of the third transistor is connected to a first low-level end; a fourth transistor, a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to a second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end.

[0008] Optionally, the noise reduction control unit further includes: a fifth transistor, a control end of the fifth transistor is connected to the driving control node of the (n + h)th gate driving module, a first end of the fifth transistor is connected to the second end of the first transistor, and a second end of the fifth transistor is connected to the first low-level end; a sixth transistor, a control end of the sixth transistor is connected to the control end of the fifth transistor, a first end of the sixth transistor is connected to the second end of the second transistor, and a second end of the sixth transistor is connected to the first low-level end.

[0009] Optionally, the noise reduction execution unit includes: a seventh transistor, a control end of the seventh transistor is connected to the threshold compensation unit, a first end of the seventh transistor is connected to the driving output end, and a second end of the seventh transistor is connected to a first low level end; an eighth transistor, a control end of the eighth transistor is connected to the control end of the seventh transistor, a first end of the eighth transistor is connected to the driving control node, and a second end of the eighth transistor is connected to the first low level end; a ninth transistor, a control end of the ninth transistor is connected to the control end of the seventh transistor, a first end of the seventh transistor is connected to the stage transmission output end, and a second end of the seventh transistor is connected to a second low level end.

[0010] Optionally, the threshold compensation unit includes: a storage capacitor, a first end of the storage capacitor is connected to an output end of the noise reduction control unit for coupling the noise reduction signal; a compensation sub-unit, the compensation sub-unit is respectively connected to a second end of the storage capacitor and the noise reduction execution unit for compensating the noise reduction signal according to a threshold voltage of a transistor in the noise reduction execution unit.

[0011] Optionally, the compensation sub-unit includes: a tenth transistor, a control end of the tenth transistor is connected to a stage transmission output end of an (n + j)-th stage gate driving module, and a first end of the tenth transistor is connected to a stage transmission output end of an (n + k)-th stage gate driving module; an eleventh transistor, a control end of the eleventh transistor is connected to a second end of the tenth transistor, a first end of the eleventh transistor is connected to a control end of the eleventh transistor, and a second end of the eleventh transistor is connected to a second end of the storage capacitor; a twelfth transistor, a control end of the twelfth transistor is connected to the control end of the tenth transistor, a first end of the twelfth transistor is connected to a stage transmission output end of an (n + l)-th stage gate driving module; a thirteenth transistor, a control end of the thirteenth transistor is connected to a second end of the twelfth transistor, a first end of the thirteenth transistor is connected to a second end of the eleventh transistor, and a second end of the thirteenth transistor is connected to a first end of the seventh transistor.

[0012] Optionally, a size of the eleventh transistor is larger than a size of the thirteenth transistor.

[0013] Optionally, a first low level output by the first low level end is less than or greater than a second low level output by the second low level end.

[0014] Second aspect, an embodiment of the present application provides a gate driving circuit, including N cascaded gate driving modules. The nth gate driving module includes: a pull-up unit, which is respectively connected to the driving output terminal and the stage transmission output terminal of the (n-i)th gate driving module; a pull-down unit, which is connected to the stage transmission output terminal of the (n+j)th gate driving module, and the pull-down unit is further connected to the pull-up unit through a driving control node; an output unit, which is respectively connected to a clock signal terminal and the driving control node; a noise reduction circuit, which is respectively connected to the driving control node, the driving output terminal and the stage transmission output terminal of the current stage gate driving module.

[0015] Third aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the driving output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0016] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects: In the embodiment of the present application, the threshold compensation unit compensates the noise reduction signal output by the noise reduction control unit according to the threshold voltage of the transistor in the noise reduction execution unit, so that the noise reduction compensation signal includes the threshold voltage of the noise reduction transistor. Even after the threshold voltage drifts severely, the noise reduction compensation signal can still turn on the transistor in the noise reduction execution unit, so that the noise reduction circuit can still work normally, avoiding the problem that the gate driving circuit fails due to the threshold voltage drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 Shown is a schematic structural diagram of a gate driving module provided by an embodiment of the present application.

[0019] Figure 2 Shown is a circuit schematic diagram of a noise reduction circuit in the related art.

[0020] Figure 3 Shown as Figure 2 The driving timing diagram of the noise reduction circuit in

[0021] Figure 4 Shown is a schematic structural diagram of a noise reduction circuit provided by an embodiment of the present application.

[0022] Figure 5 The following is a schematic circuit diagram of a noise reduction circuit provided by an embodiment of the present application.

[0023] Figure 6 The following is a schematic diagram of a driving timing provided by an embodiment of the present application.

[0024] Figure 7 The following shows Figure 6 a partial enlarged view at position A in

[0025] Explanation of reference numerals: 100, noise reduction circuit; 110, noise reduction control unit; 120, threshold compensation unit; 121, compensation subunit; 130, noise reduction execution unit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; C, storage capacitor; Qn, drive control node; P1n, first noise reduction control node; P2n, second noise reduction control node; Fn, stage transmission output terminal; Gn, drive output terminal; LC, noise reduction control terminal; VSS1, first low level terminal; VSS2, second low level terminal. Detailed implementation manners

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0027] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will recognize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0028] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, but should not be construed as a limitation to the present application.

[0029] Through research by the inventors of the present application, it is found that the gate driving circuit includes N cascaded gate driving modules. As Figure 1 shown, the nth - stage gate driving module mainly includes a pull - up unit, a pull - down unit, an output unit, a reset unit, and a noise reduction circuit, etc. The pull - up unit and the pull - down unit generate the Q - point voltage. The pull - up unit and the pull - down unit need to obtain multiple - stage transmission signals from the upper and lower gate driving modules. The Q - point voltage is the turn - on voltage of the output unit, enabling the output unit to output a gate driving signal to provide a turn - on voltage for the display area. The reset unit is used to avoid the influence between frames, and the noise reduction circuit performs noise reduction processing on the signals at each key node; where Qn represents the drive control node of the nth - stage gate driving module, Gn represents the drive output terminal of the nth - stage gate driving module, Fn represents the stage - transmission output terminal of the nth - stage gate driving module, CKn represents the clock signal terminal of the nth - stage gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn - 3 represents the drive output terminal of the (n - 3)th - stage gate driving module, Fn - 3 represents the stage - transmission output terminal of the (n - 3)th - stage gate driving module, and Fn + 4 represents the stage - transmission output terminal of the (n + 4)th - stage gate driving module.

[0030] The normal output of the gate driving module is a necessary condition to ensure the normal display of the picture. Therefore, the noise suppression effect of the noise reduction circuit on the signal is particularly important. Figure 2 The circuit schematic diagram of the noise reduction circuit in the related technology is shown as Figure 3 For Figure 2 the drive timing diagram of the noise reduction circuit in Figure 2 The first transistor T1 and the second transistor T2 in Figure 2 and Figure 3 are control transistors, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all noise reduction transistors; as When the driving control node Qn (i.e., the Q point) in the nth - stage gate driving module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned off, making the noise reduction control node Pn at a high level, and respectively turning on the third transistor T3, the fourth transistor T4, and the fifth transistor T5, thereby continuously pulling down the signals on the driving output terminal Gn, the driving control node Qn, and the stage transmission output terminal Fn, achieving noise reduction processing for each important node in the gate driving module; since the driving output terminal, the driving control node, and the stage transmission output terminal in each - stage gate driving module are only not noise - reduced during the scanning time of the current stage, and the other times are all noise - reduction processing time periods; therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the noise reduction circuit need to be in a forward gate - source voltage bias state for a long time, which easily causes the threshold voltage (Vth) of the noise reduction transistor to drift, and further leads to abnormal output signals of the GOA circuit, affecting the display effect of the display panel.

[0031] In order to improve the problem of threshold voltage drift of the noise reduction transistor, the present application provides a noise reduction circuit, which specifically includes the following embodiments: Figure 4 The following shows a schematic structural diagram of a noise reduction circuit provided by an embodiment of the present application; the noise reduction circuit 100 of this embodiment is applied to a gate driving circuit, and the gate driving circuit includes N cascaded gate driving modules; as Figure 1 shown, each - stage gate driving module at least includes a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn, and a noise reduction circuit 100; as Figure 4 shown, the noise reduction circuit 100 includes a noise reduction control unit 110, a threshold compensation unit 120, and a noise reduction execution unit 130.

[0032] In this embodiment, the first control end of the noise reduction control unit 110 is connected to the noise reduction control terminal LC, and the second control end of the noise reduction control unit 110 is connected to the driving control node Qn, and is used to output a noise reduction signal during the non - scanning time of the scanning stage of the current - stage gate driving module under the action of the noise reduction control signal output by the noise reduction control terminal LC and the voltage on the driving control node Qn.

[0033] It should be noted that in the driving technology of the display panel, the scanning (Scan) stage and the blanking stage are key points in timing control, and the two jointly ensure the correct update of pixel data and the stability of display; the scanning stage is the stage where the gate driving circuit activates pixels row by row and writes data; for example, in a row - by - row scanning display, the gate driving signal will sequentially select each row of pixels from top to bottom, and write the voltage signal into the pixel unit of that row through the data line; the blanking stage is the "interval period" between scans. At this time, the driving circuit stops writing data, which is used to switch rows or frames to prevent signal overlap from causing display confusion.

[0034] In this embodiment, the non-scanning time of the current-stage gate driving module represents the non-scanning time of the current stage in the scanning phase; that is, under the combined action of the noise reduction control signal output by the noise reduction control terminal LC and the voltage on the driving control node Qn, the noise reduction control unit 110 in the nth-stage gate driving module outputs a noise reduction signal during the non-scanning time period in the scanning phase of the nth-stage gate driving module, and does not output a noise reduction signal during the scanning time period of the nth-stage gate driving module.

[0035] In this embodiment, the threshold compensation unit 120 is respectively connected to the output end of the noise reduction control unit 110 and the noise reduction execution unit 130. The threshold compensation unit 120 is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit 130 to obtain a noise reduction compensation signal.

[0036] In this embodiment, the output end of the noise reduction execution unit 130 is respectively connected to the driving control node Qn, the driving output end Gn, and the stage transmission output end Fn, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output end Gn, and the stage transmission output end Fn according to the noise reduction compensation signal.

[0037] It should be noted that in this embodiment, noise reduction processing is performed on the voltages on the driving control node Qn, the driving output end Gn, and the stage transmission output end Fn according to the noise reduction compensation signal. That is to say, the noise reduction execution unit 130 continuously pulls down the signals on the driving output end Gn, the driving control node Qn, and the stage transmission output end Fn to prevent the voltages on the driving output end Gn, the driving control node Qn, or / and the stage transmission output end Fn from being at a high level due to leakage current or other transistor abnormalities in the circuit, thereby avoiding display abnormalities such as pixel mischarging.

[0038] In this application, the threshold compensation unit compensates the noise reduction signal output by the noise reduction control unit according to the threshold voltage of the transistor in the noise reduction execution unit, so that the noise reduction compensation signal contains the threshold voltage of the noise reduction transistor. Even after the threshold voltage drifts severely, the noise reduction compensation signal can still turn on the transistor in the noise reduction execution unit, so that the noise reduction circuit can still work normally, improving the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistor and enhancing the noise reduction stability of the noise reduction circuit.

[0039] Figure 5 The following shows a circuit schematic diagram of a noise reduction circuit provided by an embodiment of this application, as Figure 5As shown, the noise reduction control unit 110 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Among them, the control terminal of the first transistor T1 is connected to the noise reduction control terminal LC, and the first terminal of the first transistor T1 is connected to the control terminal of the first transistor T1. The control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the first terminal of the second transistor T2 is connected to the first terminal of the first transistor T1. The control terminal of the third transistor T3 is connected to the drive control node Qn of the current stage gate drive module, the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 is connected to the first low voltage terminal VSS1. The control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the second terminal of the second transistor T2, and the second terminal of the fourth transistor T4 is connected to the first low voltage terminal VSS1.

[0040] It should be noted that the main purpose of the noise reduction control unit 110 in this embodiment is to invert the voltage on the drive control node Qn of the current stage. That is to say, when the voltage on the drive control node Qn is high, the noise reduction control unit 110 outputs a low voltage, and when the voltage on the drive control node Qn is low, the noise reduction control unit 110 outputs a high voltage. Here, in combination with Figure 6 the timing diagram, the specific working principle of the noise reduction control unit 110 is elaborated: (1) When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors, the noise reduction control terminal LC outputs a high level all the time during the scanning stage, continuously turning on the first transistor T1.

[0041] (2) During the scanning time of the current stage gate drive module, the voltage on the drive control node Qn is high, and at the same time, the third transistor T3 and the fourth transistor T4 are turned on, so that the voltages on the node An and the first noise reduction control node P1n are both the first low level output by the first low voltage terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level, that is, the voltage on the first noise reduction control node P1n is the first low level, as shown in Figure 6 the Gn waveform and the P1n waveform in.

[0042] (3) During the non-scanning time of the scanning stage of the current stage gate drive module, the voltage on the drive control node Qn of the current stage is low, and at the same time, the third transistor T3 and the fourth transistor T4 are turned off, then the voltage on the node An is high, thereby turning on the second transistor T2, and the noise reduction control unit 110 outputs a high level, which is the noise reduction signal, that is to say, at this time, the voltage on the first noise reduction control node P1n is high.

[0043] In another embodiment, if Figure 5 As shown, the noise reduction control unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; wherein the control end of the first transistor T1 is connected to the noise reduction control end LC, and the first end of the first transistor T1 is connected to the control end of the first transistor T1; the control end of the second transistor T2 is connected to the second end of the first transistor T1, and the first end of the second transistor T2 is connected to the first end of the first transistor T1; the control end of the third transistor T3 is connected to the driving control node Qn of the current gate driving module, the first end of the third transistor T3 is connected to the second end of the first transistor T1, and the second end of the third transistor T3 is connected to the first low level end VSS1; the control end of the fourth transistor T4 is connected to the control end of the third transistor T3, the first end of the fourth transistor T4 is connected to the second end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first low level end VSS1.

[0044] In this embodiment, the control end of the fifth transistor T5 is connected to the driving control node of the n+h-th level gate driving module, the first end of the fifth transistor T5 is connected to the second end of the first transistor T1, and the second end of the fifth transistor T5 is connected to the first low level end VSS1; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the second end of the second transistor T2, and the second end of the sixth transistor T6 is connected to the first low level end VSS1.

[0045] It should be noted that the main purpose of the noise reduction control unit 110 provided in this embodiment is to invert the voltage on the driving control node Qn of the current gate driving module and the voltage on the driving control node of the n+h-th gate driving module, that is to say: if the voltage on any node of the current driving control node Qn and the n+h-th driving control node Qn+h is high, the noise reduction control unit 110 outputs a low level; if the voltage on the current driving control node Qn and the n+h-th driving control node Qn+h is low, the noise reduction control unit 110 outputs a high level; therefore, the voltage inversion method of the two-stage driving control node in this embodiment can widen the time that the first noise reduction control node P1n is at a low potential, delay its pull-up, and gain enough time for the threshold voltage extraction process, thereby improving the accuracy of compensation.

[0046] Here, combined Figure 6 The specific working principle of the noise reduction control unit 110 of this embodiment is described as follows: (1)When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type MOS transistors, the noise reduction control terminal LC outputs a high level continuously during the scanning stage, and the first transistor T1 is continuously turned on.

[0047] (2)During the scanning time of the current-stage gate driving module (i.e., the nth-stage gate driving module), the voltage on the driving control node Qn is high. At the same time, the third transistor T3 and the fourth transistor T4 are turned on, so that the voltages on the node An and the first noise reduction control node P1n are both the first low level output by the first low level terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level, that is, the voltage on the first noise reduction control node P1n is the first low level, as shown in Figure 6 the Gn waveform and the P1n waveform in.

[0048] (3)During the scanning time of the (n + h)th-stage gate driving module, the voltage on the (n + h)th-stage driving control node Qn+h is high. At the same time, the fifth transistor T5 and the sixth transistor T6 are turned on, so that the voltages on the node An and the first noise reduction control node P1n are both the first low level output by the first low level terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level, that is, the voltage on the first noise reduction control node P1n is the first low level, as shown in Figure 6 the Gn+h waveform and the P1n waveform in.

[0049] (4)During the non-scanning time common to the current-stage gate driving module and the (n + h)th-stage gate driving module, the voltages on the current-stage driving control node Qn and the (n + h)th-stage driving control node Qn+h are both low. At this time, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, then the voltage on the node An is high, thereby turning on the second transistor T2, and the noise reduction control unit 110 outputs a high level as the noise reduction signal, that is, the voltage on the first noise reduction control node P1n is high at this time.

[0050] In addition, it should be noted that the above description of the working principle takes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 being all N-type MOS transistors as an example. When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors, the working principle is the same but the driving timing is opposite, and it will not be elaborated here.

[0051] As shown in Figure 5As shown in the figure, the noise reduction execution unit 130 of this embodiment includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. Specifically, the control terminal of the seventh transistor T7 is connected to the threshold compensation unit 120. The first terminal of the seventh transistor T7 is connected to the drive output terminal Gn, and the second terminal of the seventh transistor T7 is connected to the first low-level terminal VSS1. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The first terminal of the eighth transistor T8 is connected to the drive control node Qn, and the second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1. The control terminal of the ninth transistor T9 is connected to the control terminal of the seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the stage transmission output terminal Fn, and the second terminal of the seventh transistor T7 is connected to the second low-level terminal VSS2.

[0052] It should be noted that, taking the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 as N-type MOS transistors as an example, the working principle of the noise reduction execution unit 130 will be described in detail as follows: (1) When the threshold compensation unit 120 outputs a noise reduction compensation signal, that is, the voltage on the second noise reduction control node P2n is high level, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on simultaneously, so that the voltage on the drive output terminal Gn is pulled down to the first low level through the turned-on seventh transistor T7, the voltage on the drive control node Qn of the current stage is pulled down to the first low level through the turned-on eighth transistor T8, and the voltage on the stage transmission output terminal Fn of the current stage is pulled down to the second low level through the turned-on ninth transistor T9. Optionally, by respectively adjusting the voltage values of the first low level and the second low level, the leakage currents of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be reduced, and the stability of the voltage on the second noise reduction control node P2n can be improved.

[0053] (2) When the threshold compensation unit 120 does not output a noise reduction compensation signal, that is, the voltage on the second noise reduction control node P2n is low level, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off simultaneously, and the noise reduction processing of the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn of the current stage is stopped.

[0054] As Figure 5 As shown in the figure, the threshold compensation unit 120 provided in this embodiment includes a storage capacitor C and a compensation subunit 121. Among them, the first terminal of the storage capacitor C is connected to the output terminal of the noise reduction control unit 110 for coupling the noise reduction signal. The compensation subunit 121 is respectively connected to the second terminal of the storage capacitor C and the noise reduction execution unit 130, and is used for compensating the noise reduction control signal according to the threshold voltage of the transistors in the noise reduction execution unit 130.

[0055] It should be noted that in this embodiment, the first end of the storage capacitor C is defined as the first noise reduction control node P1n, and the second end of the storage capacitor C is defined as the second noise reduction control node P2n. The noise reduction control unit 110 and the noise reduction execution unit 130 are connected in series through the storage capacitor C, so that the noise reduction signal on the first noise reduction control node P1n is coupled to the second noise reduction control node P2n through the storage capacitor C.

[0056] In this embodiment, the compensation sub-unit 121 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The control terminal of the tenth transistor T10 is connected to the stage transmission output terminal of the (n + j)-th stage gate driving module, and the first terminal of the tenth transistor T10 is connected to the stage transmission output terminal of the (n + k)-th stage gate driving module; the control terminal of the eleventh transistor T11 is connected to the second terminal of the tenth transistor T10, the first terminal of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and the second terminal of the eleventh transistor T11 is connected to the second end of the storage capacitor C; the control terminal of the twelfth transistor T12 is connected to the control terminal of the tenth transistor T10, and the first terminal of the twelfth transistor T12 is connected to the stage transmission output terminal of the (n + l)-th stage gate driving module; the control terminal of the thirteenth transistor T13 is connected to the second terminal of the twelfth transistor T12, the first terminal of the thirteenth transistor T13 is connected to the second terminal of the eleventh transistor T11, and the second terminal of the thirteenth transistor T13 is connected to the first terminal of the seventh transistor T7.

[0057] It should be noted that Figure 5 Qn+h in represents the drive control node of the (n + h)-th stage gate driving module, Fn+j represents the stage transmission output terminal of the (n + j)-th stage gate driving module, Fn+k represents the stage transmission output terminal of the (n + k)-th stage gate driving module, and Fn+l represents the stage transmission output terminal of the (n + l)-th stage gate driving module; according to the connection manner of the tenth transistor T10 and the eleventh transistor T11, when the stage transmission output terminals of the (n + j)-th stage gate driving module and the (n + k)-th stage gate driving module both output high levels, the potential of node Bn is raised by the turned-on tenth transistor T10, and then the potential of the second noise reduction control node P2n is raised by the turned-on eleventh transistor T11; and because the eleventh transistor T11 is in a unidirectional connection manner, the charge on the second noise reduction control node P2n will not discharge through the eleventh transistor T11.

[0058] In addition, according to the connection manners of the twelfth transistor T12 and the thirteenth transistor T13, when high levels are simultaneously output at the stage transmission output end of the n+j-th stage gate driving module and the stage transmission output end of the n+l-th stage gate driving module, the potential of node Cn is pulled high through the turned-on twelfth transistor T12, and then the second noise reduction control node P2n is connected to the driving output end Gn of the current stage through the turned-on thirteenth transistor T13.

[0059] It can be seen therefrom that the present embodiment needs to adopt timing cooperation control on Qn+h, Fn+j, Fn+k, and Fn+l; herein, taking a driving mechanism with 12CK, -6+6 stage transmission, and 5.5hCK width as an example, so i=6, j=6, and according to the logic definition of the present embodiment, h=3, k=2, and l=3, a timing schematic diagram as shown in Figure 6 is obtained; combining with Figure 6 the timing schematic diagram and Figure 7 the locally enlarged view shown in the working principle of the noise reduction circuit of the present embodiment is described as follows: Figure 6 and Figure 7 As can be seen, the potential of the first noise reduction control node P1n is simultaneously controlled by the potentials of node Qn and Qn+3, so that the low potential on the first noise reduction control node P1n continues until Figure 7 it starts to be pulled up after the t3 period in (2) The potentials on Fn+6 and Fn+2 together determine that the potential of node Bn is high at the t1 moment through the tenth transistor T10, and then the high potential of node Bn turns on the eleventh transistor T11, thereby pulling up the potential of the second noise reduction control node P2n; (3) The potentials on Fn+6 and Fn+3 together determine that the potential of node Cn is high at the t1 and t2 moments and low at the t3 moment through the twelfth transistor T12; when node Cn is at a high level, the thirteenth transistor T13 is turned on, so that the control end and the first end of the seventh transistor T7 are conducted, and a discharge is performed to the first low level end VSS1; (4) At time t1, the eleventh transistor T11 charges the second noise reduction control node P2n, and at times t1 and t2, the second noise reduction control node P2n is discharged through the seventh transistor T7. Since the size of the eleventh transistor T11 is smaller than the tenth transistor T10, at time t1, although the second noise reduction control node P2n is simultaneously charged and discharged, the potential of the second noise reduction control node P2n is gradually increased. After time t1, at time t2, the second noise reduction control node P2n only retains the discharge path of the eleventh transistor T11 and the seventh transistor T7. At this time, the final discharged voltage is the threshold voltage of the seventh transistor T7 plus the first low level (i.e., Vss1+Vth). At time t3, the potential of the node Cn is pulled down, and the thirteenth transistor T13 is turned off, so that the voltage of the second noise reduction control node P2n is in a floating state after the t3 period.

[0060] (5) After the time period t3, the potential of the first noise reduction control node P1n rises (the rising potential is ΔV). Affected by the coupling of the storage capacitor C, the potential of the second control node P2n also rises by ΔV, so that the potential of the second noise reduction control node P2n after coupling is the noise reduction compensation signal (i.e., Vss1+Vth+ΔV). At this time, the potential of the second noise reduction control node P2n includes the threshold voltage Vth of the seventh transistor T7. Even if the threshold voltage Vth of the seventh transistor T7 drifts, the potential of the second noise reduction control node P2n will be compensated accordingly, so that the noise reduction capability is not affected by the drift of the threshold voltage Vth.

[0061] (6) The discharge of the second noise reduction control node P2n is terminated in advance after the t2 period, and coupling is performed after the t3 period. The discharge end time and the coupling time are staggered to be performed at the same time, thereby avoiding the potential drop of the second noise reduction control node P2n caused by the untimely termination of the discharge process during the coupling process.

[0062] Among them, Figure 6 and Figure 7 In the figure, the start time of the t1 period corresponds to the rising edge of Fn+6, the end time of the t1 period (i.e. the start time of the t2 period) corresponds to the falling edge of Fn+2, the end time of the t2 period (i.e. the start time of the t3 period) corresponds to the falling edge of Fn+3, and the end time of the t3 period corresponds to the rising edge of P1n.

[0063] In addition, it should be noted that since the functions, models, and forward bias states of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are the same, the drift states of their threshold voltages can also be considered the same; therefore, compensating the voltage on the second noise reduction control node P2n through the threshold voltage of the seventh transistor T7 is equivalent to compensating for the threshold voltage drift of the eighth transistor T8 and the ninth transistor T9, so as to achieve the purpose of compensating for the threshold voltage drift of the transistors (abbreviated as noise reduction transistors) in the noise reduction execution unit.

[0064] The above is only illustrated by taking 12CK and -6+6 level transmission as examples. Under any number of CKs and any level transmission method, it is also applicable to this application. Only by making an adaptive selection of the logic control signal, the same threshold voltage compensation ability can be achieved.

[0065] In summary, the noise reduction circuit provided by this application has at least the following beneficial effects: (1) By extracting the threshold voltage of the transistor (i.e., the seventh transistor) for noise reduction processing, this application can better represent the change of the noise reduction ability drift, ensure the compensation accuracy, and improve the noise reduction precision.

[0066] (2) By adopting the method of inverting the voltage of the two-stage drive control node, this application can widen the duration when the first noise reduction control node P1n is at a low potential, delay its pull-up, and strive for sufficient time for the threshold voltage extraction process, thus improving the compensation accuracy.

[0067] (3) By using the logical combination of the signals output at the level transmission output end to extract the threshold voltage, this application avoids adding additional control signals and reduces the complexity of the noise reduction circuit.

[0068] (4) This application is applicable to display devices with any number of CKs and CK widths, enabling this device to have the threshold voltage compensation ability. Even after the threshold voltage drifts severely, the noise reduction circuit can still work normally, improving the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistors and enhancing the noise reduction stability of the noise reduction circuit.

[0069] In one embodiment, the embodiment of this application provides a gate drive circuit, which includes N cascaded gate drive modules. The nth gate drive module includes: a pull-up unit, a pull-down unit, an output unit, and a noise reduction circuit. The pull-up unit is respectively connected to the drive output end and the level transmission output end of the (n-i)th gate drive module; the pull-down unit is connected to the level transmission output end of the (n+j)th gate drive module, and the pull-down unit is also connected to the pull-up unit through a drive control node; the output unit is respectively connected to the clock signal terminal and the drive control node; the noise reduction circuit is respectively connected to the drive control node, the drive output end, and the level transmission output end of the current-stage gate drive module.

[0070] It should be noted that the specific structure of the gate driving module provided in this embodiment is as follows Figure 1 As shown, the working principle of the gate driving module was described above by taking i = 3 and j = 4 as examples, and will not be elaborated here.

[0071] In one embodiment, an embodiment of the present application provides a display panel, including a display area and a non-display area. The display area includes a plurality of scan lines; the non-display area includes a gate driving circuit, and the driving output ends of the circuit units in the gate driving circuit are electrically connected to at least one scan line.

[0072] In addition, terms such as "first", "second", "third", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0073] In the description of this specification, the descriptions referring to terms such as "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0074] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as a limitation to the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the description of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A noise reduction circuit, characterized in that, Applied to a gate driving circuit, the gate driving circuit includes N cascaded gate driving modules. The nth - stage gate driving module includes at least a driving control node, a driving output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: A noise reduction control unit, a threshold compensation unit, and a noise reduction execution unit; A first control end of the noise reduction control unit is connected to a noise reduction control terminal, a second control end of the noise reduction control unit is connected to the driving control node. The noise reduction control unit is configured to output a noise reduction signal during a non - scanning time of a scanning stage of the current - stage gate driving module under the action of a noise reduction control signal output from the noise reduction control terminal and a voltage on the driving control node; The threshold compensation unit is respectively connected to an output end of the noise reduction control unit and the noise reduction execution unit. The threshold compensation unit is configured to compensate the noise reduction signal according to a threshold voltage of a transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; An output end of the noise reduction execution unit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal. The noise reduction execution unit is configured to perform noise reduction processing on voltages on the driving control node, the driving output terminal, and the stage transmission output terminal according to the noise reduction compensation signal.

2. The noise reduction circuit according to claim 1, wherein The noise reduction control unit includes: A first transistor, a control end of the first transistor is connected to the noise reduction control terminal, and a first end of the first transistor is connected to the control end of the first transistor; A second transistor, a control end of the second transistor is connected to a second end of the first transistor, and a first end of the second transistor is connected to the first end of the first transistor; A third transistor, a control end of the third transistor is connected to the driving control node of the nth - stage gate driving module, a first end of the third transistor is connected to the second end of the first transistor, and a second end of the third transistor is connected to a first low - level terminal; A fourth transistor, a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the second end of the second transistor, and a second end of the fourth transistor is connected to the first low - level terminal.

3. The noise reduction circuit according to claim 2, wherein The noise reduction control unit further includes: A fifth transistor, a control end of the fifth transistor is connected to the driving control node of the (n + h)th - stage gate driving module, a first end of the fifth transistor is connected to the second end of the first transistor, and a second end of the fifth transistor is connected to the first low - level terminal; A sixth transistor, a control end of the sixth transistor is connected to the control end of the fifth transistor, a first end of the sixth transistor is connected to the second end of the second transistor, and a second end of the sixth transistor is connected to the first low - level terminal.

4. The noise reduction circuit according to claim 1, wherein The noise reduction execution unit includes: A seventh transistor, a control end of the seventh transistor is connected to the threshold compensation unit, a first end of the seventh transistor is connected to the driving output terminal, and a second end of the seventh transistor is connected to the first low - level terminal; An eighth transistor, a control end of the eighth transistor is connected to a control end of the seventh transistor, a first end of the eighth transistor is connected to the drive control node, and a second end of the eighth transistor is connected to a first low level end; A ninth transistor, a control end of the ninth transistor is connected to a control end of the seventh transistor, a first end of the seventh transistor is connected to the stage transmission output end, and a second end of the seventh transistor is connected to a second low level end.

5. The noise reduction circuit according to claim 4, wherein The threshold compensation unit includes: A storage capacitor, a first end of the storage capacitor is connected to an output end of the noise reduction control unit, and is configured to couple the noise reduction signal; A compensation sub-unit, the compensation sub-unit is respectively connected to a second end of the storage capacitor and the noise reduction execution unit, and is configured to compensate the noise reduction signal according to a threshold voltage of a transistor in the noise reduction execution unit.

6. The noise reduction circuit according to claim 5, wherein The compensation sub-unit includes: A tenth transistor, a control end of the tenth transistor is connected to a stage transmission output end of an n+j-th stage gate driving module, and a first end of the tenth transistor is connected to a stage transmission output end of an n+k-th stage gate driving module; An eleventh transistor, a control end of the eleventh transistor is connected to a second end of the tenth transistor, a first end of the eleventh transistor is connected to a control end of the eleventh transistor, and a second end of the eleventh transistor is connected to a second end of the storage capacitor; A twelfth transistor, a control end of the twelfth transistor is connected to a control end of the tenth transistor, and a first end of the twelfth transistor is connected to a stage transmission output end of an n+l-th stage gate driving module; A thirteenth transistor, a control end of the thirteenth transistor is connected to a second end of the twelfth transistor, a first end of the thirteenth transistor is connected to a second end of the eleventh transistor, and a second end of the thirteenth transistor is connected to a first end of the seventh transistor.

7. The noise reduction circuit according to claim 6, wherein A size of the eleventh transistor is larger than a size of the thirteenth transistor.

8. The noise reduction circuit according to claim 4, wherein A first low level output by the first low level end is less than or greater than a second low level output by the second low level end.

9. A gate driving circuit includes N cascaded gate driving modules, characterized in that, The n-th stage gate driving module includes: A pull-up unit, the pull-up unit is respectively connected to a drive output end of an n-i-th stage gate driving module and a stage transmission output end of the n-i-th stage gate driving module; A pull-down unit, the pull-down unit is connected to a stage transmission output end of an n+j-th stage gate driving module, and the pull-down unit is further connected to the pull-up unit through a drive control node; An output unit, the output unit is respectively connected to a clock signal terminal and the drive control node; The noise reduction circuit according to any one of claims 1-8, the noise reduction circuit is respectively connected to a drive control node, a drive output end and a stage transmission output end of a current stage gate driving module.

10. A display panel includes a display area and a non-display area, and the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to claim 9, and a drive output end of a circuit unit in the gate driving circuit is electrically connected to at least one scanning line.

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