Discharge control circuit and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a discharge control circuit and a display panel, the discharge control circuit comprises a control module, a first discharge module and a second discharge module, the first discharge module is used for discharging the display panel when it is detected that the display panel enters a shutdown state, and the second discharge module is used for discharging the display panel. The first discharging module is used for controlling a plurality of control signal ends of the gate driving circuit to be electrically connected with a first voltage output end of the control module, and the second discharging module is used for discharging the gate driving circuit after the plurality of control signal ends of the gate driving circuit are electrically connected with the first voltage output end of the control module. Controlling a data signal end of the source electrode driving circuit to be electrically connected with a second voltage output end of the control module; therefore, the voltage on the plurality of control signal ends of the gate drive circuit is pulled up to the first target voltage, and then the voltage on the data signal end of the source drive circuit is bound with the second target voltage, so that the problem of splash screen when a discharge function is started during shutdown is solved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a discharge control circuit and a display panel. Background Art

[0002] When a liquid crystal display device is turned off, in order to allow the liquid crystal to fully release charges, the discharge function usually needs to be turned on. Specifically, when the device is turned off, various signals of the display panel (such as clock signal, frame start signal, reset signal, and pull-down control signal, etc.) are all pulled high to a high level, and then quickly discharged to the ground following the high level, to avoid abnormal phenomena such as screen flashing caused by charge residue in the panel leading to liquid crystal polarization; however, when the discharge function is turned on, the data voltage that is decreasing will be coupled and pulled high, causing the pixels in the panel to suddenly light up, resulting in another screen flashing abnormality.

[0003] Therefore, currently there is a problem of screen flashing when the discharge function is turned on during shutdown of the display panel, which affects the shutdown effect of the display panel. Summary of the Invention

[0004] The present application provides a discharge control circuit and a display panel. By raising the voltages on multiple control signal terminals of the gate driving circuit to a first target voltage and then binding the voltage on the data signal terminal of the source driving circuit to a second target voltage, the present application solves the problem of screen flashing when the discharge function is turned on during shutdown.

[0005] In a first aspect, an embodiment of the present application provides a discharge control circuit applied to a display panel. The display panel includes a gate driving circuit and a source driving circuit. The discharge control circuit includes: a control module, the control module includes a first voltage output terminal for outputting a first target voltage and a second voltage output terminal for outputting a second target voltage; a first discharge module, the first discharge module is respectively connected to the first voltage output terminal of the control module and multiple control signal terminals of the gate driving circuit, and is used for controlling the multiple control signal terminals of the gate driving circuit to be electrically connected to the first voltage output terminal of the control module when detecting that the display panel enters the shutdown state, and discharging the voltage on the first voltage output terminal after a first preset duration; wherein, the multiple control signal terminals include a clock signal terminal, a frame start signal terminal, and a pull-down control terminal; a second discharge module, the second discharge module is respectively connected to the second voltage output terminal of the control module, the data signal terminal of the source driving circuit, and the first discharge module, and is used for controlling the data signal terminal of the source driving circuit to be electrically connected to the second voltage output terminal of the control module after the multiple control signal terminals of the gate driving circuit are electrically connected to the first voltage output terminal of the control module, and discharging the voltage on the second voltage output terminal after a second preset duration.

[0006] Optionally, the first discharge module includes: a shutdown detection unit configured to output a first enable signal through a first enable terminal when detecting that the display panel enters a shutdown state; a first transistor, a control terminal of the first transistor is connected to a first control terminal of the control module, and a first terminal of the first transistor is connected to the first enable terminal of the shutdown detection unit; a plurality of second transistors, control terminals of the plurality of second transistors are connected to a second terminal of the first transistor, first terminals of the plurality of second transistors are connected to a first voltage output terminal of the control module, and second terminals of the plurality of second transistors are respectively and electrically connected to a plurality of control signal terminals of the gate driving circuit one by one.

[0007] Optionally, the shutdown detection unit is further configured to output a second enable signal through a second enable terminal after a first preset duration of outputting the first enable signal; the first discharge module further includes: a third transistor, a control terminal of the third transistor is connected to the second enable terminal of the shutdown detection unit, a first terminal of the third transistor is connected to the first voltage output terminal of the control module, and a second terminal of the third transistor is grounded.

[0008] Optionally, the second discharge module includes: a fourth transistor, a control terminal of the fourth transistor is connected to a second terminal of the first transistor, and a first terminal of the fourth transistor is connected to a second control terminal of the control module; a fifth transistor, a control terminal of the fifth transistor is connected to a second terminal of the fourth transistor, and a first terminal of the fifth transistor is connected to a third control terminal of the control module; a sixth transistor, a control terminal of the sixth transistor is connected to a second terminal of the fifth transistor, and a first terminal of the sixth transistor is connected to a data signal terminal of the source driving circuit; a seventh transistor, a control terminal of the seventh transistor is connected to a control terminal of the third transistor, a first terminal of the seventh transistor is connected to a second terminal of the sixth transistor, and a second terminal of the seventh transistor is grounded.

[0009] Optionally, the second discharge module further includes: a first capacitor, a first terminal of the first capacitor is connected to the control terminal of the sixth transistor, and a second terminal of the first capacitor is grounded.

[0010] Optionally, the second discharge module includes: a delay unit, a first end of the delay unit is connected to the first discharge module, and is configured to output a delay control signal after a control signal terminal of the gate driving circuit is electrically connected to a first voltage output terminal of the control module; a fourth transistor, a control end of the fourth transistor is connected to a second end of the delay unit, a first end of the fourth transistor is connected to a second control end of the control module; a fifth transistor, a control end of the fifth transistor is connected to a second end of the fourth transistor, a first end of the fifth transistor is connected to a third control end of the control module; a sixth transistor, a control end of the sixth transistor is connected to a second end of the fifth transistor, a first end of the sixth transistor is connected to a data signal terminal of the source driving circuit; a seventh transistor, a control end of the seventh transistor is connected to a control end of the third transistor, a first end of the seventh transistor is connected to a second end of the sixth transistor, and a second end of the seventh transistor is grounded.

[0011] Optionally, the delay unit includes: a first resistor, a first end of the first resistor is connected to a second end of the first transistor; a second capacitor, a first end of the second capacitor is connected to a second end of the first resistor, and a second end of the second capacitor is connected to a control end of the fourth transistor; a triode, a base of the triode is connected to a first end of the second capacitor, a collector of the triode is connected to a first end of the first resistor, and an emitter of the triode is connected to a second end of the second capacitor; a second resistor, a first end of the second resistor is connected to a base of the triode, and a second end of the second resistor is connected to an emitter of the triode.

[0012] Optionally, the delay unit includes: an exclusive-NOR gate, a first input terminal of the exclusive-NOR gate is connected to a first end of the second transistor, a second input terminal of the exclusive-NOR gate is connected to a second end of the second transistor, and an output terminal of the exclusive-NOR gate is connected to a control end of the fourth transistor.

[0013] Optionally, the delay unit includes: a comparator, a first input terminal of the comparator is connected to a first end of the second transistor, a second input terminal of the comparator is connected to a second end of the second transistor, and an output terminal of the comparator is connected to a control end of the fourth transistor.

[0014] In a second aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area, the display area includes a pixel array; the non-display area includes a gate driving circuit, a source driving circuit, and a discharge control circuit, and the discharge control circuit is electrically connected to the gate driving circuit and the source driving circuit respectively.

[0015] The technical solution provided by the present application has at least the following beneficial effects: When the present application detects that the display panel enters the shutdown state through the first discharge module, it controls a plurality of control signal terminals of the gate driving circuit to be electrically connected to the first voltage output terminal of the control module; then, the second discharge module binds the voltage on the data signal terminal of the source driving circuit to the second target voltage, so that the voltage change of the plurality of control signal terminals has no coupling effect or a small coupling effect on the data voltage, solving the problem of screen flashing when the shutdown discharge function is turned on; finally, the first discharge module and the second discharge module respectively discharge the first voltage output terminal and the second voltage output terminal of the control module, realizing the rapid discharge of the liquid crystal capacitor and parasitic capacitor in the panel, and avoiding the screen flashing problem caused by liquid crystal polarization. Description of the Drawings

[0016] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0017] Figure 1 Shown is a schematic diagram of the sudden change in data voltage coupling in the related art.

[0018] Figure 2 Shown is a schematic structural diagram of a discharge control circuit provided by an embodiment of the present application.

[0019] Figure 3 Shown is a schematic circuit diagram of the first discharge control circuit provided by an embodiment of the present application.

[0020] Figure 4 Shown is a schematic circuit diagram of the second discharge control circuit provided by an embodiment of the present application.

[0021] Figure 5 Shown is a schematic circuit diagram of the third discharge control circuit provided by an embodiment of the present application.

[0022] Figure 6 Shown is a schematic circuit diagram of the fourth discharge control circuit provided by an embodiment of the present application.

[0023] Figure 7 Shown is a schematic circuit diagram of the fifth discharge control circuit provided by an embodiment of the present application.

[0024] Figure 8 Shown is a schematic circuit diagram of the sixth discharge control circuit provided by an embodiment of the present application.

[0025] Description of the Reference Numerals: 100. Discharge control circuit; 110. Control module; 120. First discharge module; 121. Shutdown detection unit; 130. Second discharge module; 131. Delay unit; 200. Gate drive circuit; 300. Source drive circuit; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; Q1. Triode; R1. First resistor; R2. Second resistor; C1. First capacitor; C2. Second capacitor; U1. Exclusive-NOR gate; U2. Comparator; VGH. First voltage output terminal; Vcom. Second voltage output terminal; Y1. First control terminal; Y2. Second control terminal; Y3. Third control terminal; EN1. First enable terminal; EN2. Second enable terminal; EN3. Third enable terminal; Sout. Data signal terminal; CLK. Clock signal terminal; STV. Frame start signal terminal; LC. Pull-down control terminal. Detailed implementation manners

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0027] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of this application. However, those skilled in the art will realize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of this application.

[0028] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0029] When the liquid crystal display device is turned off, the pixel capacitors store charges; if the charges are not actively discharged, the residual charges will cause long-term deflection damage to the liquid crystal molecules, which may cause screen flickering or screen aging; in order to allow the liquid crystal to fully release the charges, the discharge function usually needs to be turned on. Specifically: when the device is turned off, various control signals of the display panel (such as clock signal, frame start signal, reset signal, and pull-down control signal, etc.) are all pulled high to a high level (such as 30V), and then quickly discharged to the ground following the high level; the final result is to pull up the potential of the scan lines in the panel, and at the same time turn on all the pixel transistors in the panel, so that the pixel capacitors can discharge quickly through a unified path, avoiding charge residue in the panel from causing liquid crystal polarization and resulting in abnormal phenomena such as screen flickering. In addition, the discharge function is turned on by recognizing the decrease in the power supply voltage when the device is turned off, that is, when the power supply voltage drops to a certain threshold, the discharge function will be activated.

[0030] The inventors of the present application have found through research that since there is a parasitic capacitance between the scan lines and data lines in the panel, and the data voltage will also drop when the display device is turned off. If the discharge function is turned on during the power-down process of the data voltage, the voltage on the data line will be coupled and pulled up by the rising scan line voltage, as Figure 1 shown. Figure 1 In the figure, VDD represents the power supply voltage, Sout represents the voltage on the data signal terminal of the source driver circuit, and CLK represents the voltage on the clock signal terminal. When the power supply voltage VDD drops to a certain threshold, the discharge function is activated. The clock signal CLK, which is initially at a low potential, will be instantly pulled up to a high potential. At this time, the data voltage that is dropping will be coupled to a high potential, causing the pixels in the panel to suddenly light up, resulting in a serious screen flickering phenomenon; it should be noted that in actual applications, it is the combined action of the clock signal, frame start signal, pull-down control signal, and reset signal in the gate driver circuit that will cause the data voltage to be coupled and mutated. Figure 1 In the figure, only the influence of the change of the clock signal on the data voltage is shown, and the other signals are not shown one by one.

[0031] In order to solve the problem of screen flickering when the pixel discharge function is turned on when the display panel is turned off, the embodiment of the present application provides a discharge control circuit, which specifically includes the following embodiments: Figure 2 The following shows a schematic structural diagram of a discharge control circuit provided by an embodiment of the present application; as Figure 2As shown, the discharge control circuit 100 is applied to a display panel, which includes but is not limited to a gate driver circuit 200, a source driver circuit 300, and a pixel array. Among them, the gate driver circuit 200 provides a gate driving signal that can turn on the scan line for the pixel array, and the source driver circuit 300 provides a data voltage for the pixel array. The gate driver circuit 200 includes multiple control signal terminals, which include but are not limited to a clock signal terminal CLK, a frame start signal terminal STV, a pull-down control terminal LC, and a reset signal terminal. The signals output by each control signal terminal are the same as those in the related art, and will not be elaborated here. In addition, the source driver circuit 300 includes a data signal terminal Sout for outputting the data voltage. In practical applications, the source driver circuit 300 includes multiple data signal terminals Sout, and the functions of each data signal terminal Sout are the same. In this application, all the data signal terminals Sout of the source driver circuit 300 are uniformly referred to as the data signal terminal Sout.

[0032] The discharge control circuit 100 of this application includes a control module 110. The control module 110 includes a first voltage output terminal VGH for outputting a first target voltage and a second voltage output terminal Vcom for outputting a second target voltage. It should be noted that the first target voltage represents the high voltage corresponding to the signals output by the multiple control signal terminals of the gate driver circuit 200, such as 30V; the second target voltage represents the common voltage corresponding to the data voltage, such as 5V. In addition, the control module 110 further includes a first control terminal Y1 for outputting a first control signal, a second control terminal Y2 for outputting a second control signal, and a third control terminal Y3 for outputting a third control signal. The functions of the first control signal, the second control signal, and the third control signal will be described in the following embodiments.

[0033] In this embodiment, the discharge control circuit 100 further includes a first discharge module 120. The first discharge module 120 is respectively connected to the first voltage output terminal VGH of the control module 110 and the multiple control signal terminals of the gate driver circuit 200, and is used to control the multiple control signal terminals of the gate driver circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110 when it is detected that the display panel enters the shutdown state, and discharge the voltage on the first voltage output terminal VGH after a first preset duration.

[0034] It should be noted that before the first discharge module 120 discharges the voltage on the first voltage output terminal VGH of the control module 110, the first voltage output terminal VGH of the control module 110 always outputs the first target voltage; when the first discharge module 120 detects that the display panel starts to enter the shutdown state, the multiple control signal terminals of the gate driving circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110, so that the voltages on the multiple control signal terminals of the gate driving circuit 200 are all raised to the first target voltage; after the voltages on the multiple control signal terminals are raised to the first target voltage for a first preset duration, while the first discharge module 120 discharges the voltage on the first voltage output terminal VGH, the first voltage output terminal VGH of the control module 110 stops outputting the first target voltage, achieving the purpose of discharging the multiple control signal terminals of the gate driving circuit 200, that is, enabling the discharge function, quickly discharging the liquid crystal capacitors and parasitic capacitors in the panel, and preventing liquid crystal polarization. In addition, while the first discharge module 120 discharges the voltage on the first voltage output terminal VGH of the control module 110, the first discharge module 120 sends a feedback signal to the control module 110, and the control module 110 stops outputting the first target voltage according to the feedback signal.

[0035] In this embodiment, the discharge control circuit 100 further includes a second discharge module 130. The second discharge module 130 is respectively connected to the second voltage output terminal Vcom of the control module 110, the data signal terminal Sout of the source driving circuit 300, and the first discharge module 120, and is used to control the data signal terminal Sout of the source driving circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110 after the multiple control signal terminals of the gate driving circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110, and discharge the voltage on the second voltage output terminal Vcom after a second preset duration.

[0036] It should be noted that the second discharge module 130 can obtain the information that multiple control signal terminals of the gate driving circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110 by being connected to the first discharge module 120; after the second discharge module 130 learns that multiple control signal terminals of the gate driving circuit 200 are already electrically connected to the first voltage output terminal VGH of the control module 110, it then controls the data signal terminal Sout of the source driving circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110; therefore, the reason why the pixel brightness does not suddenly change at this time is as follows: (1) After the voltage on multiple control signal terminals of the gate driving circuit 200 is raised to the first target voltage, the voltage on the data signal terminal Sout of the source driving circuit 300 is then bound to the second target voltage, that is to say: when the voltage on multiple control signal terminals is raised to the first target voltage, the data signal terminal Sout is still outputting a stable data voltage, and at this time the data voltage is less affected by coupling; however, if there is no data voltage output at the data signal terminal Sout, the decreasing data voltage will be more affected by coupling; (2) When there is still a stable data voltage output at the data signal terminal Sout, the display panel still has a normal image display at this time. Even if there is a small coupling effect on the data voltage, there will be no obvious brightness change in the display image and it is not obvious to the human eye; however, when the data voltage drops to the black and gray level or close to the black and gray level image and is coupled to a high potential, it will cause the pixels in the panel to emit light significantly, resulting in a flash screen problem that is obvious to the human eye. It can thus be shown that the present application solves the problem of sudden pixel brightness change caused by enabling the discharge function during shutdown by raising the voltage on multiple control signal terminals of the gate driving circuit 200 to the first target voltage and then binding the voltage on the data signal terminal Sout of the source driving circuit 300 to the second target voltage.

[0037] Further, after a first preset duration when the voltage on the data signal terminal Sout is bound to the second target voltage, while the second discharge module 130 discharges the voltage on the second voltage output terminal Vcom, the second voltage output terminal Vcom of the control module 110 stops outputting the second target voltage, achieving the purpose of discharging the data signal terminal Sout of the source driving circuit 300, quickly discharging the liquid crystal capacitance and parasitic capacitance in the panel, and preventing liquid crystal polarization. In addition, while the first discharge module 120 discharges the voltage on the first voltage output terminal VGH of the control module 110, the first discharge module 120 sends a feedback signal to the control module 110, and the control module 110 stops outputting the first target voltage at the first voltage output terminal VGH and stops outputting the second target voltage at the second voltage output terminal Vcom according to the feedback signal.

[0038] In summary, when the first discharge module 120 detects that the display panel enters the shutdown state, the first discharge module 120 controls multiple control signal terminals of the gate driving circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110. Then, the second discharge module 130 binds the voltage on the data signal terminal Sout of the source driving circuit 300 to the second target voltage, so that the voltage change of the multiple control signal terminals has no coupling effect or a small coupling effect on the data voltage, solving the problem of screen flashing when the shutdown turn-on discharge function is present. Finally, the first discharge module 120 and the second discharge module 130 respectively discharge the first voltage output terminal VGH and the second voltage output terminal Vcom of the control module 110, realizing rapid discharge of the liquid crystal capacitor and parasitic capacitor in the panel, and avoiding the screen flashing problem caused by liquid crystal polarization.

[0039] Figure 3 The following shows a circuit schematic diagram of the first discharge control circuit provided by an embodiment of the present application; as Figure 3 shown, the first discharge module 120 of this embodiment includes a shutdown detection unit 121, a first transistor T1, and multiple second transistors T2. The shutdown detection unit 121 is configured to output a first enable signal through the first enable terminal EN1 when detecting that the display panel enters the shutdown state. The control terminal of the first transistor T1 is connected to the first control terminal Y1 of the control module 110, and the first terminal of the first transistor T1 is connected to the first enable terminal EN1 of the shutdown detection unit 121. The control terminals of the multiple second transistors T2 are connected to the second terminal of the first transistor T1, the first terminals of the multiple second transistors T2 are connected to the first voltage output terminal VGH of the control module 110, and the second terminals of the multiple second transistors T2 are respectively and electrically connected to multiple control signal terminals of the gate driving circuit 200.

[0040] Optionally, the shutdown detection unit 121 is further configured to output a second enable signal through the second enable terminal EN2 after a first preset duration of outputting the first enable signal.

[0041] Optionally, the first discharge module 120 further includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the second enable terminal EN2 of the shutdown detection unit 121, the first terminal of the third transistor T3 is connected to the first voltage output terminal VGH of the control module 110, and the second terminal of the third transistor T3 is grounded.

[0042] In addition, the turn-on voltage of the first transistor T1 can be at a low level. It can be understood that the first transistor T1 is a P-type MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor. The turn-on voltage of the second transistor T2 can be at a high level. It can be understood that the second transistor T2 is an N-type MOS transistor. Conversely, the first transistor T1 can also be an N-type MOS transistor, and the second transistor T2 can also be a P-type MOS transistor. The specific types of transistors in this application can be flexibly configured according to the actual application scenario.

[0043] Taking the first transistor T1 as a P-type MOS transistor, the second transistor T2 as an N-type MOS transistor, and the third transistor T3 as an N-type MOS transistor as an example, the specific working principle of the first discharge module 120 is described as follows: (1) The shutdown detection unit 121 determines whether the display panel enters the shutdown state by detecting in real time whether the power supply voltage is less than or equal to the threshold voltage. When it detects that the power supply voltage drops to the threshold voltage, it determines that the display panel enters the shutdown state and outputs a first enable signal with a high level through the first enable terminal EN1. At the same time, the first control terminal Y1 of the control module 110 outputs a low level to turn on the first transistor T1. The first enable signal with a high level acts on the control terminals of multiple second transistors T2 through the turned-on first transistor T1, and multiple second transistors T2 are turned on simultaneously, so that multiple control signal terminals of the gate driving circuit 200 are electrically connected to the first output terminal of the control module 110 through the turned-on second transistors T2, thereby realizing the function that the first discharge module 120 controls multiple control signal terminals of the gate driving circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110 when it detects that the display panel enters the shutdown state.

[0044] (2) After pulling up the voltage of multiple control signal terminals to the first target voltage, that is, after a first preset time period after the shutdown detection unit 121 outputs the first enable signal, a second enable signal with a high level is output through the second enable terminal EN2 to turn on the third transistor T3. At the same time, the third enable terminal EN3 of the shutdown detection unit 121 is also connected to the control module 110 and is used to output a third enable signal to the control module 110. The control module 110 stops outputting the first target voltage at the first voltage output terminal VGH according to the third enable signal, realizing the function that the first discharge module 120 discharges the voltage at the first voltage output terminal VGH and the voltages at multiple control signal terminals simultaneously after the first preset time period.

[0045] Such as Figure 3As shown, the second discharge module 130 of this embodiment includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The control terminal of the fourth transistor T4 is connected to the second terminal of the first transistor T1, and the first terminal of the fourth transistor T4 is connected to the second control terminal Y2 of the control module 110. The control terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4, and the first terminal of the fifth transistor T5 is connected to the third control terminal Y3 of the control module 110. The control terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, and the first terminal of the sixth transistor T6 is connected to the data signal terminal Sout of the source driver circuit 300. The control terminal of the seventh transistor T7 is connected to the control terminal of the third transistor T3, the first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6, and the second terminal of the seventh transistor T7 is grounded.

[0046] It should be noted that in this embodiment, taking the fourth transistor T4 as an N-type MOS transistor, the fifth transistor T5 as a P-type MOS transistor, the sixth transistor T6 as an N-type MOS transistor, and the seventh transistor T7 as an N-type MOS transistor as examples, the working principle of the second discharge module 130 of this embodiment is described as follows: (1) After the first transistor T1 is turned on, the first enable signal output by the shutdown detection unit 121 acts on the control terminal of the fourth transistor T4 in the second discharge module 130 through the turned-on first transistor T1, and the fourth transistor T4 is turned on, so that the low level output by the second control terminal Y2 of the control module 110 turns on the fifth transistor T5. Further, the high level output by the third control terminal Y3 of the control module 110 turns on the sixth transistor T6, realizing the function of electrically connecting the data signal terminal Sout of the source driver circuit 300 to the second voltage output terminal Vcom of the control module 110. Since the high level output by the first transistor T1 can realize the electrical connection between the multiple control signal terminals of the gate driver circuit 200 and the first voltage output terminal VGH of the control module 110 through one transistor (i.e., the second transistor T2), however, the high level output by the first transistor T1 needs to pass through three transistors (i.e., the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6) to realize the electrical connection between the data signal terminal Sout of the source driver current and the second voltage output terminal Vcom of the control module 110. The conduction time of the three transistors will be longer than that of one transistor. Therefore, after realizing the electrical connection between the multiple control signal terminals of the gate driver circuit 200 and the first voltage output terminal VGH of the control module 110, the function of controlling the electrical connection between the data signal terminal Sout of the source driver circuit 300 and the second voltage output terminal Vcom of the control module 110 is realized.

[0047] (2) The second enable signal output by the shutdown detection unit 121 turns on the seventh transistor T7; at the same time, under the action of the third enable signal output by the control module 110, the first voltage output terminal VGH and the second voltage output terminal Vcom stop outputting the first target voltage and the second target voltage respectively, so as to realize the function that the second discharge module 130 discharges the voltage on the second voltage output terminal Vcom and the voltage on the data signal terminal Sout simultaneously after a second preset time.

[0048] Figure 4 The figure shows a schematic circuit diagram of a second discharge control circuit provided by an embodiment of the present application; Figure 4 On the basis of Figure 3 the second discharge module 130 adds a first capacitor C1; specifically as Figure 4 shown, the second discharge module 130 further includes: a first capacitor C1, the first end of the first capacitor C1 is connected to the control end of the sixth transistor T6, and the second end of the first capacitor C1 is grounded.

[0049] It should be noted that in this embodiment, by setting the first capacitor C1 at the control end of the sixth transistor T6, the opening time of the sixth transistor T6 can be delayed, so that after the control signal terminals of the gate driving circuit 200 are pulled high by the voltage output from the first voltage output terminal VGH of the control module 110, the data signal terminal Sout of the source driving circuit 300 is controlled to be electrically connected to the second voltage output terminal Vcom of the control module 110, effectively avoiding the problem of the data voltage in decline being coupled and mutated.

[0050] Figure 5 The figure shows a schematic circuit diagram of a third discharge control circuit provided by an embodiment of the present application; Figure 5 On the basis of Figure 3 the input end of the second discharge module 130 adds a delay unit 131; as Figure 5 shown, the second discharge module 130 of this embodiment includes a delay unit 131, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0051] Specifically, the first end of the delay unit 131 is connected to the first discharge module 120, and is configured to output a delay control signal after the control signal terminal of the gate driving circuit 200 is electrically connected to the first voltage output terminal VGH of the control module 110; the control terminal of the fourth transistor T4 is connected to the second end of the delay unit 131, the first end of the fourth transistor T4 is connected to the second control terminal Y2 of the control module 110; the control terminal of the fifth transistor T5 is connected to the second end of the fourth transistor T4, the first end of the fifth transistor T5 is connected to the third control terminal Y3 of the control module 110; the control terminal of the sixth transistor T6 is connected to the second end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the data signal terminal Sout of the source driving circuit 300; the control terminal of the seventh transistor T7 is connected to the control terminal of the third transistor T3, the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, and the second end of the seventh transistor T7 is grounded.

[0052] It should be noted that the function of the delay unit 131 in this embodiment is the same as that of Figure 4 the first capacitor C1 in [reference]: both are to delay the conduction time of the sixth transistor T6 and provide sufficient buffer time for the voltages of multiple control signal terminals of the gate driving circuit 200 to be raised to the second target voltage; Figure 4 the first capacitor C1 in [reference] is arranged at the control terminal of the sixth transistor T6, while the delay unit 131 in this embodiment is arranged at the input end of the second discharge module 130; the delay unit 131 outputs a delay control signal for controlling the fourth transistor T4 after the control signal terminal of the gate driving circuit 200 is electrically connected to the first voltage output terminal VGH of the control module 110, which has a certain delay time compared to Figure 3 directly obtaining the delay control signal for controlling the fourth transistor T4 from the second end of the first transistor T1 in [reference]. In addition, the functions and working principles of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in this embodiment are the same as those in Figure 3 [reference], and will not be elaborated here.

[0053] Figure 6 The circuit schematic diagram of the fourth discharge control circuit provided by the embodiment of the present application is shown; Figure 6 shows Figure 5 a specific implementation manner of the delay unit 131 in [reference], as shown in Figure 6As shown: The delay unit 131 includes a first resistor R1, a second capacitor C2, a triode Q1, and a second resistor R2. The first end of the first resistor R1 is connected to the second end of the first transistor T1; the first end of the second capacitor C2 is connected to the second end of the first resistor R1, and the second end of the second capacitor C2 is connected to the control end of the fourth transistor T4; the base of the triode Q1 is connected to the first end of the second capacitor C2, the collector of the triode Q1 is connected to the first end of the first resistor R1, and the emitter of the triode Q1 is connected to the second end of the second capacitor C2; the first end of the second resistor R2 is connected to the base of the triode Q1, and the second end of the second resistor R2 is connected to the emitter of the triode Q1.

[0054] It should be noted that when the first transistor T1 conducts and outputs a high level, multiple second transistors T2 will immediately conduct, causing the voltages of multiple control signal terminals to be gradually pulled up to the first target voltage; at the same time, the high level output by the first transistor T1 charges the second capacitor C2 through the first resistor R1. When the voltage of the second capacitor C2 reaches the conduction voltage of the triode after a certain time, the triode Q1 conducts, and then the high level output by the first transistor T1 can be given to the control end of the fourth transistor T4, and then the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on in sequence, thereby realizing that the data signal terminal Sout is delayed and pulled down to the second target voltage; the delay time is determined by the capacitance value of the second capacitor C2. The larger the capacitance value, the longer the charging time, and the charging time is the delay time. The delay time can be set according to the actual situation.

[0055] Figure 7 The following shows a circuit schematic diagram of the fifth discharge control circuit provided by the embodiment of the present application; Figure 7 Shows Figure 5 Another specific implementation of the delay unit 131 in Figure 7 As shown, the delay unit 131 includes: an exclusive-NOR gate. The first input end of the exclusive-NOR gate is connected to the first end of the second transistor T2, the second input end of the exclusive-NOR gate is connected to the second end of the second transistor T2, and the output end of the exclusive-NOR gate is connected to the control end of the fourth transistor T4.

[0056] It should be noted that in this embodiment, voltage detection and determination are performed through an exclusive-NOR gate. The two input terminals of the exclusive-NOR gate are respectively connected to the first voltage output terminal VGH of the control module 110 and the control signal terminal of the gate driving circuit 200. The output terminal of the exclusive-NOR gate controls the opening and closing of the fourth transistor T4. When the voltage at the control signal terminal of the gate driving circuit 200 is not pulled up to the first target voltage, the voltages at the two input terminals of the exclusive-NOR gate are different, so the exclusive-NOR gate outputs a low level, making it impossible for the fourth transistor T4 to conduct, and the voltage at the data signal terminal Sout of the source driving circuit 300 remains unchanged. After the voltage at the control signal terminal of the gate driving circuit 200 is pulled up to the first target voltage, the voltages at the two input terminals of the exclusive-NOR gate are the same, so the exclusive-NOR gate outputs a high level, causing the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to conduct in sequence, and the voltage at the data signal terminal Sout of the source driving circuit 300 changes following the second target voltage, thus avoiding the coupling mutation of the changing data voltage.

[0057] Figure 8 FIG. shows a schematic circuit diagram of a sixth discharge control circuit provided by an embodiment of the present application; Figure 8 shows Figure 5 Another specific implementation manner of the delay unit 131 in Figure 8 As shown, the delay unit 131 includes: a comparator. The first input terminal of the comparator is connected to the first end of the second transistor T2, the second input terminal of the comparator is connected to the second end of the second transistor T2, and the output terminal of the comparator is connected to the control terminal of the fourth transistor T4.

[0058] It should be noted that in this embodiment, voltage detection and determination are performed through a comparator. The two input terminals of the comparator are respectively connected to the first voltage output terminal VGH of the control module 110 and the control signal terminal of the gate driving circuit 200. The output terminal of the comparator controls the opening and closing of the fourth transistor T4. When the voltage at the control signal terminal of the gate driving circuit 200 is not pulled up to the first target voltage, the voltages at the two input terminals of the comparator are different, so the exclusive-NOR gate outputs a low level, making it impossible for the fourth transistor T4 to conduct, and the voltage at the data signal terminal Sout of the source driving circuit 300 remains unchanged. After the voltage at the control signal terminal of the gate driving circuit 200 is pulled up to the first target voltage, the voltages at the two input terminals of the comparator are the same, so the comparator outputs a high level, causing the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to conduct in sequence, and the voltage at the data signal terminal Sout of the source driving circuit 300 changes following the second target voltage, thus avoiding the coupling mutation of the changing data voltage.

[0059] In another embodiment, the present application can also be in Figure 6 , Figure 7 and Figure 8Based on the shown delay unit 131, a first capacitor C1 is added to the control terminal of the sixth transistor T6, which can further control the turn-on time of the sixth transistor T6.

[0060] In summary, in the present application, after raising the voltages on multiple control signal terminals of the gate driving circuit 200 to a first target voltage, the voltage on the data signal terminal Sout of the source driving circuit 300 is then bound to a second target voltage, thereby solving the problem of screen flickering when the discharge function is turned on during shutdown.

[0061] In a second aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a gate driving circuit, a source driving circuit, and a discharge control circuit, and the discharge control circuit is electrically connected to the gate driving circuit and the source driving circuit respectively.

[0062] In addition, terms such as "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically and clearly defined.

[0063] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0064] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the description of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A discharge control circuit, characterized in that, Applied to a display panel, the display panel includes a gate driving circuit and a source driving circuit, and the discharge control circuit includes: A control module, the control module includes a first voltage output terminal for outputting a first target voltage and a second voltage output terminal for outputting a second target voltage; A first discharge module, the first discharge module is respectively connected to the first voltage output terminal of the control module and multiple control signal terminals of the gate driving circuit, and is used for controlling the multiple control signal terminals of the gate driving circuit to be electrically connected to the first voltage output terminal of the control module when it is detected that the display panel enters the shutdown state, and discharging the voltage on the first voltage output terminal after a first preset time period; wherein, the multiple control signal terminals include a clock signal terminal, a frame start signal terminal, and a pull-down control terminal; A second discharge module, the second discharge module is respectively connected to the second voltage output terminal of the control module, the data signal terminal of the source driving circuit, and the first discharge module, and is used for controlling the data signal terminal of the source driving circuit to be electrically connected to the second voltage output terminal of the control module after the multiple control signal terminals of the gate driving circuit are electrically connected to the first voltage output terminal of the control module, and discharging the voltage on the second voltage output terminal after a second preset time period.

2. The discharge control circuit according to claim 1, characterized in that, The first discharge module includes: A shutdown detection unit, configured to output a first enable signal through a first enable terminal when it is detected that the display panel enters the shutdown state; A first transistor, the control terminal of the first transistor is connected to the first control terminal of the control module, and the first terminal of the first transistor is connected to the first enable terminal of the shutdown detection unit; Multiple second transistors, the control terminals of the multiple second transistors are connected to the second terminal of the first transistor, the first terminals of the multiple second transistors are connected to the first voltage output terminal of the control module, and the second terminals of the multiple second transistors are respectively electrically connected to the multiple control signal terminals of the gate driving circuit one by one.

3. The discharge control circuit according to claim 2, wherein The shutdown detection unit is further configured to output a second enable signal through a second enable terminal after a first preset time period of outputting the first enable signal; The first discharge module further includes: a third transistor, the control terminal of the third transistor is connected to the second enable terminal of the shutdown detection unit, the first terminal of the third transistor is connected to the first voltage output terminal of the control module, and the second terminal of the third transistor is grounded.

4. The discharge control circuit according to claim 3, wherein The second discharge module includes: A fourth transistor, the control terminal of the fourth transistor is connected to the second terminal of the first transistor, and the first terminal of the fourth transistor is connected to the second control terminal of the control module; A fifth transistor, the control terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the first terminal of the fifth transistor is connected to the third control terminal of the control module; A sixth transistor, the control terminal of the sixth transistor is connected to the second terminal of the fifth transistor, and the first terminal of the sixth transistor is connected to the data signal terminal of the source driving circuit; A seventh transistor, a control terminal of the seventh transistor is connected to a control terminal of the third transistor, a first terminal of the seventh transistor is connected to a second terminal of the sixth transistor, and a second terminal of the seventh transistor is grounded.

5. The discharge control circuit according to claim 4, characterized in that, The second discharge module further includes: A first capacitor, a first terminal of the first capacitor is connected to a control terminal of the sixth transistor, and a second terminal of the first capacitor is grounded.

6. The discharge control circuit according to claim 3, characterized in that, The second discharge module includes: A delay unit, a first terminal of the delay unit is connected to the first discharge module, and is configured to output a delay control signal after a control signal terminal of the gate driving circuit is electrically connected to a first voltage output terminal of the control module; A fourth transistor, a control terminal of the fourth transistor is connected to a second terminal of the delay unit, and a first terminal of the fourth transistor is connected to a second control terminal of the control module; A fifth transistor, a control terminal of the fifth transistor is connected to a second terminal of the fourth transistor, and a first terminal of the fifth transistor is connected to a third control terminal of the control module; A sixth transistor, a control terminal of the sixth transistor is connected to a second terminal of the fifth transistor, and a first terminal of the sixth transistor is connected to a data signal terminal of the source driving circuit; A seventh transistor, a control terminal of the seventh transistor is connected to a control terminal of the third transistor, a first terminal of the seventh transistor is connected to a second terminal of the sixth transistor, and a second terminal of the seventh transistor is grounded.

7. The discharge control circuit according to claim 6, wherein The delay unit includes: A first resistor, a first terminal of the first resistor is connected to a second terminal of the first transistor; A second capacitor, a first terminal of the second capacitor is connected to a second terminal of the first resistor, and a second terminal of the second capacitor is connected to a control terminal of the fourth transistor; A triode, a base of the triode is connected to a first terminal of the second capacitor, a collector of the triode is connected to a first terminal of the first resistor, and an emitter of the triode is connected to a second terminal of the second capacitor; A second resistor, a first terminal of the second resistor is connected to a base of the triode, and a second terminal of the second resistor is connected to an emitter of the triode.

8. The discharge control circuit according to claim 6, wherein The delay unit includes: An exclusive-NOR gate, a first input terminal of the exclusive-NOR gate is connected to a first terminal of the second transistor, a second input terminal of the exclusive-NOR gate is connected to a second terminal of the second transistor, and an output terminal of the exclusive-NOR gate is connected to a control terminal of the fourth transistor.

9. The discharge control circuit according to claim 6, wherein The delay unit includes: A comparator, a first input terminal of the comparator is connected to a first terminal of the second transistor, a second input terminal of the comparator is connected to a second terminal of the second transistor, and an output terminal of the comparator is connected to a control terminal of the fourth transistor.

10. A display panel, comprising a display area and a non-display area, characterized in that, The display area includes a pixel array; The non-display area includes a gate driving circuit, a source driving circuit, and the discharge control circuit according to any one of claims 1-9, and the discharge control circuit is electrically connected to the gate driving circuit and the source driving circuit respectively.

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