Memory device including in-memory operation

Abstract

A memory device including an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including bit cells, and a method of operating the same are provided. Each of the plurality of bit cells includes a first transistor having one end connected to a corresponding write bit line, another end connected to a storage node, and a gate terminal connected to a write word line, and at least one second transistor having the other end connected to a storage node. And at least one second transistor, one end of which is connected to the read bit line, the other end of which is connected to the read word line, and a gate terminal of which is connected to the storage node. A current value of an on current of at least one second transistor included in each bit cell corresponds to a value obtained by multiplying a reference current value by a power of 2, the power of 2 being different for each bit cell.

Description

Technical Field

[0001] The inventive concept relates to a memory device, and more particularly, to a memory device that performs a compute-in-memory (CIM) function and an operating method thereof. Background Art

[0002] Artificial intelligence technologies using artificial neural networks are revolutionizing by demonstrating excellent accuracy in fields such as image recognition and natural language processing.

[0003] Since these artificial intelligence technologies require a huge amount of computation, CIM technologies that can perform some computations in memory are attracting attention.

[0004] To implement a CIM device, various devices that can perform both a memory function and a computing function are being studied. Summary of the Invention

[0005] The inventive concept provides a memory device that performs an internal computing operation using an internal multiplier of a memory including a plurality of bit cells having different on-currents and an operating method thereof.

[0006] According to an aspect of the inventive concept, there is provided a memory device including an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including a plurality of bit cells, wherein each of the plurality of bit cells includes: a first transistor having one end connected to a corresponding one of the plurality of write bit lines, the other end connected to a storage node, and a gate terminal connected to the write word line; and at least one second transistor having one end connected to the read bit line, the other end connected to the read word line, and a gate terminal connected to the storage node. A current value of an on-current of the at least one second transistor included in each of the plurality of bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2, and the power of 2 is different for each of the plurality of bit cells.

[0007] According to another aspect of the inventive concept, there is provided a method of operating a memory device including a plurality of bit cells, each of the plurality of bit cells including a first transistor and at least one second transistor, one end of the first transistor being connected to a corresponding one of a plurality of write bit lines, the other end of the first transistor being connected to a storage node, and a gate terminal of the first transistor being connected to a write word line, one end of the at least one second transistor being connected to a read bit line, the other end of the at least one second transistor being connected to a read word line, and a gate terminal of the at least one second transistor being connected to the storage node, and the at least one second transistor providing different on-currents for the plurality of bit cells. The method includes performing a multiplication operation of first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells. Performing the multiplication operation includes: applying a cut-off voltage to the write word line in a first time period; applying a ground voltage to the read word line in a second time period; and applying a voltage having an amplitude associated with the second operation target data to the read bit line in a third time period.

[0008] According to another aspect of the inventive concept, there is provided a method of operating a memory device including a plurality of bit cells, each of the plurality of bit cells including a first transistor and at least one second transistor, one end of the first transistor being connected to a corresponding one of a plurality of write bit lines, the other end of the first transistor being connected to a storage node, and a gate terminal of the first transistor being connected to a write word line, one end of the at least one second transistor being connected to a read bit line, the other end of the at least one second transistor being connected to a read word line, and a gate terminal of the at least one second transistor being connected to the storage node, and the at least one second transistor providing different on-currents for the plurality of bit cells. The method includes performing a multiplication operation of first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells. Performing the multiplication operation includes: applying a cut-off voltage to the write word line in a first time period; applying a read bit line voltage to the read bit line in a second time period; and applying a pulse voltage to the read word line in a third time period, the pulse voltage maintaining a ground voltage level during a pulse time period having a length proportional to a magnitude of the second operation target data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating a semiconductor system according to an embodiment; Figure 2A and Figure 2B and Figure 3AAnd Figure 3B is a circuit diagram illustrating a bit cell according to an exemplary embodiment; Figure 4A And Figure 4B is a circuit diagram illustrating the structure of a multiplier within a memory according to an exemplary embodiment; Figure 5 is a circuit of an analog-to-digital converter according to an embodiment; Figure 6 And Figure 7 is a timing diagram showing a write operation according to an exemplary embodiment; Figure 8 is a diagram illustrating a write operation for first operation target data according to an exemplary embodiment; Figure 9 is a circuit diagram illustrating a refresh operation according to an embodiment; Figure 10 is according to an embodiment Figure 9 timing diagram of the refresh operation; Figure 11 is a circuit diagram of a multiplication operation according to an embodiment; Figure 12 is to illustrate according to an embodiment Figure 11 timing diagram of the multiplication operation; Figure 13 is a circuit diagram illustrating a multiplication operation between a binary number and a decimal number according to an embodiment; Figure 14 is a circuit diagram illustrating a multiplication operation according to an embodiment; Figure 15 is a diagram illustrating according to an embodiment Figure 14 timing diagram of the multiplication operation; Figure 16 is a circuit diagram illustrating a multiplication operation between a binary number and a decimal number according to an embodiment; Figure 17 And Figure 18 is a timing diagram illustrating a read operation according to an exemplary embodiment. DETAILED DESCRIPTION

[0010] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram showing a semiconductor system according to an embodiment.

[0012] Referring to Figure 1 , a semiconductor system 1 according to an embodiment may include a host device 10 and a memory device 20.

[0013] The host device 10 can be, for example, a computing system such as a computer, a laptop computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device. Alternatively, the host device 10 can be one of the components included in a computing system, such as a graphics card.

[0014] The host device 10 is a functional block that operates as a general-purpose computer within the semiconductor system 1 and can include a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or an application processor (AP). The host device 10 can include a memory controller 11 that manages sending data to and receiving data from the memory device 20.

[0015] The memory controller 11 can access the memory device 20 in response to a memory request from the host device 10. For example, the memory controller 11 can access an in-memory multiplier (IMM) 21 included in the memory device 20 by providing an address, a command, and data to the memory device 20. The memory controller 11 can control a write operation, a multiplication operation, a refresh operation, or a read operation on the IMM 21. In this specification, the IMM 21 can be referred to as an in-memory arithmetic circuit.

[0016] In some embodiments, the memory controller 11 can access a memory cell array 22 included in the memory device 20 by providing an address, a command, and data to the memory device 20.

[0017] The memory device 20 can write data or read data under the control of the memory controller 11. For example, the memory device 20 can be a double data rate synchronous dynamic random access memory (DDR SDRAM) device. However, the scope of the inventive concept is not limited thereto, and the memory device 20 can be any one of volatile memory devices such as low power double data rate (LPDDR) SDRAM, wide I / O DRAM, high bandwidth memory (HBM), hybrid memory cube (HMC), etc. According to an embodiment, the memory device 20 can be any one of non-volatile memory devices such as flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0018] The memory device 20 can be an in-memory computing (CIM) device or an in-memory processing (PIM) device that performs internal operations under the control of the host device 10.

[0019] The memory device 20 may include an IMM 21, a memory cell array 22, a voltage generator 23, an analog-to-digital converter (ADC) 24, a word line driver 25, and a bit line sense amplifier (BLSA) 26.

[0020] The IMM 21 may perform a write operation, a read operation, a refresh operation, or a multiplication operation on target data. The IMM 21 may be connected to a write word line WWL, a plurality of write bit lines WBL, a read word line RWL, and a read bit line RBL. The IMM 21 may operate in a processing mode.

[0021] The memory cell array 22 may store data provided from the memory controller 11 or provide data requested by the memory controller 11. Although not shown, the memory cell array 22 may be connected to bit lines and word lines. The memory cell array 22 may operate in a normal mode.

[0022] The memory controller 11 may access the IMM 21 or the memory cell array 22 through an address. However, the present invention is not limited thereto, and the IMM 21 may be included in the memory cell array 22, and a part of the memory cell array 22 may operate as the IMM 21.

[0023] Each of the IMM 21 and the memory cell array 22 may include a plurality of memory cells. The IMM 21 and the memory cell array 22 may include 2 transistor 0 capacitor (2T0C) cells or 2 transistor 1 capacitor (2T1C) cells, but the present invention is not limited thereto. The memory cells included in the IMM 21 may be referred to as bit cells. A multiplication operation may be performed on the data stored in the bit cells.

[0024] The voltage generator 23 may generate voltages applied to the write word line WWL, the write bit lines WBL, the read word line RWL, and the read bit line RBL of the IMM 21.

[0025] The ADC 24 may detect a current value of a current output from the read word line RWL, and based on the detected current value, may acquire data stored in the IMM 21 or data corresponding to a result of a multiplication operation performed by the IMM 21.

[0026] During a write operation, the IMM 21 may store first operation target data in a plurality of bit cells included in the IMM 21 based on voltages provided from a plurality of write bit lines WBL. For example, when a first write word line voltage (e.g., Figure 6 V in WBL1 ) is applied to the write bit line WBL, a “1” may be stored in the bit cell, and when a second write bit line voltage (e.g., Figure 6 V in WBL2When applied to the write bit line WBL, a "0" can be stored in the bit cell. The write operation will be described in more detail with reference to Figures 6 to 8 below.

[0027] The multiple bit cells included in the IMM 21 can output a conduction current according to the first operation target data. Specifically, each of the multiple bit cells can be turned on or off according to the first operation target data stored in each of the multiple bit cells. For example, when "1" is stored in the bit cell, the bit cell can be turned on, and when "0" is stored in the bit cell, the bit cell can be turned off.

[0028] The current values of the conduction currents output from the multiple bit cells can be different. The current values of the conduction currents output from the multiple bit cells can correspond to the product of a reference current value and a power of 2. For example, the current value of the conduction current output from the first bit cell can correspond to the product of the reference current value and 2 0 = 1, the current value of the conduction current output from the second bit cell can correspond to the product of the reference current value and 2 1 and the current value of the conduction current output from the third bit cell can correspond to the product of the reference current value and 2 2 and the current value of the conduction current output from the fourth bit cell can correspond to the product of the reference current value and 2 3 The reference current value can mean the current value of the conduction current output from the first bit cell. Therefore, the current value of the conduction current output from a specific bit cell can represent the digital value of the digit corresponding to that bit cell among the binary numbers indicated by the first operation target data. For example, when the first to fourth bit cells store a four-bit binary number, the first bit cell stores the least significant bit (LSB) and the fourth bit cell stores the most significant bit (MSB), the current value of the conduction current output from the first bit cell can represent 2 0 and the current value of the conduction current output from the fourth bit cell can represent 2 3 .

[0029] In some embodiments, the channel width-to-length ratio W / L ratio of the read transistors (e.g., Figure 2A and Figure 2B Rtr in) included in the multiple bit cells can correspond to the product of a reference channel width-to-length ratio and a power of 2. For example, the channel width-to-length ratio of the read transistor included in the first bit cell can correspond to the value obtained by multiplying the reference channel width-to-length ratio by 2 0 = 1, the channel width-to-length ratio of the read transistor included in the second bit cell can correspond to the value obtained by multiplying the reference channel width-to-length ratio by 2 1 and the channel width-to-length ratio of the read transistor included in the third bit cell can correspond to the value obtained by multiplying the reference channel width-to-length ratio by 2 2corresponds to the obtained value, and the channel width-to-length ratio of the read transistor included in the fourth bit cell can be obtained by multiplying the reference channel width-to-length ratio by 2 3 corresponds to the obtained value. The reference channel width-to-length ratio can represent the channel width-to-length ratio of the read transistor included in the first bit cell. Reference may be made to Figure 2A and Figure 3A for a description of the structure of a bit cell that performs an internal calculation operation based on the channel width-to-length ratio.

[0030] In some embodiments, each of the plurality of bit cells may include read transistors connected in parallel in a power of 2. The channel width-to-length ratio of the read transistors included in each of the plurality of bit cells may be the same. For example, the first bit cell may include 2 0 = 1 read transistor, the second bit cell may include 2 1 = 2 read transistors, the third bit cell may include 2 2 = 4 read transistors, and the fourth bit cell may include 2 3 = 8 read transistors. Reference may be made to Figure 2B and Figure 3B for a description of the structure of a bit cell that performs an internal calculation operation based on read transistors whose number of parallel connections corresponds to a power of 2.

[0031] During the multiplication operation, the IMM 21 may perform a multiplication operation on the first operation target data and the second operation target data based on voltages corresponding to the stored first operation target data and the second operation target data provided via the read bit line RBL or the read word line RWL by the voltage generator 23. In some embodiments, when the second operation target data is A, the voltage generator 23 may supply A×V READ to the read bit line RBL, and the IMM 21 may output, via the read word line RWL, a current whose value corresponds to the product of the reference current value, the first operation target data, and A. In some embodiments, when the second operation target data is A, the voltage generator 23 may supply a negative pulse voltage having a cut-off voltage level within A time to the read word line RWL, and the IMM 21 may output, via the read word line RWL, a current whose value corresponds to the value obtained by multiplying the reference current value, the first operation target data, and A. The multiplication operation will be described in detail below with reference to Figures 11 to 16

[0032] ​The ADC 24 can detect the current from the read word line RWL and obtain binary number data corresponding to the product of the first operation target data and A from the current value of the detected current. However, the operation of the ADC 24 is not limited to this. For example, the ADC 24 can obtain binary number data corresponding to the product of the first operation target data and A based on the reduced voltage level of the read bit line RBL while outputting a current through the read word line RWL after precharging the read bit line RBL. For example, the ADC 24 can include at least one capacitor and obtain binary number data corresponding to the product of the first operation target data and A by detecting the voltage of the capacitor. The following can refer to Figure 5 an example describing the operation of the ADC 24.

[0033] During a read operation, the IMM 21 can output the sum of the conduction currents output from multiple bit cells to the read word line RWL by selectively turning on the read transistors of the multiple bit cells according to the first operation target data. The ADC 24 can obtain the first operation target data corresponding to the read result based on the sum of the conduction currents. The read operation can be an example of a multiplication operation. Specifically, the multiplication operation when the second operation target data is "1" can be understood as a read operation. The following can refer to Figure 17 and Figure 18 describe the read operation in detail.

[0034] During a refresh operation, the memory device 20 can keep the first operation target data stored in the storage nodes of each of the multiple bit cells. Specifically, the memory device 20 can include multiple bit line sense amplifiers (e.g., Figure 9 SA0 to SA N-1 ) connected to multiple write bit lines WBL, and can perform a refresh operation based on the multiple bit line sense amplifiers. The following can refer to Figure 9 and Figure 10 describe the refresh operation in detail.

[0035] The word line driver 25 can apply a voltage generated from the voltage generator 23 to the write word line WWL or the read word line RWL.

[0036] The BLSA 26 can apply a voltage generated from the voltage generator 23 to the write bit line WBL or the read bit line RBL.

[0037] The memory device 20 according to an embodiment can perform a write operation, a read operation, a refresh operation, and a multiplication operation through the IMM 21, thereby reducing the calculation burden of the host device 10.

[0038] In addition, even if the process in which the host device 10 receives the first operation target data from the memory device 20 is omitted, the multiplication operation on the first operation target data can be executed within the memory device 20, and thus the bottleneck phenomenon caused by the operation data can be solved.

[0039] Figure 2A , Figure 2B , Figure 3A and Figure 3B illustrate bit cells BC i and BC i ' according to an exemplary embodiment.

[0040] During a write operation, Figure 1 's IMM 21 can store the first operation target data. Referring to Figure 2A , the bit corresponding to the i-th bit of the first operation target data can be stored in the storage node Q of the bit cell BC i .

[0041] The bit cell BC i may include a write transistor Wtr and a read transistor Rtr. For example, the bit cell BC i may have a 2T0C structure. At least one of the write transistor Wtr and the read transistor Rtr may include a channel containing indium gallium zinc oxide (IGZO). However, the present invention is not limited thereto, and the channels of the write transistor Wtr and the read transistor Rtr may include various materials. One end of the write transistor Wtr may be connected to the write bit line WBL, the other end of the write transistor Wtr may be connected to the storage node Q, and the gate terminal of the write transistor Wtr may be connected to the write word line WWL.

[0042] One end of the read transistor Rtr may be connected to the read bit line RBL, the other end of the read transistor Rtr may be connected to the read word line RWL, and the gate terminal of the read transistor Rtr may be connected to the storage node Q.

[0043] During a write operation, the bit corresponding to the i-th bit of the first operation target data can be stored in the storage node Q. When the first operation target data includes N bits (N is a natural number), the bit corresponding to the 0-th bit may be the LSB, and the bit corresponding to the N-1-th bit may be the MSB.

[0044] During a read operation, the bit cell BC i may provide a conduction current I i to the read word line RWL, the current value of which corresponds to the product value between the digital value of the i-th bit of the first operation target data and the reference current value.

[0045] During the multiplication operation, the second operation target data can be provided by reading the bit line RBL or the word line RWL. During the multiplication operation, the bit cell BC i can supply a conduction current I to the read word line RWL i , and the current value corresponds to the product of the digital value of the i-th digit in the first operation target data, the reference current value, and the second operation target data. For example, when "1" is stored in the storage node Q and the second operation target data with a value of A is provided by reading the bit line RBL or the word line RWL, the read transistor Rtr can output a conduction current to the read word line RWL whose current value corresponds to the product of 2 i , the reference current value, and A.

[0046] When a conduction voltage is applied to the write word line WWL, the first write bit line voltage (e.g., Figure 6 V in WBL1 ) or the second write bit line voltage (e.g., Figure 6 V in WBL2 ) is applied to the write bit line WBL so that "1" or "0" can be stored in the storage node Q.

[0047] In Figure 2A , the channel width-to-length ratio W / L of the read transistor Rtr can correspond to 2 i . Specifically, the channel width-to-length ratio W / L of the read transistor Rtr can correspond to the product of the reference channel width-to-length ratio and 2 i .

[0048] In Figure 2B , different from the bit cell BC Figure 2A , the bit cell BC i , the bit cell BC i can include 2 i read transistors Rtr.

[0049] In Figure 2B , one end of each of the 2 i read transistors Rtr can be commonly connected to the read bit line RBL, one end of each of the 2 i read transistors Rtr can be commonly connected to the read word line RWL, and the gate terminals of each of the 2 i read transistors Rtr can be connected in parallel between the read bit line RBL and the read word line RWL.

[0050] In Figure 2B , the channel width-to-length ratio of each of the 2 i read transistors Rtr can be the same as each other. Therefore, 2 iThe current values of the on-currents of each of the read transistors Rtr can be the same as each other. During a read operation, the sum of the current values of the on-currents supplied from 2 i read transistors Rtr to the read word line RWL can correspond to a value obtained by multiplying a reference current value by 2 i . During a multiplication operation, the sum of the current values of the on-currents supplied from 2 i read transistors Rtr to the read word line RWL can correspond to a value obtained by multiplying the reference current value, 2 i , and a second operation target data.

[0051] During Figure 2A and Figure 2B , during the multiplication operation, the bit cell BC i can supply a current to the read word line RWL, the current value of which corresponds to the product of the reference current value, 2 i , and the second operation target data.

[0052] During Figure 2A and Figure 2B , during the read operation, the bit cell BC i can supply a current to the read word line RWL, the current value of which corresponds to the product of 2 i and the reference current value, where 2 i is the position value of the bit located at the i-th position in the first operation target data.

[0053] Refer to Figure 3A and Figure 3B . Different from the bit cell BC Figure 2A of i , the bit cell BC i ' may further include a capacitor C. One end of the capacitor C can be connected to the storage node Q, and the other end of the capacitor C can be connected to the ground node. By connecting the capacitor C to the storage node Q, the amount of electric charge stored in the storage node Q can be increased.

[0054] In this specification, the bit cells included in the IMM 21 are described as Figure 2A or Figure 2B of the bit cell BC i , but the present invention is not limited thereto. For example, the bit cells included in the IMM 21 can be Figure 3A or Figure 3B of the bit cell BC i ', and can have various structures of a write transistor Wtr and a read transistor Rtr including Figure 2A and Figure 2B of the bit cell BC i .

[0055] Figure 4A and Figure 4B is a circuit diagram showing the structures of IMM 21 and IMM 21' according to an exemplary embodiment.

[0056] Referring Figure 4A , IMM 21 may include a first - order cell BC0 to an N - th order cell BC N-1 .

[0057] The gate terminals of the write transistors W0 to W N-1 included in the first - order cell BC0 to the N - th order cell BC N-1 can be commonly connected to a write word line WWL. One end of each of the write transistors W0 to W N-1 can be connected to the corresponding write bit lines WBL0 to WBL N-1 . For example, one end of the write transistor W0 can be connected to the write bit line WBL0, and one end of the write transistor W N-2 can be connected to the write bit line WBL N-2 , and one end of the write transistor W N-1 can be connected to the write bit line WBL N-1 . The other ends of each of the write transistors W0 to W N-1 can be connected to the corresponding storage nodes. For example, the other end of the write transistor W0 can be connected to the storage node Q0, and the other end of the write transistor W N-2 can be connected to the storage node Q N-2 , and the other end of the write transistor W N-1 can be connected to the storage node Q N-1 .

[0058] The read transistors R0 to R N-1 included in the first - order cell BC0 to the N - th order cell BC N-1 have one ends that can be commonly connected to a read bit line RBL. The other ends of the read transistors R0 to R N-1 can be commonly connected to a read word line RWL. The gate terminals of each of the read transistors R0 to R N-1 can be connected to the corresponding storage nodes. For example, the gate terminal of the read transistor R0 can be connected to the storage node Q0, and the gate terminal of the read transistor R N-2 can be connected to the storage node Q N-2 , and the gate terminal of the read transistor R N-1 can be connected to the storage node Q N-1 .

[0059] The read transistors R0 to R N-1The channel width-to-length ratio W / L of each of them can correspond to the product of a reference channel width-to-length ratio and a power of 2. For example, the channel width-to-length ratio of the read transistor R0 can be the product of the reference channel width-to-length ratio and 2 0 = 1, and the channel width-to-length ratio of the read transistor R N-2 can be the product of the reference channel width-to-length ratio and 2 N-2 and the channel width-to-length ratio of the read transistor R N-1 can be the product of the reference channel width-to-length ratio and 2 N-1 . The reference channel width-to-length ratio can refer to the channel width-to-length ratio of the read transistor R0.

[0060] During a write operation, the first arithmetic target data can be stored in the storage nodes Q0 to Q N-1 of the first bit cells BC0 to the Nth bit cells BC N-1 based on the voltage provided by the write bit lines WBL0 to WBL N-1 . For example, when the first write bit line voltage V WBL1 is applied to the write bit line WBL0, a "1" can be stored in the storage node Q0, and when the second write bit line voltage V WBL2 is applied to the first write bit line WBL0, a "0" can be stored in the storage node Q0. For example, the first write bit line voltage V WBL1 can be the positive power supply voltage VDD, and the second write bit line voltage V WBL2 can be the ground voltage V GND .

[0061] During a read operation, each of the read transistors R0 to R N-1 can output a conduction current to the read word line RWL whose amplitude is proportional to the corresponding channel width-to-length ratio. For example, each of the read transistors R0 to R N-1 can provide a conduction current to the read word line RWL whose current value corresponds to the product of the digital value of the corresponding number of bits and the reference current value. Therefore, the total current of the conduction current provided to the read word line RWL can have a current value corresponding to the product of the first arithmetic target data and the reference current value.

[0062] During a multiplication operation, each of the read transistors R0 to R N-1 can output a conduction current to the read word line RWL whose amplitude is proportional to the corresponding channel width-to-length ratio and the second arithmetic target data. For example, each of the read transistors R0 to R N-1Each of them may supply a conduction current to the read word line RWL, where the current value corresponds to the multiplication value of the digital value of the corresponding number of bits, the reference current value, and the second operation target data. Therefore, the total current of the conduction current supplied to the read word line RWL may have a current value corresponding to the product of the first operation target data, the reference current value, and the second operation target data.

[0063] The ADC 24 may obtain the first operation target data corresponding to the result of the read operation or the binary number data corresponding to the result of the multiplication operation based on the total current.

[0064] The memory device 20 according to the embodiment may operate as a CIM by performing a multiplication operation using bit cells in which the ratio between conduction currents is a power of 2.

[0065] Reference Figure 4B , the IMM 21' may include the first bit cell BC0 to the Nth bit cell BC N-1 .

[0066] The first bit cell BC0 to the Nth bit cell BC N-1 Each of them may include read transistors Rtr in a quantity corresponding to a power of 2. Additionally, each of the first bit cell BC0 to the Nth bit cell BC N-1 may include a different number of read transistors Rtr. The number of read transistors Rtr may be equal to the digital value of the corresponding number of bits of the first bit cell BC0 to the Nth bit cell BC N-1 . For example, the first bit cell BC0 may include 2 0 = 1 read transistor, which is the digital value of the 0th bit, and the (N - 1)th bit cell BC N-2 may include 2 N-2 read transistors, which is the digital value of the (N - 2)th bit, and the Nth bit cell BC N-1 may include 2 N-1 read transistors, which is the digital value of the (N - 1)th bit.

[0067] In each of the first bit cell BC0 to the Nth bit cell BC N-1 , one terminal of the read transistor Rtr may be commonly connected to the read bit line RBL, and the other terminal of the read transistor Rtr may be commonly connected to the read word line RWL, and the gate terminals of the read transistors Rtr may be commonly connected to the storage node.

[0068] The first bit cell BC0 to the Nth bit cell BC N-1Each of the groups of read transistors Rtr included therein can be referred to as a read transistor group. For example, one read transistor included in the first bit cell BC0 can be referred to as the first read transistor group RG0, and the 2 N-2 read transistors included in the (N - 1)-th bit cell BC N-2 can be referred to as the (N - 1)-th read transistor group RG N-2 , and the 2 N-1 read transistors included in the N-th bit cell BC N-1 can be referred to as the N-th read transistor group RG N-1 .

[0069] During a read operation, each of the first read transistor group RG0 to the N-th read transistor group RG N-1 can output a conduction current to the read word line RWL that is proportional to the number of read transistors included in each of the first read transistor group RG0 to the N-th read transistor group RG N-1 . For example, each of the first read transistor group RG0 to the N-th read transistor group RG N-1 can provide a conduction current to the read word line RWL that corresponds to the product of the digital value of the corresponding number of bits and the reference current value. Therefore, the total current of the conduction current provided to the read word line RWL can have a current value corresponding to the product value between the first operation target data and the reference current value.

[0070] During a multiplication operation, each of the first read transistor group RG0 to the N-th read transistor group RG N-1 can output a conduction current to the read word line RWL whose amplitude is proportional to the number of read transistors included in each of the first read transistor group RG0 to the N-th read transistor group RG N-1 and the second operation target data. For example, each of the first read transistor group RG0 to the N-th read transistor group RG N-1 can provide a conduction current to the read word line RWL that corresponds to the product of the digital value of the corresponding number of bits, the reference current value, and the second operation target data. Therefore, the total current of the conduction current provided to the read word line RWL can have a current value corresponding to the product of the first operation target data, the reference current value, and the second operation target data.

[0071] Hereinafter, the IMM 21 of Figure 4A will be mainly described, but the description of the IMM 21 of Figure 4A can also be applied to the IMM 21' of Figure 4B . For example, in the read transistors R0 to R of Figure 4A N-1 ​Among them, the on-current supplied from the read transistor R0 to the read word line RWL can be the same as the on-current supplied from the Figure 4B read transistor groups RG0 to RG in N-1 the read transistor group RG in i to the read word line RWL.

[0072] Figure 5 FIG. shows a circuit of the ADC 24 according to an embodiment.

[0073] Referring to Figure 5 , the ADC 24 can convert an analog input signal Vin into digital output signals b1 to bm. The analog input signal Vin can be the voltage charged into the capacitor C. The capacitor C can be charged by the current supplied from the read word line RWL of the IMM 21, and the voltage charged during the reference time can be applied to the comparator circuit 520 as the analog input signal Vin.

[0074] The digital output signals b1 to bm can be composed of multiple bits. During the read operation, the binary number indicated by the digital output signals b1 to bm can be the first operation target data stored in the IMM 21. During the multiplication operation, the binary number indicated by the digital output signals b1 to bm can be the result of multiplying the first operation target data stored in the IMM 21 by the second operation target data corresponding to the voltage applied to the read bit line RBL.

[0075] The ADC 24 can include a resistor array 510, a comparator circuit 520, and an encoder 530. The comparator circuit 520 can include multiple comparators COMP.

[0076] The resistor array 510 can include multiple resistors R1 to R6. One end of the resistor array 510 can receive a reference voltage Vref, and the other end of the resistor array 510 can be connected to a ground node. The reference voltage Vref can be distributed to each node formed by the multiple resistors R1 to R6.

[0077] The comparator circuit 520 can output multiple output signals Vout1 to VoutL by comparing the voltage signals distributed to each node formed by the multiple resistors R1 to R6 with the analog input signal Vin and amplifying the comparison result.

[0078] The encoder 530 can receive the multiple output signals Vout1 to VoutL and generate a bit sequence corresponding to the multiple output signals Vout1 to VoutL as the digital output signals b1 to bm.

[0079] The ADC 24 can be different from Figure 5implemented in various ways and can have various structures for generating binary number data corresponding to the current value of the current based on the current supplied from the read word line RWL.

[0080] Figure 6 and Figure 7 is a timing diagram illustrating a write operation according to an exemplary embodiment. Reference may be made to Figure 1 and Figure 4A for illustration. Figure 6 and Figure 7 .

[0081] Referring to Figure 6 , at the first time point t1, the BLSA 26 can apply a second write bit line voltage V N-2 to the write bit lines WBL0 to WBL WBL2 , and apply a first write bit line voltage V N-1 to the write bit line WBL WBL1 . Accordingly, one end of each of the first write transistors W0 to the Nth write transistor W N-1 can be precharged with the first write bit line voltage V WBL1 or the second write bit line voltage V WBL2 . The level of the first write bit line voltage V WBL1 can be higher than the level of the second write bit line voltage V WBL2 .

[0082] Referring to Figure 6 , at the second time point t2, the word line driver 25 can apply a conduction voltage V ON to the write word line WWL. The first write transistors W0 to the Nth write transistor W N-1 can be turned on by the conduction voltage V ON . In an embodiment, the level of the conduction voltage V ON can be equal to or greater than the level of the positive power supply voltage VDD. The first write bit line voltage V N-1 or the second write bit line voltage V WBL1 precharged to one end of each of the first write transistors W0 to the Nth write transistor W WBL2 can be transferred to the other end of each of the first write transistors W0 to the Nth write transistor W N-1 . That is, the first operation target data can be transferred to the first storage nodes Q0 to the Nth storage nodes Q N-1 .

[0083] Referring to Figure 6 , at the third time point t3, the word line driver 25 can apply a cut-off voltage V OFF to the write word line WWL. The first write transistors W0 to the Nth write transistor W N-1 can be turned off by the cut-off voltage VOFF Cut-off. For example, the cut-off voltage V OFF may be the ground voltage V GND . Thus, by maintaining the charge states of the first storage node Q0 to the Nth storage node Q N-1 , the first operation target data can be stored in the IMM 21.

[0084] Specifically, “1” can be stored in the Nth storage node Q WBL1 pre-charged by the first write bit line voltage V N-1 , and “0” can be stored in the first storage node Q0 to the (N−1)th storage node Q WBL2 pre-charged by the second write bit line voltage V N-2 . That is, the binary number data 10…02 can be stored in the IMM 21. However, the present invention is not limited thereto, and “0” can be stored in the Nth storage node Q WBL1 pre-charged by the first write bit line voltage V N-1 , and “1” can also be stored in the first storage node Q0 to the (N−1)th storage node Q WBL2 pre-charged by the second write bit line voltage V N-2 .

[0085] In Figure 6 , although the level of the conduction voltage V ON is shown to be higher than the level of the cut-off voltage V OFF , the present invention is not limited thereto. For example, different from the write transistors W0 to W Figure 4A illustrated as N-type transistors in N-1 , when the write transistors are P-type transistors, the level of the conduction voltage V ON can be lower than the level of the cut-off voltage V OFF .

[0086] Referring to Figure 6 , during the period from the first time point t1 to the fourth time point t4, the BLSA 26 can apply the ground voltage V GND to the read bit line RBL. The word line driver 25 can apply the ground voltage V GND to the read word line RWL.

[0087] In some embodiments, during the period from the third time point t3 to the fourth time point t4, the BLSA 26 can initialize the write bit lines WBL0 to WBL N-1 . For example, the BLSA 26 can apply the ground voltage V N-1 or the second write bit line voltage V GND to all of the write bit lines WBL0 to WBL WBL2 .

[0088] Reference Figure 7 , different from Figure 6 , during the period from the first time point t1 to the fourth time point t4, the BLSA 26 can apply a first precharge voltage V pre1 to the read bit line RBL. The word line driver 25 can apply a second precharge voltage V pre2 to the read word line RWL. The first precharge voltage V pre1 and the second precharge voltage V pre2 can be the same or different. Each of the first precharge voltage V pre1 and the second precharge voltage V pre2 can have a level higher than the ground voltage V GND .

[0089] By precharging both ends of the read transistors R0 to R N-1 while the first operation target data is stored in the storage nodes Q0 to Q N-1 , current leakage from the storage nodes Q0 to Q N-1 to both ends of the read transistors R0 to R N-1 can be prevented.

[0090] However, the present invention is not limited thereto, and the word line driver 25 and the BLSA 26 can prevent current leakage from the storage nodes Q0 to Q N-1 to both ends of the read transistors R0 to R N-1 by precharging at least one of the read word line RWL and the read bit line RBL during a part of the period from the first time point t1 to the fourth time point t4.

[0091] Figure 8 is a diagram illustrating a write operation of the first operation target data 11012 according to an embodiment.

[0092] Reference Figure 8 , the IMM 80 can have the structure and functions of the IMM 21 described in Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B and Figures 5 to 7 . The IMM 80 can include a first bit cell BC0 to a fourth bit cell BC3.

[0093] The IMM 80 can store the binary number 11012 as the first operation target data by performing a write operation.

[0094] The fourth bit cell BC3 can store a value related to having 2 3The bit corresponding to the number of bits of the numerical value, i.e., the MSB. The third cell BC2 can store the bit corresponding to the number of bits of a numerical value having 2 2 The bit corresponding to the number of bits of the numerical value. The second cell BC1 can store the bit corresponding to the number of bits of a numerical value having 2 1 The bit corresponding to the number of bits of the numerical value. And the first cell BC0 can store the bit corresponding to the number of bits of a numerical value having 2 0 The bit corresponding to the number of bits of the numerical value, i.e., the LSB.

[0095] Specifically, as described with reference to Figure 6 and Figure 7 At the first time point t1, the BLSA 26 can apply a first write bit line voltage V to the first write bit line WBL0, the third write bit line WBL2, and the fourth write bit line WBL3, and apply a second write bit line voltage V to the second write bit line WBL1. WBL1 And apply a second write bit line voltage V to the second write bit line WBL1. WBL2 .

[0096] The word line driver 25 can apply a conduction voltage V to the write word line WWL at the second time point t2, and apply a cut-off voltage V to the write word line WWL at the third time point t3. ON And apply a cut-off voltage V to the write word line WWL at the third time point t3. OFF Therefore, the binary number 11012 as the first operation target data can be stored in the IMM 80.

[0097] Figure 9 is a circuit diagram illustrating a refresh operation according to an embodiment, and Figure 10 is a Figure 9 timing diagram of the refresh operation according to the embodiment.

[0098] Referring to Figure 9 , as described above with reference to Figure 8 , the IMM 80 can store the first operation target data 11012.

[0099] The write bit lines WBL0 to WBL N-1 can be connected to the BLSA 26. Specifically, the write bit line WBL0 can be connected to the sense amplifier SA0, the write bit line WBL1 can be connected to the sense amplifier SA1, the write bit line WBL2 can be connected to the sense amplifier SA2, and the write bit line WBL3 can be connected to the sense amplifier SA3. The BLSA 26 can pre-charge or sense the voltage level of each of the write bit lines WBL0 to WBL N-1 Pre-charge or sense the voltage level of each of the write bit lines WBL0 to WBL N-1 .

[0100] Referring to Figure 10 , the refresh operation can be performed during the period from the first time point t1 to the sixth time point t6.

[0101] At a first time point t1, the BLSA 26 can apply a precharge voltage V to the write bit lines WBL0 to WBL3. pre .

[0102] At a second time point t2, the word line driver 25 can apply a conduction voltage V to the write word line WWL. ON . As a result, the write transistors W0 to W3 can be turned on, and the storage nodes Q0 to Q3 can share charge with the write bit lines WBL0 to WBL3. Since the write bit line WBL1 is connected to the storage node Q1 storing "0", the voltage level can be reduced more significantly compared to the write bit lines WBL0, WBL2, and WBL3 connected to the storage nodes Q0, Q2, and Q3 storing "1".

[0103] At a third time point t3, the word line driver 25 can turn off the write transistors W0 to W3 by applying a cutoff voltage V to the write word line WWL. OFF

[0104] At the third time point t3, the BLSA 26 can detect the voltage level of each of the write bit lines WBL0 to WBL3 and amplify the voltage level of each of the write bit lines WBL0 to WBL3 to a first write bit line voltage V WBL1 or a second write bit line voltage V. WBL2 . Specifically, the voltage level of the write bit line WBL0 having a relatively low voltage level can be amplified to the second write bit line voltage V. WBL2 And the voltage level of each of the write bit lines WBL0, WBL2, and WBL3 having a relatively high voltage level can be amplified to the first write bit line voltage V. WBL1 .

[0105] At a fourth time point t4, the word line driver 25 can apply a conduction voltage V to the write word line WWL. ON The write transistors W0 to W3 can be turned on by the conduction voltage V. ON . As a result, the first write bit line voltage V WBL1 or the second write bit line voltage V WBL2 can be provided to the storage nodes Q0 to Q3. Specifically, the first write bit line voltage V WBL1 can be provided to the storage nodes Q0, Q2, and Q3, and the second write bit line voltage V WBL2 can be provided to the storage node Q1.

[0106] At a fifth time point t5, the word line driver 25 can apply a cutoff voltage V to the write word line WWL. OFF The write transistors W0 to W3 can be turned off by the cutoff voltage V. OFFTherefore, by maintaining the charge states of the storage nodes Q0 to Q3, the first operation target data may be stored in the IMM 80.

[0107] By rewriting data to the storage nodes Q0 to Q3 through a refresh operation, data retention performance can be improved.

[0108] Figure 11 is a circuit diagram illustrating a multiplication operation according to an embodiment. Figure 12 This is to explain the Figure 11 Timing diagram for the multiplication operation.

[0109] refer to Figure 11 During the multiplication operation, the BLSA 26 may apply a voltage having an amplitude proportional to the second operation target data “A” to the read bit line RBL. For example, the BLSA 26 may apply A×V READ The read transistors R0 to R1 operate in the linear region. N-1 The drain voltage range can include A×V READ Therefore, the reading transistors R0 to R N-1 Can output with A×V READ Proportional to the current. For example, A×V READ can be less than by subtracting the read transistor R0 to R from the positive supply voltage VDD N-1 The threshold voltage V th In some embodiments, V READ The level of V may be pre-recorded in an internal register (not shown) at startup or during manufacture of the memory device 20. In some embodiments, V READ The level of V READ The level of can be variably adjusted according to the value of "A".

[0110] From the read transistor R0 to R N-1 The read transistor R i Output conduction current I i It can be expressed as in Equation 1 (i is an integer greater than or equal to 0 and less than or equal to N-1).

[0111] [Equation 1]

[0112] Here, D i It can be stored in storage node Q i The data in W can be read by transistor R i The channel width of the read transistor R iChannel length.

[0113] In this document, in all equations given in this specification, the current from the sense transistor is described in the following form: the product of the electron mobility (μ) and the gate oxide film capacitance (Cox) is regarded as 1 and omitted for simplicity. This is to illustrate the relative current change under certain conditions, and in actual design or simulation, the actual current model considering mobility and capacitance should be used. For example, in the equation, "W / L (VDD-Vth) V READ " can refer to "W / L μCox (VDD-Vth) V READ ".

[0114] In Figure 4B the embodiment of the IMM 21', I i can mean the current supplied from the sense transistor bank RG i to the sense word line RWL.

[0115] As the total current I N-1 which is the sum of the on-currents output from the sense transistors R0 to R total can be expressed as in Equation 2.

[0116] [Equation 2]

[0117] For example, the current value of the total current I total can be proportional to the product of the binary number [D N-1 D N-2 … D0]2 stored in the IMM 80 as the first operation target data and "A" as the second operation target data.

[0118] In Figure 4B the embodiment of the IMM 21', I total can mean the sum of the currents supplied from the first sense transistor bank RG0 to the Nth sense transistor bank RG N-1 to the sense word line RWL.

[0119] Referring again to Figure 5 , by generating the digital output signals b1 to bm for the total current I total supplied through the sense word line RWL, the ADC 24 can obtain the result value of the multiplication operation of the first operation target data and the second operation target data.

[0120] Referring to Figure 12 , at the first time point t1, the word line driver 25 can apply the cut-off voltage V OFF . Thus, the write transistors W0 to W N-1can be cut off.

[0121] At the second time point t2, the word line driver 25 can apply a ground voltage V to the read word line RWL GND .

[0122] At the third time point t3, the BLSA 26 can apply a voltage proportional to the amplitude of the second arithmetic target data "A" to the read bit line RBL. For example, the BLSA 26 can apply a voltage with an amplitude of A×V READ to the read bit line RBL.

[0123] Although it is illustrated that a cut-off voltage V is applied to the write bit lines WBL0 to WBL during the period from the first time point t1 to the fourth time point t4 N-1 , the present invention is not limited thereto. For example, according to the data stored in the storage node, the voltage level applied to the write bit line can vary. Specifically, when "0" is stored in the storage node, a cut-off voltage V can be applied to the corresponding write bit line OFF , and when "1" is stored in the storage node, a conduction voltage V can be applied to the corresponding write bit line OFF . ON .

[0124] Figure 13 is a circuit diagram illustrating a multiplication operation between the binary number 11012 and the decimal number 3 according to an embodiment.

[0125] As described above with reference to Figure 8 and Figure 9 , the binary number 11012 can be stored in the Figure 13 IMM 80.

[0126] When at the Figure 12 third time point t3, the BLSA 26 can apply a voltage with a magnitude of 3×V to the read bit line RBL READ .

[0127] Since "0" is stored in the storage node Q1, the read transistor R1 can be cut off and no conduction current I1 of the read transistor R1 is generated.

[0128] Therefore, as described in Equation 3, the total current I total can be the sum of the conduction currents I0, I2, and I3 of the read transistors R0, R2, and R3.

[0129] [Equation 3]

[0130] Here, I ref1 can have the same as in Equation 1 and Equation 2 The corresponding values. As referred to above Figures 11 to 13 described, IMM 21 and IMM 80 can perform a multiplication operation based on the magnitude of the voltage applied to the read bit line RBL.

[0131] Figure 14 is a circuit diagram illustrating a multiplication operation according to an embodiment. Figure 15 is a diagram illustrating according to an embodiment Figure 14 timing diagram of the multiplication operation of.

[0132] Refer to Figure 14 , during the multiplication operation, BLSA 26 can apply a read bit line voltage V to the read bit line RBL RBL . The word line driver 25 can apply a negative pulse voltage to the read word line RWL, and its voltage level drops from the positive power supply voltage VDD level to the ground voltage V GND level during the time period "T" which is the second operation target data.

[0133] For the time period "T" from the read transistors R0 to R N-1 among the read transistors R i The sum of the output on-currents I i can be expressed as in Equation 4 (where i is an integer greater than or equal to 0 and less than or equal to N - 1).

[0134] [Equation 4]

[0135] During the time period "T", the sum of the on-currents I output from the read transistors R0 to R N-1 can be expressed as in Equation 5. total The sum of the output on-currents I

[0136] [Equation 5]

[0137] For example, during the time period "T", the sum magnitude of the current I total can be proportional to the product of the binary number [D N-1 D N-2 ,... D0]2 stored in IMM 21 as the first operation target data and the second operation target data "T".

[0138] Refer to again Figure 5 , by generating digital output signals b1 to bm for the sum of the currents I total provided through the read word line RWL for the time period T, the ADC 24 can obtain the result value of the multiplication operation of the first operation target data and the second operation target data.

[0139] refer to Figure 15 At the first time point t1, the word line driver 25 may apply a cutoff voltage V to the write word line WWL. OFF Therefore, write transistors W0 to W N-1 Can be closed.

[0140] At the second time point t2, the BLSA 26 may apply a read bit line voltage V RBL . Read the bit line voltage V RBL can be used to enable the read transistor R0 to R N-1 The voltage range that operates in the linear region or saturation region.

[0141] Between the third time point t3 and the fourth time point t4, the word line driver 25 may apply the ground voltage V to the read word line RWL for a period of time proportional to the size or length of the second operation target data “T”. GND For example, the word line driver 25 may apply a negative pulse voltage having a length of a time period “T”. Herein, the time period “T” may be referred to as a pulse time period.

[0142] Although the writing of the bit lines WBL0 to WBL1 from the first time point t1 to the fourth time point t4 is illustrated, N-1 Apply cut-off voltage V OFF , but the present invention is not limited thereto. For example, depending on the data stored in the storage node, the voltage level applied to the write bit line may vary. In detail, when "0" is stored in the storage node, a cut-off voltage may be applied to the corresponding write bit line, and when "1" is stored in the storage node, a turn-on voltage may be applied to the corresponding write bit line.

[0143] Figure 16 is a circuit diagram illustrating a multiplication operation between a binary number 11012 and a decimal number 3 according to an embodiment.

[0144] As referenced above Figure 8 and Figure 9 As described, the binary number 11012 can be stored in Figure 16 of IMM 80.

[0145] When Figure 15 In the time period between the third time point t3 and the fourth time point t4, the word line driver 25 may apply the ground voltage V to the read word line RWL in the time period corresponding to “3”. GND For example, the word line driver 25 may apply a negative pulse voltage with a length corresponding to "3".

[0146] Since "0" is stored in the storage node Q1, the read transistor R1 can be turned off and the on-current I1 of the read transistor R1 is not generated.

[0147] Therefore, the total current I during the time period T total The sum can be expressed as in Equation 6.

[0148] [Equation 6]

[0149]

[0150] Here, I ref2 can have values corresponding to those in Equations 4 and 5.

[0151] As described above with reference to Figures 14 to 16 the IMM 21 and the IMM 80 can perform a multiplication operation based on the length of the pulse applied to the read word line RWL.

[0152] Figure 17 and Figure 18 are timing diagrams illustrating the read operation according to an exemplary embodiment. Reference can be made to Figure 12 to illustrate Figure 17 , and reference can be made to Figure 15 to illustrate Figure 18 .

[0153] Referring to Figure 17 , different from Figure 12 , at the third time point t3, the BLSA 26 can apply a voltage with an amplitude of 1×V READ to the read bit line RBL.

[0154] Therefore, the sum I of the on-currents output from the read transistors R0 to R N-1 can be expressed as in Equation 7. total

[0155] [Equation 7]

[0156] For example, the total current I total can have a magnitude corresponding to the multiplication between the first operation target data stored in the IMM 21 and I ref1 .

[0157] Referring again to Figure 5 , the ADC 24 can generate digital output signals b1 to bm for the current I total provided through the read word line RWL. The digital output signals b1 to bm can represent the first operation target data ​​The same value.

[0158] Reference Figure 18 , different from that in Figure 15 , at the third time point t3, the word line driver 25 can apply a negative pulse voltage having a ground voltage V to the read word line RWL during a period corresponding to 1 GND level. For example, the word line driver 25 can apply a negative pulse voltage having a length corresponding to "1".

[0159] Therefore, the sum of I total provided through the read word line RWL during the period corresponding to 1 can be expressed as in Equation 8.

[0160] [Equation 8]

[0161] For example, the sum of the total current I total can have an amplitude corresponding to the multiplication between the first arithmetic target data stored in the IMM 21 and I ref2 .

[0162] Referring again to Figure 5 , the ADC 24 can generate digital output signals b1 to bm for the sum of the total current I total provided through the read word line RWL. The digital output signals b1 to bm can represent the same value as the first arithmetic target data .

[0163] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory device, the memory device comprising: An in-memory operation circuit, the in-memory operation circuit being connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including a plurality of bit cells; Wherein each of the plurality of bit cells includes: A first transistor, one end of the first transistor being connected to a corresponding write bit line among the plurality of write bit lines, the other end of the first transistor being connected to a storage node, and the gate terminal of the first transistor being connected to the write word line; and At least one second transistor, one end of the at least one second transistor being connected to the read bit line, the other end of the at least one second transistor being connected to the read word line, and the gate terminal of the at least one second transistor being connected to the storage node, Wherein the current value of the on-current of the at least one second transistor included in each of the plurality of bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2, and Wherein the power of 2 is different for each of the plurality of bit cells.

2. The memory device according to claim 1, wherein, The channel width-to-length ratio of the at least one second transistor included in each of the plurality of bit cells corresponds to a value obtained by multiplying a reference channel width-to-length ratio by a corresponding power of 2.

3. The memory device according to claim 1, wherein, Each of the plurality of bit cells includes a number of the second transistors corresponding to the respective power of 2, and the number of the second transistors included in each of the plurality of bit cells is different from each other.

4. The memory device according to claim 1, the memory device further comprising: A bit line sense amplifier configured to provide a voltage to the plurality of write bit lines and the read bit line; And A word line driver configured to provide a voltage to the write word line and the read word line.

5. The memory device according to claim 4, wherein, The memory device is configured such that, when a write operation is performed on first operation target data: The bit line sense amplifier applies a first write bit line voltage or a second write bit line voltage different from the first write bit line voltage to the plurality of write bit lines during a first time period according to the first operation target data, and The word line driver applies a conduction voltage to the write word line during a second time period and an off voltage to the write word line during a third time period.

6. The memory device according to claim 5, wherein, The memory device is further configured such that, during the first time period to the third time period: The bit line sense amplifier applies a ground voltage to the read bit line, and The word line driver applies the ground voltage to the read word line.

7. The memory device according to claim 5, wherein, The memory device is further configured such that: The bit line sense amplifier applies a first precharge voltage to the read bit line during at least a part of the first time period to the third time period, The word line driver applies a second precharge voltage to the read word line during at least a part of the first time period to the third time period, and Wherein both the first precharge voltage and the second precharge voltage are different from the ground voltage.

8. The memory device according to claim 5, wherein The memory device is further configured such that: In a fourth time period, the bit line sense amplifier pre-charges the plurality of write bit lines to a pre-charge voltage greater than the ground voltage. In a fifth time period, the word line driver applies a conduction voltage to the write word line. In a sixth time period, the word line driver applies the cut-off voltage to the write word line, and the bit line sense amplifier applies the first write bit line voltage or the second write bit line voltage to the plurality of write bit lines by amplifying the voltage levels of the plurality of write bit lines. In a seventh time period, the word line driver applies the conduction voltage to the write word line, and In an eighth time period, the word line driver applies the cut-off voltage to the write word line.

9. The memory device according to claim 4, wherein, The memory device is configured such that when performing a multiplication operation between first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells, it causes: In a first time period, the word line driver applies a cut-off voltage to the write word line. In a second time period, the word line driver applies a ground voltage to the read word line, and In a third time period, the bit line sense amplifier applies a voltage whose amplitude is proportional to the second operation target data to the read bit line.

10. The memory device according to claim 4, wherein, The memory device is configured such that when performing a read operation on first operation target data stored in the storage nodes of the plurality of bit cells, it causes: In a first time period, the word line driver applies a cut-off voltage to the write word line. In a second time period, the word line driver applies a ground voltage to the read word line, and In a third time period, the bit line sense amplifier applies a predetermined read voltage to the read bit line.

11. The memory device according to claim 4, wherein, The memory device is configured such that when performing a multiplication operation between first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells, it causes: In a first time period, the word line driver applies a cut-off voltage to the write word line. In a second time period, the bit line sense amplifier applies a read bit line voltage to the read bit line, and In a third time period, the word line driver applies a pulse voltage to the read word line, and the pulse voltage maintains the level of the ground voltage within a pulse time period having a length proportional to the second operation target data.

12. The memory device according to claim 11, wherein, In a time period other than the pulse time period within the third time period, the pulse voltage includes a positive power supply voltage level.

13. The memory device according to claim 4, wherein, The memory device is configured such that when performing a read operation on first operation target data stored in the storage nodes of the plurality of bit cells, it causes: In a first time period, the word line driver applies a cut-off voltage to the write word line. In a second time period, the bit line sense amplifier applies a read bit line voltage to the read bit line, and In a third time period, the word line driver applies a pulse voltage to the read word line, and the pulse voltage maintains the level of the ground voltage within a time period having a length corresponding to the value of "1".

14. The memory device according to claim 1, the memory device further comprising: An analog-to-digital converter configured to receive currents of a plurality of second transistors included in the plurality of bit cells from the read word line and generate a digital output signal based on current values of the currents.

15. A method of operating a memory device, the memory device including a plurality of bit cells, each of the plurality of bit cells including a first transistor and at least one second transistor, one end of the first transistor being connected to a corresponding write bit line among a plurality of write bit lines, the other end of the first transistor being connected to a storage node, and a gate terminal of the first transistor being connected to a write word line; One end of the at least one second transistor is connected to a read bit line, the other end of the at least one second transistor is connected to a read word line, and a gate terminal of the at least one second transistor is connected to the storage node, and the at least one second transistor provides different on-currents for the plurality of bit cells. The method includes: Performing a multiplication operation of first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells. Wherein performing the multiplication operation includes: Applying a cut-off voltage to the write word line in a first time period; Applying a ground voltage to the read word line in a second time period; and Applying a voltage having an amplitude associated with the second operation target data to the read bit line in a third time period.

16. The method according to claim 15, the method further includes: Performing a write operation on the first operation target data. Wherein performing the write operation includes: Applying a first write bit line voltage or a second write bit line voltage to the plurality of write bit lines according to the first operation target data in a fourth time period; Applying a conduction voltage to the write word line in a fifth time period; and Applying the cut-off voltage to the write word line in a sixth time period.

17. The method according to claim 16, wherein, Performing the write operation further includes: Applying a ground voltage to the read bit line and the read word line during the fourth time period to the sixth time period.

18. The method according to claim 16, wherein, Performing the write operation further includes: Applying a first pre-charge voltage to the read bit line during at least a part of the fourth time period to the sixth time period; and Applying a second pre-charge voltage to the read word line during at least a part of the fourth time period to the sixth time period, and wherein both the first pre-charge voltage and the second pre-charge voltage are different from the ground voltage.

19. The method according to claim 15, the method further includes: Generating result data corresponding to a result of the multiplication operation of the first operation target data and the second operation target data based on an amplitude of the on-currents of the plurality of second transistors included in the plurality of bit cells provided from the read word line.

20. A method of operating a memory device, the memory device including a plurality of bit cells, each of the plurality of bit cells including a first transistor and at least one second transistor, one end of the first transistor being connected to a corresponding write bit line among a plurality of write bit lines, the other end of the first transistor being connected to a storage node, and a gate terminal of the first transistor being connected to a write word line; One end of the at least one second transistor is connected to a read bit line, the other end of the at least one second transistor is connected to a read word line, and a gate terminal of the at least one second transistor is connected to the storage node, and the at least one second transistor provides different on-currents for the plurality of bit cells. The method includes: Performing a multiplication operation of first operation target data and second operation target data stored in the storage nodes of the plurality of bit cells. Wherein performing the multiplication operation includes: Applying a cut-off voltage to the write word line in a first time period; Applying a read bit line voltage to the read bit line in a second time period; and A pulse voltage is applied to the read word line in the third time period, and the pulse voltage maintains a ground voltage level during a pulse time period having a length proportional to the second operation target data.

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