Test optimization method and system for high-capacity 3D flash memory

Abstract

The invention relates to a test optimization method and system for a high-capacity 3D flash memory, and the method comprises the steps: carrying out the reliability testing of a random storage unit in a target flash memory chip for multiple times through grouping based on a reference temperature and a target temperature; the method comprises the following steps: respectively collecting test data of reliability test of a target chip at a reference temperature and a target temperature, and constructing a data sample set according to the test data; based on the data sample set and a few-sample training method, training a discriminator model used for judging whether the flash memory chip has a fault or not; and obtaining test data of the target flash memory chip under the reliability test at the target temperature, and inputting the test data into the discriminator model to obtain a test result of the target flash memory chip. According to the invention, the characteristic storage unit and the discriminator are selected to predict the test result at the target temperature to optimize the test process of the high-capacity 3D flash memory chip, a small amount of test data is analyzed to obtain the test result, the test time is greatly shortened, and the test efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of flash memory reliability testing, and particularly relates to a test optimization method and system for large-capacity 3D flash memory, and particularly to a multi-temperature test method and system for flash memory reliability for long-term storage. Background Art

[0002] With the rapid development of technologies such as big data, cloud computing, and the Internet of Things, the amount of information to be stored and analyzed has increased explosively, and the demand for storage capacity has been continuously increasing. In order to obtain a larger storage capacity and a higher storage density, flash memory manufacturers and users have shifted their focus from planar architectures to 3D architectures. During long-term use and under different environmental conditions, problems such as data loss or damage may occur in flash memory, and reliability testing is required to detect and solve potential problems in advance. Therefore, conducting reliability testing on 3D NAND flash memory is crucial for exploring its reliability characteristics, improving product quality, ensuring data security, and promoting its wide application in various fields.

[0003] Traditional testing methods need to design experiments separately for different temperatures to obtain a large amount of data in order to obtain error characteristics at different temperatures. However, this process consumes a huge amount of the lifespan of flash memory particles, resulting in extremely high testing costs. Summary of the Invention

[0004] In order to reduce the testing cost of flash memory and improve the testing accuracy, in the first aspect of the present invention, a test optimization method for large-capacity 3D flash memory is provided, including: based on a reference temperature and a target temperature, performing multiple reliability tests on random storage units in a target flash memory chip by grouping; respectively collecting test data of the target chip during reliability testing at the reference temperature and the target temperature, and constructing a data sample set according to the test data; the test data includes storage location, number of read / write operations, read / write time, and abnormal information; based on the data sample set and a few-shot training method, training a discriminator model for determining whether a flash memory chip fails; obtaining test data of the target flash memory chip during reliability testing at the target temperature, and inputting the test data into the discriminator model to obtain a test result of the target flash memory chip.

[0005] In some embodiments of the present invention, the performing multiple reliability tests on random storage units in a target flash memory chip by grouping based on a reference temperature and a target temperature includes: randomly sampling from multiple target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; based on the reference temperature and the target temperature, respectively performing programming, erasing, and read cycle tests on the two groups of target chips.

[0006] Further, the programming, erasing, and reading loop test on the two groups of target chips includes: in each loop test, sequentially performing erase, write, programming, and read operations on the target chips, and marking the failed operations; determining whether the target chips under test are faulty, and determining whether to end the loop test according to the determination result.

[0007] In some embodiments of the present invention, training a discriminator model for determining whether a flash memory chip is faulty based on the data sample set and the few-shot training method includes: using the test data of the target chips subjected to N reliability tests at both the reference temperature and the target temperature as samples, where n≥1000; using the test data of the n reference temperature and target temperature as samples, and using the results of the target temperature failing M reliability tests as labels, m>n; based on the samples and the labels, training a discriminator model for determining whether a flash memory chip is faulty through the few-shot training method.

[0008] Further, 。

[0009] In the above embodiments, the discriminator model is a neural network.

[0010] In a second aspect of the present invention, there is provided a test optimization system for a large-capacity 3D flash memory, including: a test module for performing multiple reliability tests on random storage units in target flash memory chips in groups based on a reference temperature and a target temperature; a construction module for respectively collecting test data of the target chips subjected to reliability tests at the reference temperature and the target temperature, and constructing a data sample set according to the test data; the test data includes storage location, read / write times, read / write time, and abnormal information; a training module for training a discriminator model for determining whether a flash memory chip is faulty based on the data sample set and the few-shot training method; a judgment module for obtaining test data of the target flash memory chip under the reliability test at the target temperature, and inputting the test data into the discriminator model to obtain a test result of the target flash memory chip.

[0011] Further, the test module includes: a sampling unit for randomly sampling from multiple target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; a test unit for performing programming, erasing, and reading loop tests on the two groups of target chips respectively based on the reference temperature and the target temperature.

[0012] In a third aspect of the present invention, there is provided an electronic device, including: one or more processors; a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, enabling the one or more processors to implement the test optimization method for a large-capacity 3D flash memory provided by the present invention in the first aspect.

[0013] In a fourth aspect of the present invention, there is provided a computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the test optimization method for large-capacity 3D flash memory provided in the first aspect of the present invention.

[0014] The beneficial effects of the present invention are as follows: The present invention will design an optimization method for multi-temperature testing of flash memory reliability for long-term storage. This reliability testing method is designed based on the 3D NAND flash memory reliability mechanism, and can accurately simulate and predict the reliability degradation process of flash memory chips during data retention at different temperatures. The modeling method establishes a model based on the test data at room temperature, and uses a small amount of data in multi-temperature testing for model training, so as to obtain accurate prediction results at a lower test cost and improve the universality of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the basic process of the test optimization method for large-capacity 3D flash memory in some embodiments of the present invention; Figure 2 is a schematic diagram of the specific process of the test optimization method for large-capacity 3D flash memory in some embodiments of the present invention; Figure 3 is a flowchart of the room temperature programming / erasing / reading cycle test in some embodiments of the present invention; Figure 4 is a flowchart of the programming / erasing / reading test at the target temperature in some embodiments of the present invention; Figure 5 is a flowchart of establishing a discriminator mathematical model in some embodiments of the present invention; Figure 6 is a schematic diagram of the structure of the discriminator model in some embodiments of the present invention; Figure 7 is a specific structure diagram of the large-capacity 3D flash memory test optimization system in some embodiments of the present invention; Figure 8 is a schematic diagram of the structure of the large-capacity 3D flash memory test optimization device in some embodiments of the present invention; Figure 9 is a schematic diagram of the structure of an electronic device in some embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0017] Reference Figures 1 to 3, in the first aspect of the present invention, a method for optimizing the test of a large-capacity 3D flash memory is provided, including: S100. Based on a reference temperature and a target temperature, performing multiple reliability tests on random storage units in a target flash memory chip by grouping; S200. Respectively collecting test data of the target chip during reliability tests at the reference temperature and the target temperature, and constructing a data sample set according to the test data; the test data includes storage location, number of read / write operations, read / write time, and abnormal information; S300. Based on the data sample set and a few-shot training method, training a discriminator model for determining whether a flash memory chip fails; S400. Obtaining test data of the target flash memory chip during the reliability test at the target temperature, and inputting the test data into the discriminator model to obtain the test result of the target flash memory chip.

[0018] In step S100 of some embodiments of the present invention, the performing multiple reliability tests on random storage units in a target flash memory chip by grouping based on a reference temperature and a target temperature includes: randomly sampling from multiple target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; respectively performing programming, erasing, and read cycle tests on the two groups of target chips based on the reference temperature and the target temperature.

[0019] Specifically, a multi-level cell 3D NAND flash (TLC NAND flash) product under a certain manufacturing process is used as the object of failure prediction. First, samples are selected from the storage units in the flash memory chip. Randomly select the same number of storage blocks with odd block numbers and even block numbers, and ensure that the selected storage blocks are evenly distributed throughout the address range of the chip. For each selected storage block, multiple consecutive boundary physical address word line storage units are selected within the block, and the middle physical address word line storage units are randomly selected for testing. The test data used for the flash memory test is pseudo-random test data, the number of erase / program / read cycles Cpe is 1000, and the values of the temperature K are -40, 0, 55, and 80 degrees Celsius.

[0020] Furthermore, the respectively performing programming, erasing, and read cycle tests on the two groups of target chips includes: in each cycle test, sequentially performing erase, write, program, and read operations on the target chip, and marking the failed operations; determining whether the tested target chip fails, and determining whether to end the cycle test according to the determination result.

[0021] The specific test steps are as follows: 1. The test device performs an erase operation on the storage block to be tested; 2. Check the chip erase operation success flag. If the erase operation is successful, proceed to step 3. Otherwise, return to step 1. When the number of repetitions of step 1 exceeds 5 times, mark the storage block to be tested as a bad block and reselect the storage block to be tested; 3. The test device writes test data to the storage block to be tested; 4. Check the chip programming operation success flag. If the programming operation is successful, proceed to step 5. Otherwise, return to step 3. When the number of repetitions of step 3 exceeds 5 times, mark the storage block to be tested as a bad block and reselect the storage block to be tested; 5. Wait for 1 minute. The test device performs a read operation on the storage block to be tested and collects chip parameters; 6. Determine whether the chip to be tested has a fault. If a fault occurs, end the normal temperature cycle test. 7. Determine whether the number of erase / program / read cycles experienced by the storage block to be tested is less than 1000. If the programming / erase / read cycle is less than 1000, repeat steps 1 to 6.

[0022] In step S200 of some embodiments of the present invention, test data of the target chip for reliability testing at a reference temperature and a target temperature are respectively collected, and a data sample set is constructed according to the test data; the test data includes storage location, number of read / write operations, read / write time, and abnormal information; Reference Figure 4 , which shows a flowchart of programming / erasing / reading tests at the target temperature. The flash memory chip is placed in the test device, the temperature chamber is adjusted to the target temperature, an erase / program / read operation is performed once, chip parameters are collected, and the discriminator determines whether the chip to be tested has a fault; change the value of the target temperature K and repeat the above steps until all values of K are traversed.

[0023] It should be noted that the reference temperature is normal temperature, that is, the ambient temperature is 25°C: for industrial-grade chips, the operating temperature range is usually -40°C to 85°C. The operating temperature range of commercial-grade chips (also known as consumer-grade or civilian-grade) is usually 0°C to +70°C. Therefore, for commercial-grade chips, normal temperature can also be considered 25°C.

[0024] Reference Figure 5 , in step S300 of some embodiments of the present invention, the discriminator model for determining whether a flash memory chip has a fault trained based on the data sample set and the few-shot training method includes: using the test data of the target chip for n reliability tests at both the reference temperature and the target temperature as samples, where n≥1000; using the test data of n reference temperatures and target temperatures as samples, and using the results of m reliability tests with faults at the target temperature as labels, where m>n; based on the samples and the labels, training a discriminator model for determining whether a flash memory chip has a fault through the few-shot training method.

[0025] Specifically, samples are taken from the target model chips, and the sampled flash memory chips are divided into two groups, namely Group A and Group B. The flash memory chips in Group A are selected and subjected to normal temperature erase / program / read cycle tests according to Figure 3 the method. The chips in Group B are subjected to erase / program / read cycle tests at the target temperature according to Figure 4 the method.

[0026] The chip parameters obtained from the normal temperature tests of Group A and the chip parameters obtained from the n - time erase / program / read cycle tests of Group B at the target temperature K are used as the discriminator inputs, and whether a failure occurs after the m - time erase / program / read cycles of Group B at the target temperature K is used as the discriminator output; the relationship between the input chip parameters and the output discrimination result is calculated to establish a discriminator mathematical model. Among them, the calculation method for the relationship between the input chip parameters and the output discrimination result is any calculation method that can accurately establish the relationship between variables.

[0027] Referring to Figure 6 , the artificial neural network includes: an input layer, a hidden layer, a softmax layer, and an output layer. Among them, the number of hidden layers is 10, the number of units in each layer is 50, and the activation function is sigmoid. The model inputs are: the original number of error bits of the selected storage unit, the block number to which the storage unit belongs, the word line position to which the storage unit belongs, the number of program / erase cycles experienced by the storage unit, the test temperature of the storage unit, the erase operation time of the storage unit, the program operation time of the storage unit, the read operation time of the storage unit, the read - retry number of error bits, and the read - retry delay. The model output is: whether a failure occurs after the target number of erase / program / read cycles. The specific steps for modeling the discriminator model are as follows: 1. Initialize the training algorithm; 2. Input the data of the chips in Group A into the artificial neural network, and the training algorithm calculates the error between the output of the artificial neural network and the actual value; 3. The training algorithm adjusts the weights of the artificial neural network; 4. Determine whether the number of epochs reaches 100. If it reaches 100, stop training; otherwise, return to step 2. 5. The program outputs the discriminator model. For the trained discriminator model, reset the parameters of the input layer, softmax layer, and output layer of the model, that is, restore the parameters of the specified neural network layer to the values before cycling. The training algorithm adjusts the parameters of the discriminator model after resetting the input layer, softmax layer, and output layer. The specific steps are as follows: 1. Input the test data of the flash memory chips in Group B as training data into the discriminator model; 2. The training algorithm calculates the error between the output of the artificial neural network and the actual value and adjusts the weights of the artificial neural network; 3. Determine whether the error decreases or the number of epochs reaches 1000. If one of the conditions is met, stop training; 4. The program outputs the discriminator model.

[0028] Embodiment 2 Referring to Figure 8, in the second aspect of the present invention, a test optimization system 1 for a large-capacity 3D flash memory is provided, including: a test module 11, configured to perform multiple reliability tests on random storage units in a target flash memory chip in groups based on a reference temperature and a target temperature; a construction module 12, configured to respectively collect test data of the target chip during reliability tests at the reference temperature and the target temperature, and construct a data sample set according to the test data; the test data includes storage location, number of read / write operations, read / write time, and exception information; a training module 13, configured to train a discriminator model for determining whether a flash memory chip fails based on the data sample set and a few-shot training method; a judgment module 14, configured to obtain test data of the target flash memory chip during a reliability test at the target temperature, and input the test data into the discriminator model to obtain a test result of the target flash memory chip.

[0029] Further, the test module 11 includes: a sampling unit, configured to randomly sample from multiple target chips, and divide the sampled target chips into two groups based on the reference temperature and the target temperature; a test unit, configured to perform programming, erasing, and read cycle tests on the two groups of target chips respectively based on the reference temperature and the target temperature.

[0030] Reference Figure 7 , in an embodiment of the invention, the test optimization system for a large-capacity 3D flash memory includes a storage unit selection module for selecting characteristic storage units in a chip under test. An operation configuration module generates test scripts corresponding to different target temperatures K. A chip parameter acquisition module acquires parameters of the chip under test according to data from the storage unit selection module and the operation configuration module, and transmits the obtained data to a data storage module. A discriminator module makes a judgment based on the input data provided by the data storage module, and transmits the result to a result statistics module, thereby generating a test report of the chip.

[0031] Embodiment 3 Reference Figure 9 , in the third aspect of the present invention, an electronic device is provided, including: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enabling the one or more processors to implement the test optimization method for a large-capacity 3D flash memory in the first aspect of the present invention.

[0032] The electronic device 500 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 501, which may perform various appropriate actions and processes according to a program stored in the read-only memory (ROM) 502 or a program loaded from the storage device 508 into the random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. The input / output (I / O) interface 505 is also connected to the bus 504.

[0033] Generally, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 9 the electronic device 500 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had. Figure 9 Each block shown in

[0034] In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowchart can be implemented as computer software programs. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program includes program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, the above-described functions defined in the method of the embodiment of the present disclosure are performed. It should be noted that the computer-readable medium described in the embodiments of the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In an embodiment of the present disclosure, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0035] The above computer-readable medium can be included in the above electronic device; or it can exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more computer programs, and when the above one or more programs are executed by the electronic device, the electronic device is caused to: Computer program code for performing the operations of the embodiments of the present disclosure may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, Python, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0036] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0037] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A test optimization method for a large-capacity 3D flash memory, characterized in that, Including: Based on the reference temperature and the target temperature, perform multiple reliability tests on random storage units in the target flash memory chip by grouping; Collect the test data of the target chip during reliability tests at the reference temperature and the target temperature respectively, and construct a data sample set according to the test data; the test data includes storage location, number of read / write operations, read / write time, and abnormal information; Based on the data sample set and the few-shot training method, train a discriminator model for judging whether the flash memory chip fails; Obtain the test data of the target flash memory chip during the reliability test at the target temperature, and input the test data into the discriminator model to obtain the test result of the target flash memory chip.

2. The test optimization method for the large-capacity 3D flash memory according to claim 1, characterized in that The performing multiple reliability tests on random storage units in the target flash memory chip by grouping based on the reference temperature and the target temperature includes: Randomly sample from multiple target chips, and divide the sampled target chips into two groups based on the reference temperature and the target temperature; Based on the reference temperature and the target temperature, perform programming, erasing, and reading cycle tests on the two groups of target chips respectively.

3. The test optimization method for the large-capacity 3D flash memory according to claim 2, wherein The performing programming, erasing, and reading cycle tests on the two groups of target chips includes: In each cycle test, perform erase, write, program, and read operations on the target chip in sequence, and mark the failed operations; Judge whether the target chip under test fails, and determine whether to end the cycle test according to the judgment result.

4. The test optimization method for the large-capacity 3D flash memory according to claim 1, characterized in that The training a discriminator model for judging whether the flash memory chip fails based on the data sample set and the few-shot training method includes: Use the test data of the target chip that has undergone N reliability tests at both the reference temperature and the target temperature as samples, where n≥1000; Use the test data of n times at the reference temperature and the target temperature as samples, and use the results of failures in M reliability tests at the target temperature as labels, where m>n; Based on the samples and the labels, train a discriminator model for judging whether the flash memory chip fails through the few-shot training method.

5. The test optimization method for the large-capacity 3D flash memory according to claim 4, characterized in that 。 6. The test optimization method for a large-capacity 3D flash memory according to claim 1, wherein, The discriminator model is a neural network.

7. A test optimization system for a large-capacity 3D flash memory, characterized in that, Including: A test module for performing multiple reliability tests on random storage units in the target flash memory chip by grouping based on the reference temperature and the target temperature; A construction module for collecting the test data of the target chip during reliability tests at the reference temperature and the target temperature respectively, and constructing a data sample set according to the test data; the test data includes storage location, number of read / write operations, read / write time, and abnormal information; A training module for training a discriminator model for judging whether the flash memory chip fails based on the data sample set and the few-shot training method; A judgment module for obtaining the test data of the target flash memory chip during the reliability test at the target temperature, and inputting the test data into the discriminator model to obtain the test result of the target flash memory chip.

8. The test optimization system for a large-capacity 3D flash memory according to claim 7, characterized in that, The test module includes: A sampling unit for randomly sampling from multiple target chips and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; A test unit for performing programming, erasing, and reading cycle tests on the two groups of target chips respectively based on the reference temperature and the target temperature.

9. An electronic device, comprising: One or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the test optimization method for a large-capacity 3D flash memory according to any one of claims 1 to 6.

10. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the test optimization method for a large-capacity 3D flash memory according to any one of claims 1 to 6.

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