A broadband arbitrary reference adaptive clock synchronization device

Abstract

The present invention relates to the field of clock synchronization, and more specifically to a broadband arbitrary reference adaptive clock synchronization device. An input signal is amplified and shaped to generate two signals. One signal is sent to an FPGA, and the other is sent to an orthogonal power splitter. The mixed signal is then mixed with a local oscillator signal through an orthogonal modulator to generate a mixed signal. The mixed signal is then passed through a fixed frequency divider to generate a frequency-divided signal. This mixed signal is then phase-detected with a DDS output signal to generate an error voltage, which is then passed through a low-pass filter to control a crystal oscillator. The crystal oscillator's output is passed through a coupler to generate two signals. One signal serves as the global system clock, and the other signal is passed through a fixed frequency multiplier to obtain a multiplied signal. The multiplied signal passes through a filter amplifier and then to a power splitter. The power splitter splits the multiplied signal into two signals. One signal serves as the reference clock and generates a corresponding frequency point under the control of the FPGA to generate an output signal. The other signal is passed through an amplifier and serves as the local oscillator signal of the orthogonal modulator. The present invention is suitable for adaptive clock synchronization devices.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization, and in particular to a broadband arbitrary reference adaptive clock synchronization device. Background Art

[0002] Clock synchronization is a crucial component of electronics and communications technologies. It has a wide range of applications, including device synchronization, device cascading, and device cascading. As demands diversify, the traditional fixed 10MHz reference clock for instrumentation is no longer sufficient. An increasing number of applications require reference clocks with broadband adaptive coverage, making the design of broadband, arbitrary-reference synchronization circuits increasingly important.

[0003] Conventional instruments typically require an external reference clock input, most often a fixed 10MHz or 100MHz. Most instruments incorporate a high-performance local clock, such as 100MHz, and then use an integer phase detector to lock the 10MHz or 100MHz to the internal clock frequency. This method is simple and inexpensive, but it also has significant drawbacks: it only supports fixed frequencies and, due to the typically narrow loop filter, its synchronization range is also limited.

[0004] like Figure 1 Traditional clock synchronization schemes in the instruments shown here often use an integer phase detector and a fairly narrow filter to synchronize to an external reference. The reference output is equal to an integer multiple of the reference input, and the loop filter parameters are fixed. These limitations make this scheme difficult to meet the new requirements for wideband reference adaptation. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a broadband arbitrary reference adaptive clock synchronization device, which realizes input broadband arbitrary reference adaptive clock synchronization.

[0006] The present invention adopts the following technical solution to achieve the above-mentioned object. The present invention provides a broadband arbitrary reference adaptive clock synchronization device, including an amplification and shaping circuit unit 1, an orthogonal power divider 2, an orthogonal modulator 3, a fixed frequency divider 4, a phase detector 5, a low-pass filter 6, a crystal oscillator 7, a coupler 8, a fixed frequency multiplier 9, a filter amplifier 10, a power divider 11, a DDS (Direct Digital Synthesizer) module 12, an amplifier 13, and an FPGA (Field-Programmable Gate Array) module 14;

[0007] The input broadband reference signal is shaped by the amplifying and shaping circuit unit 1 to generate two signals, one of which is sent to the FPGA module 14 for frequency counting, and the other is sent to the orthogonal power divider 2 to generate two orthogonal signals, which are output to the orthogonal modulator 3. The two orthogonal signals are mixed with the local oscillator signal by the orthogonal modulator 3 to obtain a mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider 4 to obtain a divided signal F5. The divided signal F5 is used for phase detection with the output signal F3 from the DDS module 12 to generate an error voltage, which is processed by the low-pass filter 6 and then controls the crystal oscillator 7 in real time. The output of the crystal oscillator 7 is After passing through the coupler 8, two output signals are generated, one of which is used as the global system clock, and the other output signal is multiplied by the fixed multiplier 9 to obtain the multiplied signal F2. The multiplied signal F2 is processed by the filter amplifier 10 and output to the power divider 11. The power divider 11 divides the multiplied signal F2 into two signals. One of the multiplied signals F2 is used as the reference clock of the DDS module 12, and generates the corresponding frequency point to generate the output signal F3 under the control of the FPGA module 14. The other signal of the multiplied signal F2 is used as the local oscillator signal of the orthogonal modulator 3 after passing through the amplifier 13.

[0008] Furthermore, the output signal F3 of the DDS module is F2(FTW / 2 b ) = N*F1*(FTW / 2 b ), F2=N*F1, where FTW is the frequency control word of DDS, b is the number of bits of DDS module 12, and F1 is an output signal serving as the global system clock.

[0009] Furthermore, the orthogonal modulator 3 mixes with the local oscillator signal to obtain a mixing signal F4, F4=F2+Fref, and the mixing signal F4 is divided by the fixed frequency divider 4 to obtain a divided signal F5, F5=(F2+Fref) / R, then F5=(N*F1+Fref) / R, where Fref represents the input reference frequency, N is the multiplication coefficient of the fixed frequency multiplier 9, and R is the division coefficient of the fixed frequency divider 4.

[0010] Furthermore, when the FPGA module 14 completes the synchronous configuration of the DDS module, the output signal F3 of the DDS module is equal to the frequency-divided signal F5, then:

[0011] F5=(N*F1+Fref) / R= N*F1*(FTW / 2 b );

[0012] Fref= R* N*F1*(FTW / 2 b )- N*F1.

[0013] The beneficial effects of the present invention are:

[0014] The present invention introduces self-mixing technology, and introduces the frequency-multiplied signal F2 obtained after multiplying the output frequency into the reference port of the phase detector and the reference frequency Fref to achieve self-mixing, and then passes it through a fixed frequency divider to obtain the frequency-divided signal F5. This operation not only reduces the input operating frequency bandwidth, but also increases the reference frequency, reduces the equivalent frequency multiplication number, and improves the phase noise.

[0015] The output of the DDS is used as the feedback frequency in the feedback loop of the present invention, and the high resolution of the DDS is used to cleverly achieve any input frequency requirement.

[0016] The present invention uses a quadrature power divider and a quadrature modulator for reference modulation, cleverly avoiding the local oscillator and image frequency. If a traditional mixing filter solution is used, it will be very difficult to achieve the suppression of deviation from 1MHz.

[0017] The present invention introduces an FPGA module to count the input reference Fref in real time and dynamically configure the output frequency of the DDS, thereby realizing the input reference adaptive configuration without manual intervention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a block diagram of the clock synchronization circuit structure of a conventional instrument and equipment provided by the present invention;

[0019] Figure 2 This is a structural block diagram of a broadband arbitrary reference adaptive clock synchronization device provided by the present invention. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] The present invention provides a broadband arbitrary reference adaptive clock synchronization device, such as Figure 2 As shown, it includes an amplifying and shaping circuit unit 1, an orthogonal power divider 2, an orthogonal modulator 3, a fixed frequency divider 4, a phase detector 5, a low-pass filter 6, a crystal oscillator 7, a coupler 8, a fixed frequency multiplier 9, a filter amplifier 10, a power divider 11, a DDS module 12, an amplifier 13, and an FPGA module 14;

[0022] The input broadband reference signal is shaped by the amplifying and shaping circuit unit 1 to generate two signals, one of which is sent to the FPGA module 14 for frequency counting, and the other is sent to the orthogonal power divider 2 to generate two orthogonal signals, which are output to the orthogonal modulator 3. The two orthogonal signals are mixed with the local oscillator signal by the orthogonal modulator 3 to obtain a mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider 4 to obtain a divided signal F5. The divided signal F5 is used for phase detection with the output signal F3 from the DDS module 12 to generate an error voltage, which is processed by the low-pass filter 6 and then controls the crystal oscillator 7 in real time. The output of the crystal oscillator 7 is After passing through the coupler 8, two output signals are generated, one of which is used as the global system clock, and the other output signal is multiplied by the fixed multiplier 9 to obtain the multiplied signal F2. The multiplied signal F2 is processed by the filter amplifier 10 and output to the power divider 11. The power divider 11 divides the multiplied signal F2 into two signals. One of the multiplied signals F2 is used as the reference clock of the DDS module 12, and generates the corresponding frequency point to generate the output signal F3 under the control of the FPGA module 14. The other signal of the multiplied signal F2 is used as the local oscillator signal of the orthogonal modulator 3 after passing through the amplifier 13.

[0023] The specific process of implementing synchronous configuration is as follows:

[0024] Step 1: Count the input frequency through the controller FPGA module 14 to complete the input frequency value confirmation and obtain Fref;

[0025] Step 2: The controller FPGA module 14 calculates the output frequency F5 of the fixed frequency divider 4 according to the calculated input frequency value Fref, and then configures the output frequency F3 of the DDS according to the calculated value of F5 so that F3=F5, completing the synchronization configuration.

[0026] The working principle of the present invention is as follows: F2=N*F1, the output of DDS F3=F2FTW / 2 b = N*F1*FTW / 2 b , where FTW is the frequency control word of DDS, b is the number of bits of the DDS module, and the output of the orthogonal modulator 3 is F4=F2+Fref. The output of this signal after passing through the fixed frequency divider 4 is F5=F2+Fref / R, which can be sorted out as follows:

[0027] F5=N*F1+Fref / R;

[0028] Wherein, N is the frequency multiplication coefficient of the fixed frequency multiplier 9, and R is the frequency division coefficient of the fixed frequency divider 4;

[0029] When the FPGA module 14 completes the DDS module configuration, F3=F5, so F5=N*F1+Fref / R= N*F1*FTW / 2 b. Then we get Fref= R*N*F1*FTW / 2 b - N*F1;

[0030] The F5 calculation formula shows that the bandwidth of the original wideband reference is reduced by 1 / R after passing through the fixed divider 4. Simultaneously, the introduction of the internal clock F2 for self-mixing reduces the bandwidth while still increasing the phase detection frequency, thus preventing significant phase noise degradation. Furthermore, the Fref calculation formula shows that the resolution of any reference is determined by the DDS, and using a high-bit DDS allows for nearly any resolution.

[0031] In one embodiment of the present invention, the input frequency is 1MHz-100MHz, with a bandwidth of up to 100MHz. The frequency division coefficient R of frequency divider 4 is fixed at 40, the output frequency F1 of oven-controlled crystal oscillator 7 is fixed at 100MHz, and the multiplication coefficient N of frequency multiplier 9 is fixed at 10. Therefore, the range of phase-locked frequency F5 is 25.05-27.5MHz. It can be seen that after frequency division, the reference frequency variation range is less than 2.5MHz, which effectively reduces the pressure of circuit design. The DDS is an AD9912 with a 48-bit bit width, which can achieve a resolution of 4uHz. This embodiment can automatically output a constant 100MHz synchronous clock based on any external Fref value.

[0032] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.

Claims

1. A broadband arbitrary reference adaptive clock synchronization device, characterized in that: It includes an amplifying and shaping circuit unit (1), an orthogonal power divider (2), an orthogonal modulator (3), a fixed frequency divider (4), a phase detector (5), a low-pass filter (6), a crystal oscillator (7), a coupler (8), a fixed frequency multiplier (9), a filter amplifier (10), a power divider (11), a DDS module (12), an amplifier (13), and an FPGA module (14); The input broadband reference signal is shaped by the amplifying and shaping circuit unit (1) to generate two signals, one of which is sent to the FPGA module (14) for frequency counting, and the other is sent to the orthogonal power divider (2) to generate two orthogonal signals, which are output to the orthogonal modulator (3). The two orthogonal signals are mixed with the local oscillator signal by the orthogonal modulator (3) to obtain a mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider (4) to obtain a divided signal F5. The divided signal F5 is used for phase detection with the output signal F3 from the DDS module (12) to generate an error voltage, which is processed by the low-pass filter (6) and then controls the crystal oscillator (7) in real time. The crystal oscillator (7) The output is passed through a coupler (8) to generate two output signals, one of which is used as a global system clock, and the other is multiplied by a fixed frequency multiplier (9) to obtain a frequency-multiplied signal F2. The frequency-multiplied signal F2 is processed by a filter amplifier (10) and output to a power divider (11). The power divider (11) divides the frequency-multiplied signal F2 into two signals, one of which is used as a reference clock for a DDS module (12) and generates an output signal F3 at a corresponding frequency point under the control of an FPGA module (14). The other of which is used as a local oscillator signal for an orthogonal modulator (3) after passing through an amplifier (13).

2. The broadband arbitrary reference adaptive clock synchronization device according to claim 1, characterized in that: The output signal F3 of the DDS module (12) is F2*(FTW / 2 b ), where F2=N*F1, then F3= N*F1*(FTW / 2 b ), where FTW is the frequency control word of the DDS module, b is the number of bits of the DDS module (12), F1 is an output signal of the global system clock, and N is the multiplication factor of the fixed multiplier (9).

3. The broadband arbitrary reference adaptive clock synchronization device according to claim 2, characterized in that: The orthogonal modulator (3) mixes the local oscillator signal to obtain a mixed signal F4, F4=F2+Fref. The mixed signal F4 is divided by the fixed frequency divider (4) to obtain a divided signal F5, F5=(F2+Fref) / R, then F5=(N*F1+Fref) / R, where Fref represents the input reference frequency, N is the multiplication coefficient of the fixed frequency multiplier (9), and R is the division coefficient of the fixed frequency divider (4).

4. The broadband arbitrary reference adaptive clock synchronization device according to claim 3, characterized in that: When the FPGA module (14) completes the synchronous configuration of the DDS module (12), the output signal F3 of the DDS module (12) is equal to the frequency division signal F5, then: F5=(N*F1+Fref) / R= N*F1*(FTW / 2 b ); Fref= R* N*F1*(FTW / 2 b )- N*F1。

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