Mixing fitting FPGA technology chaotic signal generator realization method

Abstract

According to the hybrid fitting FPGA technology chaotic signal generator implementation method, a memristive chaotic system with complex nonlinear characteristics such as a hyperbolic function and a natural logarithm can be efficiently generated on a resource-limited FPGA. According to the scheme, target function slope distribution is analyzed, binomial fitting is adopted for slope steep intervals, hardware architecture is optimized to reduce resource occupation, and linear fitting is adopted for slope gentle intervals to simplify implementation logic. According to the memristor chaotic system model constructed based on the hybrid strategy, an iterative operation module is integrated on a chip. Experimental verification shows that the method obviously reduces the consumption of storage resources while keeping high precision, and is particularly suitable for chaotic signal generation scenes with low power consumption and high real-time requirements.

Description

Technical Field

[0001] The present invention belongs to the field of nonlinear dynamics, and specifically relates to a method for implementing a chaotic signal generator of FPGA technology with hybrid fitting. Background Art

[0002] FPGA (Field Programmable Gate Array), as an important tool for hardware implementation of information encryption currently, has been widely studied and applied both at home and abroad. Many foreign research institutions and scholars use FPGA for the modeling, simulation, and implementation of encryption algorithms of memristive chaotic systems. By combining chaotic systems with traditional encryption algorithms, the security and efficiency of information encryption are improved. The applications of FPGA in chaotic encryption include key generation based on chaotic mapping, generation of chaotic sequences, and chaotic scrambling, etc. Meanwhile, many domestic research institutions and scholars also study chaotic systems on FPGA and implement information encryption. The specific approach is to design and implement nonlinear chaotic digital circuits, develop a hardware implementation platform for chaotic systems, and further study chaotic encryption algorithms and chaotic sequence generators. In addition, some researchers also combine memristive chaotic systems with other encryption algorithms such as AES, DES, etc. to improve the effect and security of information encryption. These systems not only exhibit rich dynamic characteristics but also possess excellent stability and high repeatability.

[0003] With the in-depth research on memristive chaotic systems, how to accurately implement their mathematical models using existing electronic circuit technologies has become a key problem to be solved urgently. Although analog circuits can implement memristive chaotic systems, they are affected by transistor mismatch and process deviation, and have inherent defects such as long development cycles and poor replication effects. Digital platforms such as ASIC, FPGA, and single-chip microcontrollers can effectively avoid component matching problems. Among them, FPGA has become a better choice due to its advantages of parallel computing ability, hardware reconfigurability, and real-time performance.

[0004] However, the existing implementation of memristive chaotic systems based on FPGA has significant deviations between the hardware implementation results and the simulation model due to insufficient calculation accuracy of nonlinear functions (such as tanh, cosh, ln, etc.). Especially when the system contains multiple nonlinear functions and runs for a long time, the cumulative error will cause the iteration values to diverge. Aiming at the problem of insufficient calculation accuracy existing in the existing FPGA technology when implementing memristive chaotic systems containing multiple nonlinear functions (such as tanhx, coshx, lnx, etc.), the present invention proposes a method for implementing a memristive chaotic circuit of FPGA with lower resource occupancy, better real-time performance, and higher calculation accuracy.

[0005] Technical comparison with the published application CN119272828B "Method for implementing a fractional-order memristive Hopfield neural network circuit based on FPGA"; This application CN119272828B uses the G-L fractional derivative definition and the short-term memory principle, and only through multi-segment linear fitting of the hyperbolic tangent function, it completes the FPGA circuit implementation of the fractional-order memristive Hopfield model.

[0006] This application analyzes the slope characteristics of the hyperbolic tangent function, hyperbolic cotangent function, and natural logarithm, and combines the FPGA resources and accuracy requirements. It selects to use binomial curve fitting in the interval with a larger slope and optimizes the hardware architecture to reduce resource consumption, and uses linear fitting in the interval with a smaller slope to simplify the implementation of the objective function.

[0007] This application CN119272828B uses a 64-bit RAM IP core to store the slope term and intercept term coefficients of a linear function, and uses a multiplier and an adder to perform fitting to implement a non-linear function. However, when applied to the natural logarithm function ln(x), since a straight line cannot fit the function value at ln(0+) well, the larger the x approaches 0+, the greater the error will be. To make up for this error, a large number of segmentation intervals need to be increased.

[0008] This application uses a 96-bit RAM IP core to store the three coefficients of a quadratic function, and uses three multipliers and two adders to perform fitting to implement a non-linear function. Taking the slope as the demarcation point between linear and curve fitting, curve fitting is adopted near ln(0+), which can better approximate the curve characteristics of ln(x), reduce the number of segments and fitting errors.

[0009] This application CN119272828B does not use Euler iteration for design. The overall module structure is different from this application, and the iteration process is more complex than this application, requiring more iteration time.

[0010] There are essential differences between the two in the implementation of technical solutions.

[0011] This application CN119272828B uses the G-L fractional derivative definition and the short-term memory principle, which is applicable to the design of fractional-order memristive neural networks and is not applicable to conventional integer-order memristive chaotic systems.

[0012] This application does not belong to a fractional-order neural network circuit and belongs to a method for implementing a memristive chaotic circuit.

[0013] There are essential differences between the two in the application scenarios.

[0014] Technical comparison with the published application CN116720554B "A method for implementing a multi-segment linear fitting neuron circuit based on FPGA technology"; This application CN116720554B belongs to an improved Fitzhugh-Nagumo neuron model. Mathematically, the model structure is a two-dimensional differential equation with a hyperbolic tangent function, a sine function, and an external excitation source. The second-order Runge-Kutta iteration is used during iteration.

[0015] This application belongs to a memristive chaotic circuit model. Mathematically, the model structure is a three-dimensional differential equation with a hyperbolic tangent function, a hyperbolic cotangent function, and the natural logarithm. The Euler iteration method is used, and the number of iteration steps is less than that of the second-order Runge-Kutta iteration.

[0016] This application CN116720554B uses a hardware function fitting method of a 64-bit RAM IP core when designing the hyperbolic tangent function. This method stores the slope term and the intercept term coefficients of the linear function once, and uses a multiplier and an adder to achieve the linear piecewise fitting of the non-linear function. However, when applied to the natural logarithm function ln(x), this method has significant limitations near the boundary of the function domain (x→0+): Since the linear fitting cannot accurately approximate the asymptotic characteristics of ln(x) in this interval, as x approaches 0+, the fitting error shows a monotonically increasing trend. To meet the accuracy requirements, the number of segmented intervals has to be increased significantly. In addition, Patent CN116720554B also includes implementing the sine function using a segmentation method (non-piecewise linear fitting), and circular addressing is achieved by predefining the function values of the interval segments and then judging the address of the sine function.

[0017] This application realizes the hyperbolic tangent function, the hyperbolic cotangent function, and the natural logarithm by storing the three coefficients of the quadratic function in a 96-bit RAM IP core, and uses three multipliers and two adders for fitting. With the slope as the demarcation point between the straight line and the curve fitting, curve fitting is adopted near ln(0+), which can better approximate the curve characteristics of ln(x), reduce the number of segments and the fitting error.

[0018] There are essential differences between the two in the implementation of technical solutions. Summary of the Invention

[0019] To solve the above technical problems, the present invention proposes a method for implementing a chaotic signal generator using hybrid fitting FPGA technology to construct a memristive chaotic system with high precision and low resource occupancy. Combining the FPGA resources and accuracy requirements, the slope of the target non-linear function is analyzed, and the slope threshold is determined through engineering practice. When the slope of a certain interval of the function is greater than the threshold, binomial curve fitting is used, and the hardware architecture is optimized in the FPGA to reduce resources. When the slope is less than the threshold, linear fitting is used to simplify the fitting function, which is implemented through simple logic units. The fitting results are selected to construct a memristive chaotic system model, and the iterative module of the memristive chaotic system is integrated on the FPGA. Thus, a memristive chaotic system containing multiple non-linear functions is implemented in a manner of high precision and low resource occupancy.

[0020] To achieve the above object, the technical solution adopted by the present invention is as follows: A method for implementing a chaotic signal generator using hybrid fitting FPGA technology, the specific steps are as follows: 1) Combining the FPGA resource constraints and accuracy requirements, analyze the slope of the target non-linear function, and determine the slope threshold through engineering experiments; 2) Divide the function intervals based on the slope threshold; When the slope of a certain interval of the function is greater than the threshold, use the binomial curve fitting method to design the function fitting module for this interval, and specifically optimize the FPGA hardware architecture to reduce resource consumption; When the slope is less than the threshold, use the linear fitting method to simplify the function of this interval, and implement the fitting function through simple logic units in the FPGA; 3) Select the fitting module results of each interval to construct a mathematical model of the memristive chaotic system, and integrate the iterative calculation module of the memristive chaotic system on the FPGA; 4) According to the given iterative formula, use the Verilog hardware description language to build a state machine control module on the Xilinx ISE development platform to realize the loop execution of the iterative formula. Subsequently, use MATLAB to convert the obtained IEEE754 floating-point number format and draw a graph, and compare and analyze it with the result generated by Visual Studio C++; 5) Finally, download the generated bit file after compilation and synthesis to the FPGA via the JTAG interface, and observe the actual output signal with an oscilloscope.

[0021] As a further improvement of the present invention, the function processing of the function fitting module designed by the binomial curve fitting method in step 2) is specifically processed as follows: 21. Respectively take the derivatives of the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions. First, find the derivatives of these three functions, and then draw the slope images in the corresponding fitting intervals based on the derivative results; 22. According to the actual engineering requirements, determine the slope-dominated division intervals for linear fitting and curve fitting. When the slope is greater than the set threshold, perform quadratic curve fitting; when the slope is less than the set threshold, perform linear fitting. When performing linear or curve fitting, use Visual studio C++ to write the least squares method to determine the fitting coefficients of the straight line and the curve. 23. For the coefficients obtained from the curve fitting of a single non-linear function, there are a total of 3 coefficients, which need to be encoded into 96-bit data in a group of 3 32-bit IEEE754 floating-point numbers. The high 32 bits are the quadratic term coefficients, the middle 32 bits are the linear term coefficients, and the low 32 bits are the constants. For the coefficients of linear fitting, there are 2 coefficients in total, which need to be encoded into 64-bit data in a group of 2 32-bit IEEE754 floating-point numbers. The high 32 bits are the linear term coefficients, and the low 32 bits are the constants, which are used for the generation of the COE file and the production of the RAM IP core in Xilinx. 24. When searching for the storage address of the fitting coefficients in the fitting function RAM IP core through the independent variable, it is necessary to search in combination with the division interval.

[0022] As a further improvement of the present invention, in the function processing of the function fitting module designed by the binomial curve fitting method, the specific process of using the least squares method to determine the fitting coefficients of the straight line and the curve is as follows: Suppose the data to be fitted is , and these data are represented by , is the fitting value, is the independent variable, is a constant, and for each data point, the fitting value is , the actual value is , the residual is , the input variable of the th data point is , is a positive integer, expressed as ; The goal of the least squares method is to minimize the sum of the squares of the residuals of all data points: ; By solving the minimum value of the objective function through the above formula, the estimated values of the parameters are obtained. In simple linear regression, when the fitting function is assumed to be , the objective function is: ; Furthermore, when the fitting function is assumed to be , the objective function is: ; By ,​​​​​​​​​​ and Taking the partial derivatives and setting them equal to zero will yield the normal equations, and then the constants , and can be estimated. In the above equations, is the intercept, is the linear slope, is the curve curvature, is the number of data points.

[0023] As a further improvement of the present invention, in step 3), when constructing the mathematical model of the memristive chaotic system, the selected memristive chaotic model is: ; ; ; In the above equations is the voltage value of the resistor device in the memristive circuit, is the voltage value of the memristor device in the memristive circuit, is the voltage value of the capacitor device in the memristive circuit, is a positive system parameter, is the time.

[0024] As a further improvement of the present invention, in step 3), an iterative calculation module of the system is integrated on the FPGA, and the iterative calculation is specifically as follows; The differential equation of the memristive chaotic system uses the Euler iteration formula to obtain the following iterative formula of the memristive chaotic system: ; In the above equations is the voltage value of the resistor device in the memristive circuit at the previous moment, is the voltage value of the memristor device in the memristive circuit at the next moment, is the voltage value of the capacitor device in the memristive circuit at the next moment, is the voltage value of the resistor device in the memristive circuit at the current moment, is the voltage value of the memristor device in the memristive circuit at the current moment, is the voltage value of the capacitor device in the memristive circuit at the current moment, is a positive system parameter, is the iteration step size of the system.

[0025] The advantages of the present invention are: The hybrid straight line and curve fitting strategy applied in the present invention can quickly and accurately match the target non-linear function. Tests were carried out on the Spartan-6 series FPGA development board, and the data processing delay was significantly reduced compared with the traditional scheme. This method first analyzes the slope of the non-linear function and determines a reasonable threshold in combination with FPGA resources and accuracy requirements. When the slope of the function interval exceeds the threshold, binomial curve fitting is used, and when it is lower than the threshold, straight line fitting is adopted, achieving the efficient simplification of the non-linear function of the memristive chaotic system in the FPGA. This significantly reduces the resource occupancy of the iterative solution module of the memristive chaotic system, while improving the system calculation accuracy and operation efficiency. This method not only has a good fitting effect on common non-linear functions, but also has good adaptability to complex transcendental functions, etc., and has important application potential and research significance in the fields of chaotic signal generation, secure communication encryption, and construction of memristive neural networks. Description of the Drawings

[0026] Figure 1 It is a schematic diagram of the least squares method fitting; Figure 2 It is a hyperbolic tangent function approximation module; Figure 3 It is a Verilog algorithm overall module diagram; Figure 4 It is a schematic diagram of the Euler iteration module principle; Figure 5 It is a schematic diagram of the overall connection; Figure 6 It is a z-y chaotic phase diagram captured by the oscilloscope with k = 2.07. Specific Embodiments

[0027] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments: The present invention proposes a method for implementing a chaotic signal generator based on FPGA technology with hybrid fitting, which focuses on solving the problems of accuracy and resource consumption of complex non-linear functions such as hyperbolic tangent, hyperbolic cotangent, and natural logarithm in FPGA implementation. This method analyzes the slope characteristics of the function, sets a threshold to achieve partition processing, uses binomial curve fitting in the high slope interval to ensure accuracy, and uses straight line fitting in the low slope interval to optimize resources. Finally, a memristive chaotic system with high precision and low resource occupancy is implemented on the FPGA, providing an innovative solution for chaotic signal generation.

[0028] The specific steps of the algorithm are as follows: 1. First, the processing steps of the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions: Step 1), take the derivatives of the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions respectively. To facilitate the drawing of the slope change images of the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions within the fitting interval, the derivatives of these three functions need to be calculated first. According to the requirements of drawing the slope images based on the derivatives and engineering simplification, selectively perform curve or straight-line fitting; Step 2), according to the actual engineering requirements, determine the slope-dominated division intervals for straight-line fitting and curve fitting. When the slope is greater than the set threshold, perform quadratic curve fitting; when the slope is less than the set threshold, perform straight-line fitting. In the present invention, when the independent variable of the hyperbolic tangent function satisfies , the interval where the slope is greater than 0.786448 is for curve fitting, and the interval where the slope is less than 0.786448 is for straight-line fitting. At this time . When the independent variable of the hyperbolic cotangent function satisfies , the interval where the slope is greater than 0.521095 is for curve fitting, and the interval where the slope is less than 0.521095 is for straight-line fitting. At this time . When the independent variable of the natural logarithm function satisfies Figure 1 , the interval where the slope is greater than 2 is for curve fitting, and the interval where the slope is less than 2 is for straight-line fitting. At this time . When performing fitting with a straight line or a curve, the least squares method is used to determine the fitting coefficients of the straight line and the curve through Visual studio C++; The schematic diagram of the least squares method fitting is as shown in . Assume that the data to be fitted is , and these data are represented by . is the fitted value, is the independent variable, is a constant, and for each data point, the fitted value is , the actual value is , the residual is , and the input variable of the th data point is . The goal of the least squares method is to minimize the sum of the squares of the residuals of all data points: ; By solving the minimum value of the objective function through the above formula, the estimated values of the parameters are obtained. In simple linear regression, when the fitting function is assumed to be , the objective function is: ; For a further assumed fitting function When, the objective function is: ; By taking the partial derivatives of , and and setting them equal to zero, the normal equation can be obtained, and then the estimated values of the constants , and can be solved. In the above formula, is the intercept, is the linear slope, is the curve curvature, is the number of data points.

[0029] Step 3), for the coefficients of the curve fitting of a single non-linear function, there are 3 in total, and they need to be encoded into 96-bit data in a group of 3 32-bit IEEE754 floating-point numbers. The high 32 bits are the quadratic term coefficients, the middle 32 bits are the linear term coefficients, and the low 32 bits are the constants. For the coefficients of the straight line fitting, there are 2 in total, and they need to be encoded into 64-bit data in a group of 2 32-bit IEEE754 floating-point numbers. The high 32 bits are the linear term coefficients, and the low 32 bits are the constants, which are used for the generation of the.COE file and the production of the RAM IP core in Xilinx; Step 4), in the present invention, the fitting intervals of the straight line and the curve are divided by the slope value. When the hyperbolic tangent function is in the curve fitting interval , the interval is divided into 10 segments, and the straight line interval is , and the divided interval is 1250 segments. When the hyperbolic cotangent function is in the curve fitting interval , the interval is also divided into 10 segments, and the straight line interval is , and the divided interval is 3150 segments. When the natural logarithm function is in the curve fitting interval , the interval is divided into 100 segments. In particular, the first interval is set as , and the straight line interval is , and the divided interval is 1900 segments. Secondly, by using the boundedness of the hyperbolic tangent function, when constructing the hyperbolic tangent function, the function value with the independent variable greater than 3 is forced to be converted to 1. When constructing the hyperbolic tangent function with a negative independent variable, the odd function property is used, and only half of the original RAM IP core resources are consumed. When constructing the hyperbolic cotangent function, the even function property is used, and only half of the original RAM IP core resources are consumed. Through practice, the function construction module can be designed as Figure 2As shown in the figure, the independent variable is amplified by a multiplier to a multiple corresponding to the segmented interval and converted into a decimal fixed-point number. Then, the integer part is retained for addressing, the parameter values of the quadratic curve fitting are searched and stored, and the quadratic curve fitting function value can be constructed by calling the multiplier and adder. When the expandable module in the figure is omitted, the independent variable is directly multiplied by the slope term through the multiplier and then added to the intercept term to obtain the linear fitting.

[0030] 2. According to the above steps 1), 2), 3), and 4), select the memristive chaotic system model as: ; ; ; In the above formula is the voltage value of the resistive device in the memristive circuit, is the voltage value of the memristive device in the memristive circuit, is the voltage value of the capacitive device in the memristive circuit, is a positive system parameter, is the time, take and set , , .

[0031] 3. According to the differential equation of the above memristive chaotic system and using the Euler iteration formula, the iteration formula of the memristive chaotic system is obtained as follows: ; In the above formula are the voltage values of the resistor, memristor, and capacitor at the current moment in the memristive circuit. When the iteration is performed for the first time, select the parameter , and stipulate that are the voltage values of the resistor, memristor, and capacitor at the next moment calculated by the iteration formula, , , , is the system iteration step size.

[0032] 4. According to the above mathematical iteration formula, the Verilog hardware design is implemented using the state machine architecture in the Xilinx ISE development environment. After completing the RTL coding, functional verification is performed in the joint simulation environment of Xilinx ISE and ModelSim by writing a Testbench. The hexadecimal data generated by the simulation is parsed and converted into decimal values by MATLAB, and waveform analysis and algorithm verification are performed through plotting. The overall RTL architecture of the system is as Figure 3 shown. The Euler iteration module is constructed through the adder IP core and multiplier IP core of IEEE754 floating-point numbers, and can generate x n+1 、yn+1 , z n+1 Iterative value. Due to the pipelined parallel design of the FPGA, while generating the iterative value, the data conversion module can convert the data into fixed-point numbers and start the D / A conversion module, thus realizing the decimal output of the iterative value.

[0033] Figure 4 is the schematic diagram of the Euler iterative module. Adopting a parallel pipelined design, it can generate iterative values in less than a microsecond. The input x n and y n initial values can generate three non-linear functions, namely ln(x n +b), ln(bcosh(y n )) and tanh(y n ) through the non-linear function construction module. In the multiplier 1 of the first-level pipeline, the initial value of z n is inverted to obtain negative z n which is multiplied by 2. In multiplier 2, y n is multiplied by k. Adder 1 realizes the addition of 2k and 1. Adder 2 realizes the addition of negative ln(x n +b) and ln(bcosh(y n ))). In the adder 1 of the second-level pipeline, negative z n is added to the result of multiplier 2 in the first-level pipeline. Multiplier 1 realizes the multiplication of y n and the value of adder 1 in the first-level pipeline. Multiplier 2 realizes the multiplication of parameter a and the value of adder 2 in the first-level pipeline. Multiplier 3 realizes the multiplication of the value of b + x n and the value of tanh(y n ). In the adder 1 of the third-level pipeline, the value of multiplier 1 in the first-level pipeline is added to the value of multiplier 1 in the second-level pipeline. In adder 2, the value of adder 1 in the second-level pipeline is added to the negative product value obtained by inverting multiplier 3 in the second-level pipeline. In the fourth-level pipeline, multiplier 1 realizes the multiplication of the step size h and adder 1 in the third-level pipeline. Multiplier 2 realizes the multiplication of the complementary h and multiplier 2 in the second-level pipeline. Multiplier 3 realizes the multiplication of the step size h and the value of adder in the third-level pipeline. In the fifth-level pipeline, adders 1, 2, and 3 are used to add the multipliers 1, 2, and 3 in the fourth-level pipeline to the iterative initial values z n , x n , y n . Subsequently, the adder value output is the iterative value z n+1 , x n+1 , y n+1 at the next moment.

[0034] 5. When the simulation results of Modelsim are consistent with those of the compilation platform Visual studio C++, the bit file generated after compilation and synthesis on the Xilinx ISE platform can be burned into the FPGA through the JTAG interface and observed with an oscilloscope. The connection block diagram is as shown in Figure 5 shown below.

[0035] 6. The chaotic signals generated by the memristive chaotic system captured by the oscilloscope are as shown in Figure 6 shown below.

[0036] In summary, the present invention proposes a method for implementing a chaotic signal generator based on the FPGA technology of hybrid straight line and curve fitting, which can achieve a memristive chaotic system containing tanh(x), cosh(x), and ln(x) with high precision and high efficiency using fewer RAM IP core resources under the condition of limited resources of the Spartan-6 series FPGA. This method combines the FPGA resources and the accuracy requirements, analyzes the slope of the target non-linear function, and determines the slope threshold through engineering practice. When the slope of a certain interval of the function is greater than the threshold, binomial curve fitting is used, and the hardware architecture is optimized in the FPGA to reduce resources. When the slope is less than the threshold, straight line fitting is used to simplify the fitting function, which is implemented through simple logic units. The fitting results are selected to construct a memristive chaotic system model, and an iterative module of the memristive chaotic system is integrated on the FPGA. The above is only one of the implementation modes of the present invention. For those of ordinary skill in the relevant technical field, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

[0037] The above is only a preferred embodiment of the present invention, and it is not intended to limit the present invention in any other form. Any modification or equivalent change made according to the technical essence of the present invention still belongs to the scope of protection required by the present invention.

Claims

1. Implementation method of a chaotic signal generator using a hybrid-fitted FPGA technology, characterized in that: The specific steps are as follows: 1) Combine the FPGA resource constraints and precision requirements, analyze the slope of the target non-linear function, and determine the slope threshold through engineering experiments; 2) Divide the function into intervals based on the slope threshold; When the slope of a certain interval of the function is greater than the threshold, use the binomial curve fitting method to design the function fitting module for this interval, and optimize it specifically in the FPGA hardware architecture to reduce resource consumption; When the slope is less than the threshold, use the straight line fitting method to simplify the function of this interval, and implement the fitting function through the simple logic unit in the FPGA; 3) Select the fitting module results of each interval to construct the mathematical model of the memristive chaotic system, and integrate the iterative calculation module of the memristive chaotic system on the FPGA; 4) According to the given iterative formula, use the Verilog hardware description language to build a state machine control module on the Xilinx ISE development platform to realize the loop execution of the iterative formula. Subsequently, use MATLAB to convert the obtained IEEE754 floating-point number format and draw a graph, and compare and analyze it with the result generated by Visual Studio C++; 5) Finally, download the generated bit file after compilation and synthesis to the FPGA via the JTAG interface, and observe the actual output signal with an oscilloscope.

2. The method for realizing a chaotic signal generator based on FPGA technology with hybrid fitting according to claim 1, wherein: In step 2), the function processing of the function fitting module designed by the binomial curve fitting method for this interval is specifically as follows:

21. Differentiate the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions respectively. First, find the derivatives of these three functions, and then draw the slope images in the corresponding fitting intervals based on the derivative results; 22. According to the actual engineering requirements, determine the slope-dominated division intervals for straight line fitting and curve fitting. When the slope is greater than the set threshold, fit with a quadratic curve. When the slope is less than the set threshold, fit with a straight line. When fitting with a straight line or a curve, use Visual studio C++ to write the least squares method to determine the fitting coefficients of the straight line and the curve; 23. For a single non-linear function, there are 3 fitting coefficients for the curve fitting required, which need to be encoded into 96-bit data in a group of 3 32-bit IEEE754 floating-point numbers. The high 32 bits are the quadratic term coefficients, the middle 32 bits are the linear term coefficients, and the low 32 bits are the constants. There are 2 fitting coefficients for the straight line fitting, which need to be encoded into 64-bit data in a group of 2 32-bit IEEE754 floating-point numbers. The high 32 bits are the linear term coefficients, and the low 32 bits are the constants, which are used for the generation of the COE file and the production of the RAM IP core in Xilinx; 24. When searching for the storage address of the fitting coefficient in the fitting function RAM IP core through the independent variable, it is necessary to search in combination with the divided interval.

3. The method for realizing a chaotic signal generator based on FPGA technology with hybrid fitting according to claim 2, wherein: The specific process of using the least squares method to determine the fitting coefficients of the straight line and the curve during the function processing of the function fitting module designed by the binomial curve fitting method is as follows: Suppose the data to be fitted is , and these data are represented by . is the fitted value, is the independent variable, is a constant, and the fitted value for each data point is , the actual value is , the residual is , the input variable of the -th data point is , is a positive integer, denoted as ; The goal of the least squares method is to minimize the sum of the squares of the residuals of all data points: ； Solve the objective function through the above formula The minimum value of, the estimated value of the parameter is obtained. In simple linear regression, the fitting function is assumed to be When, the objective function is: ； A further fitting function is assumed to be When, the objective function is: ； By taking the partial derivatives of , and and setting them equal to zero, the normal equations can be obtained, and then the estimated values of the constants , and can be solved. In the above equations, is the intercept, is the linear slope, is the curve curvature, and is the number of data points.

4. The implementation method of the FPGA technology chaotic signal generator with hybrid fitting according to claim 2, characterized in that: In the construction of the mathematical model of the memristive chaotic system in step 3), the selected memristive chaotic model is: ； ； ； In the above formula is the voltage value of the resistive device in the memristive circuit, is the voltage value of the memristive device in the memristive circuit, is the voltage value of the capacitive device in the memristive circuit, is a positive system parameter, is time.

5. The implementation method of the FPGA technology chaotic signal generator with hybrid fitting according to claim 3, characterized in that: In step 3), an iterative calculation module of the system is integrated on the FPGA, and the iterative calculation is specifically as follows; For the differential equation of the memristive chaotic system, the Euler iterative formula is used to obtain the iterative formula of the memristive chaotic system as follows: ； In the above formula is the voltage value at a certain moment under the resistive device in the memristive circuit, is the voltage value at the next moment of the memristive device in the memristive circuit, is the voltage value at the next moment of the capacitive device in the memristive circuit, is the voltage value at the current moment of the resistive device in the memristive circuit, is the voltage value at the current moment of the memristive device in the memristive circuit, is the voltage value at the current moment of the capacitive device in the memristive circuit, is a positive system parameter, is the iteration step size of the system.

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