FPGA-based overhead processing device and method for fine-grained optical transport network

Abstract

The present application discloses an overhead processing device for a fine-grained optical transport network based on an FPGA. Various bit-width conversion modules are used to convert the bit width of input fgODUflex signals. The converted fgODUflex signals occupy the same data bus in a time-division multiplexed manner. Based on this data bus, overhead bytes of each fgODUflex signal are processed through time-division multiplexing, thereby saving FPGA system resources.

Description

Technical Field

[0001] The present application relates to the technical field of fine-grained optical transport networks, and in particular to an overhead processing device and method for fine-grained optical transport networks based on FPGA. Background Art

[0002] Fine-grain Optical Transport Network (fgOTN) is a technological evolution of SDH (ITU-T G.707) and OTN (ITU-G.709). It perfectly inherits the high reliability and deterministic latency characteristics of SDH and OTN (Optical Transport Network). It supports a variety of VBR (variable bit rate) and CBR (constant bit rate) services such as Ethernet, E1, and SDH. It can provide a secure hard isolation solution based on rigid hard pipes for high-quality connections. It is widely applicable to operators' government and enterprise dedicated lines, as well as private networks in industries such as power and transportation.

[0003] Fine-grained optical transport networks utilize a fixed time slot allocation design with 10Mb / s bandwidth as the unit, meeting the requirements for highly reliable, deterministic, and time-delayed transmission of small-scale services with minimal resources. Related overhead processing methods suffer from technical issues such as high resource usage, low efficiency, and insufficient processing bandwidth. Increasing bandwidth requires multiple circuit replication, which consumes significant FPGA resources and complicates implementation. Summary of the Invention

[0004] The purpose of this application is to provide a data mapping device for a fine-grained optical transport network based on FPGA, which uses time division multiplexing to insert overhead bytes of fgODUflex signals of multiple channels on a data bus, saving FPGA system resources.

[0005] In a first aspect, the present application provides an FPGA-based fine-grained optical transport network overhead processing device, the device comprising:

[0006] multiple bit width conversion modules, configured to, for each bit width conversion module, convert a first fgODUflex signal having a first bit width into a second fgODUflex signal having a second bit width, and have each second fgODUflex signal occupy the same data bus in a time division multiplexing manner, wherein the first fgODUflex signal and the second fgODUflex signal both carry corresponding channel numbers;

[0007] a framing module, configured to perform the following processing for each clock cycle of the system clock: obtaining a channel number, a second fgODUflex signal, and a frame header indication signal corresponding to the current clock cycle; performing byte counting on the second fgODUflex signal in response to the frame header indication signal, and obtaining a column count value and a row count value corresponding to the channel number in the current clock cycle;

[0008] The multiframe synchronization module is configured to perform the following processing for each clock cycle of the system clock: obtain the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle; when the column count value reaches the maximum column count value and the row count value reaches the maximum row count value, increment the multiframe count value corresponding to the channel number by one to obtain the multiframe count value corresponding to the channel number;

[0009] The overhead processing module is used to perform the following processing for each clock cycle of the system clock: obtain the channel number, the second fgODUflex signal, the column count value, the row count value and the multiframe count value corresponding to the current clock cycle, determine the position of the overhead byte based on the column count value, the row count value and the multiframe count value, and perform overhead byte insertion at the position.

[0010] Optionally, the bit width conversion module is specifically used to:

[0011] A 64-bit first fgODUflex signal is input in each clock cycle, and four 64-bit first fgODUflex signals input in four consecutive clock cycles are combined into a 256-bit second fgODUflex signal. When the 64-bit first fgODUflex signal is input in the first clock cycle, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

[0012] Optionally, the framing module includes a row counter, a column counter, and a first storage unit. The first storage unit uses each channel number as a storage address, and the storage space corresponding to each storage address stores the column count value and row count value corresponding to the channel number, wherein:

[0013] For each channel number, the channel number, frame header indication, and second fgODUflex signal in the current clock cycle are determined. The column counter counts the second fgODUflex signal, adds one to the stored column count value corresponding to the channel number to obtain a column count value, and stores the obtained column count value in the storage space corresponding to the channel number in the first storage unit. In the next clock cycle corresponding to the channel number, the column counter adds one to the last stored column count value, and so on. In response to the column counter reaching 238, the row counter adds one to the stored row count value to obtain a row count value, and stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit. The column counter is reset and counts from zero again, and so on until the row count value reaches 1 and the column count value reaches 238. The column counter and the row counter are reset. In the case of a frame header indication, the column count value and the row count value corresponding to the channel number in the first storage unit are cleared to zero.

[0014] Optionally, the multiframe synchronization module includes a second storage unit. For each channel number, if there is a frame header indication in the current clock cycle, the corresponding channel number and the multiframe count value with bit positions 207~200 in the second fgODUflex signal are obtained, and the obtained multiframe count value is stored in the storage space corresponding to the channel number in the second storage unit. In the clock cycle when the column count value is 238 and the row count value is 1, the stored multiframe count value is increased by one as the updated multiframe count value, and the updated multiframe count value is stored in the storage space corresponding to the channel number in the second storage unit.

[0015] Optionally, the overhead processing module includes a BIP overhead processing unit and a third storage unit, wherein, for each channel number,

[0016] If the column count value of the current clock cycle is the first value and the row count value is 0, or if the column count value of the current clock cycle is the first value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and a 144-bit payload signal in the second fgODUflex signal;

[0017] If the column count value of the current clock cycle is the second value and the row count value is 0, or if the column count value of the current clock cycle is the second value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal;

[0018] The BIP overhead processing unit performs BIP-8 calculation on each acquired 144-bit payload signal and each second fgODUflex signal to obtain a BIP overhead of the current frame, and stores the BIP overhead of the current frame in a storage space corresponding to the channel number in the third storage unit.

[0019] If the column count value of the current clock cycle is 0 and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the BIP overhead of the previous frame corresponding to the channel number into the corresponding bit position of the second fgODUflex signal. The third storage unit stores the BIP overhead of the previous frame, the BIP overhead of the previous frame, and the BIP overhead of the current frame corresponding to each channel number. The first value is one of the following: 0, 59, 119, 179, and the second value is any value between 0 and 238 except the first value.

[0020] Optionally, the overhead processing module includes a BWR overhead processing unit and a fourth storage unit, wherein, for each channel number,

[0021] If the column value in the current clock cycle is 0 and the row value is 0, the BWR overhead processing unit obtains the first 3 bits of data at bit positions 143 to 141 of the corresponding channel number and the second fgODUflex signal, and stores the first 3 bits of data in the storage space corresponding to the channel number in the third storage unit 144;

[0022] If the column value in the current clock cycle is 119 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the second 3-bit data at bit positions 15 to 13 in the second fgODUflex signal, and stores the second 3-bit data in the storage space corresponding to the channel number in the third storage unit 144;

[0023] If the column value in the current clock cycle is 0 and the row value is 1, the BWR overhead processing unit obtains the corresponding channel number and the CRC-3 data with bit positions 143 to 141 in the second fgODUflex signal, performs CRC-3 calculation on the stored first 3-bit data and the second 3-bit data, and verifies the calculated result with the obtained CRC-3 data. If they are consistent, the bandwidth adjustment indication is output.

[0024] Optionally, the overhead processing module includes a reporting overhead processing unit and a fifth storage unit, for each channel number,

[0025] If the column value in the current clock cycle is 0 and the row count value is 0, the report overhead processing unit obtains the channel number corresponding to the clock cycle, outputs an indication signal to the receiving side, and receives the report overhead output from the receiving side. The fifth storage unit stores the report overhead in the storage space corresponding to the channel number, where the report overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead.

[0026] If the column count value and the row count value in the current clock cycle are 0 and 0, or if the column count value and the row count value in the current clock cycle are 0 and 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 163, 159, and 155 of the second fgODUflex signal, respectively.

[0027] If the column count value in the current clock cycle is 119 and the row count value is 0, or if the column count value in the current clock cycle is 119 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 35, 31, and 27 of the second fgODUflex signal, respectively.

[0028] If the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to the channel number into bit positions 167-164, 215-212, and 191-188 of the second fgODUflex signal, respectively.

[0029] Optionally, the pin processing module includes a TTI overhead processing unit and a sixth storage unit. The sixth storage unit uses the channel number, the lowest two bits of the multiframe indication, and the position sequence number as the storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number is used to indicate the position sequence of the TTI overhead in the fgODUflex frame structure. The position sequence number is 00, 01, 10, and 11. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead.

[0030] For each channel number, if the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 00 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95-80, 79-64, and 63-48 of the second fgODUflex signal, respectively.

[0031] If the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 01 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal, respectively.

[0032] If the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 10 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal, respectively.

[0033] If the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 11 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal, respectively.

[0034] Optionally, the overhead processing module includes a STAT overhead processing unit 1 and a seventh storage unit. The seventh storage unit uses the channel number as a storage address. The storage space corresponding to each storage address is used to store the corresponding STAT overhead. The STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead.

[0035] For each channel number, if the column count value in the current clock cycle is 0 and the row count value is 0, or if the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 162-160, 158-156, and 154-152 of the second fgODUflex signal, respectively.

[0036] If the column count value in the current clock cycle is 119 and the row count value is 0, or the column count value in the current clock cycle is 119 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 34-32, 30-28, and 26-24 of the second fgODUflex signal, respectively.

[0037] Optionally, the overhead processing module includes an APS overhead processing unit and an eighth storage unit. The eighth storage unit uses the channel number as the storage address. The storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead.

[0038] For each channel number, if the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM ASP overhead, TCM2ASP overhead, and TCM1 ASP overhead corresponding to the channel number into bit positions 63-48, 95-80, and 79-64 of the second fgODUflex signal, respectively.

[0039] In a second aspect, the present application provides an FPGA-based fine-grained optical transport network overhead processing method, the method comprising:

[0040] Converting a first fgODUflex signal having a first bit width into a second fgODUflex signal having a second bit width, and having each second fgODUflex signal occupy the same data bus in a time division multiplexing manner, wherein both the first fgODUflex signal and the second fgODUflex signal carry a corresponding channel number;

[0041] For each clock cycle of the system clock, the following processing is performed:

[0042] Obtaining a channel number, a second fgODUflex signal, and a frame header indication signal corresponding to a current clock cycle, performing byte counting on the second fgODUflex signal in response to the frame header indication signal, and obtaining a column count value and a row count value corresponding to the channel number in the current clock cycle;

[0043] Obtain the channel number, the second fgODUflex signal, the column count, and the row count corresponding to the current clock cycle. When the column count reaches the maximum column count value and the row count reaches the maximum row count value, increment the multiframe count corresponding to the channel number by one to obtain the multiframe count corresponding to the channel number.

[0044] Obtain the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle, determine the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and perform overhead byte insertion at the position.

[0045] This application uses each bit width conversion module to convert the bit width of the input fgODUflex signal, and each converted fgODUflex signal occupies the same data bus in a time-division multiplexed form. Based on this data bus, the overhead bytes of each fgODUflex signal are processed through time-division multiplexing, which can realize overhead processing of large-bandwidth fgODUflex data. This solution can be flexibly configured, save FPGA system resources, support service flows of any number of entries, and users can arbitrarily configure it according to actual needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A system block diagram of an FPGA-based fine-grained optical transport network overhead processing device provided in an embodiment of the present application;

[0047] Figure 2 Schematic diagram of the fgODUflex standard frame structure provided for the first embodiment of this application;

[0048] Figure 3 A timing diagram of the bit width conversion module provided in an embodiment of the present application;

[0049] Figure 4 This is a timing diagram summarizing the output data of the four bit width conversion modules provided in an embodiment of the present application;

[0050] Figure 5 A schematic diagram of the structure of the framing module provided in an embodiment of the present application;

[0051] Figure 6 A timing diagram of row and column counting of a single data stream provided in an embodiment of the present application;

[0052] Figure 7 A timing diagram of row and column counting of multiple data streams provided in an embodiment of the present application;

[0053] Figure 8 A schematic diagram of the structure of the multiframe synchronization module provided in an embodiment of the present application;

[0054] Figure 9 A multiframe counting timing diagram provided in an embodiment of the present application;

[0055] Figure 10 A schematic diagram of the structure of the overhead processing module provided in an embodiment of the present application;

[0056] Figure 11 A timing diagram of BIP overhead processing provided in an embodiment of the present application;

[0057] Figure 12 A flowchart of a method for processing overhead in a fine-grained optical transport network based on FPGA provided in an embodiment of the present application;

[0058] Figure 13 A system block diagram of the communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The present application will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in this field based on these embodiments are included in the scope of protection of the present application.

[0060] like Figure 1As shown, a data mapping device for a fine-grained optical transport network based on an FPGA, provided in one embodiment of the present application, includes multiple bit-width conversion modules 11, a framing module 12, a multiframe synchronization module 13, and an overhead processing module 14. For each bit-width conversion module 11, a first fgODUflex (Fine Grain Optical Data Unit Flex) signal having a first bit-width is converted into a second fgODUflex signal having a second bit-width. Each second fgODUflex signal occupies the same data bus in a time-division multiplexed manner, wherein both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers. For each clock cycle of the system clock, the framing module 12 performs the following processing: obtains the channel number corresponding to the current clock cycle, the second fgODUflex signal, and a frame header indication signal; performs byte count on the second fgODUflex signal in response to the frame header indication signal, and obtains the column count value and row count value corresponding to the channel number in the current clock cycle. The multiframe synchronization module 13 performs the following processing for each clock cycle of the system clock: obtains the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle; when the column count value reaches the maximum column count value and the row count value reaches the maximum row count value, increments the multiframe count value corresponding to the channel number by one to obtain the multiframe count value corresponding to the channel number. The overhead processing module 14 performs the following processing for each clock cycle of the system clock: obtains the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle; determines the position of the overhead bytes based on the column count value, the row count value, and the multiframe count value; and inserts the overhead bytes at this position. The overhead bytes include BIP (Bit Interleaved Parity) overhead, BWR (Bandwidth Resizing) overhead, Backward Defect Indication (BDI) overhead, Backward Error Indication (BEI) overhead, Backward Input Alignment Error (BIAE) overhead, TTI (Trail Trace Identifier) overhead, STAT (Path Status) overhead, and APS (Automatic Protection Switching) overhead.

[0061] In this embodiment, each bit width conversion module 11 performs bit width conversion on the input fgODUflex signal, and each converted fgODUflex signal occupies the same data bus in a time-division multiplexed form. Based on this data bus, the overhead bytes of each fgODUflex signal are processed through time-division multiplexing, which can realize overhead processing of large-bandwidth fgODUflex data. This solution can be flexibly configured, can save FPGA system resources, can support service flows of any number of entries, and users can make any configuration according to actual needs.

[0062] like Figure 2 In the fgODUflex standard frame structure shown, bytes 1-16 are the overhead byte area, bytes 17-1904 are the payload area, bytes 1905-1920 are the overhead byte area, and bytes 1921-3824 are the payload area. Therefore, overhead byte insertion is implemented based on the byte position of each overhead byte. The fgODUflex frame alignment signal consists of 8 bytes of FAS, labeled FAS0 through FAS1, located in byte columns 1 to 4 and columns 1905 to 1908, respectively.

[0063] In one embodiment of the present application, the first bit width is set to 64 bits and the second bit width is set to 256 bits. For each bit width conversion module 11, a 64-bit first fgODUflex signal is input in each clock cycle, and a 256-bit second fgODUflex signal composed of the 64-bit first fgODUflex signal input in four consecutive clock cycles is output. When the 64-bit first fgODUflex signal is input in the first clock cycle, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

[0064] Exemplarily, the first fgODUflex signal can be understood as the payload area in the frame structure being filled with data, the overhead area being 0, and the overhead bytes being filled based on the solution of the present application.

[0065] The protocol stipulates that the frame length of the fgODUflex signal is 4*3824 bytes, which can be exactly divided into 478 256-bit data blocks. Therefore, the bit width conversion module 11 performs preliminary processing on the input first fgODUflex signal and expands the input data stream from a 64-bit data stream to a 256-bit data stream.

[0066] For example, Figure 3The timing diagram of the bit width conversion module 11 is shown. The input data of the bit width conversion module 11 is the 64-bit first fgODUflex signal, and the first 64-bit first fgODUflex signal inputted first is the high 64 bits of the 256-bit second fgODUflex signal. As shown in the figure, the first 64-bit first fgODUflex signal inputted in the first clock cycle is a, which corresponds to bits [255:192] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is 000a; the second 64-bit first fgODUflex signal inputted in the second clock cycle is b, which corresponds to bits [191:128] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is 00ab; the third 64-bit first fgODUflex signal input in the third clock cycle is c, which corresponds to bits [127:64] of the 256-bit second fgODUflex signal. The second fgODUflex signal in this clock cycle is 0abc; the fourth 64-bit first fgODUflex signal input in the fourth clock cycle is d, which corresponds to bits [63:0] of the 256-bit second fgODUflex signal. The second fgODUflex signal in this clock cycle is abcd. A 64-bit first fgODUflex signal is input in each clock cycle. The first fgODUflex signal is input for four consecutive clock beats. The output data signal remains unchanged for four clock beats and is stored as a 256-bit second fgODUflex signal. The second fgODUflex signal is output once every four clock beats, and the data is updated every four clock beats.

[0067] Exemplarily, the input data of the bit width conversion module 11 also includes the channel number corresponding to the first fgODUflex signal, such as Figure 3 The channel number shown is 0, indicating that the channel number of the first fgODUflex signal input to the bit width conversion module 11 is 0, and the bit width conversion module 11 processes the fgODUflex signal with channel number 0. It is understood that the channel number of the first fgODUflex signal processed by the bit width conversion module 11 can be different each time. The first fgODUflex signals input to the bit width conversion module 11 within four clock cycles generally have the same channel number. The channel numbers of the first fgODUflex signals processed by each bit width conversion module 11 can be the same or different.

[0068] For example, when the 64-bit first fgODUflex signal is input in the first clock cycle, it is necessary to determine whether the 64-bit first fgODUflex signal is a frame header through the externally input frame header indication. If there is a frame header indication, the frame header indication is temporarily stored, and after all the first fgODUflex signals of the 4-beat clock are received, the frame header indication and the 256-bit second fgODUflex signal are output together. The frame header indication may generally be input together with the first 64-bit first fgODUflex signal input by the bit width conversion module 11, but not every first 64-bit first fgODUflex signal will be input together, so when the 256-bit second fgODUflex signal is output, it is not necessarily output together with the frame header indication. Figure 3 As shown, the high level of the frame header indication indicates that the corresponding first fgODUflex signal is a frame header, which is subsequently output together with the first fgODUflex signal.

[0069] For example, four bit width conversion modules 11 can be supported, each of which supports 10G bandwidth, and can support a total of 40G bandwidth, and can support any number of service flows. Figure 4 As shown in the timing diagram summarizing the output data of the four bit width conversion modules, the channel number 0 of the first bit width conversion module 11 corresponds to p0, and the output of the second fgODUflex signal 0 corresponds to a; the channel number 1 of the second bit width conversion module 11 corresponds to p1, and the output of the second fgODUflex signal 1 corresponds to b; the channel number 2 of the third bit width conversion module 11 corresponds to p2, and the output of the second fgODUflex signal 2 corresponds to c; the channel number 3 of the fourth bit width conversion module 11 corresponds to p3, and the output of the second fgODUflex signal 3 corresponds to d. The channel numbers of the four bit width conversion modules 11 occupy the same data bus in a time division multiplexing form, as shown in FIG. Figure 4 The output channel numbers shown are p0, p1, p2, and p3, and the second fgODUflex signals of the four bit width conversion modules 11 occupy the same data bus in a time division multiplexing form, such as Figure 4 The output second fgODUflex signals shown are a, b, c, and d.

[0070] For example, the second fgODUflex signal output by each bit width conversion module 11 is valid for four beats, so the signals output by the four bit width conversion modules 11 occupy the same data bus, so it is only necessary to take the data output by one bit width conversion module 11 in turn in each beat, such as Figure 4As shown, the data output by each bit width conversion module 11 is selected by using the clock beat counting signal. The clock beat counting signal counts to four beats in total. When the clock beat counting signal is 0 (i.e., the first beat clock), the second fgODUflex signal output by the first bit width conversion module 11 is selected. Since the second fgODUflex signal output by the first bit width conversion module 11 is valid for four beats, the second fgODUflex signal of the first beat clock is selected, and the second fgODUflex signals of the remaining 2nd to 4th beat clocks of the first bit width conversion module 11 are treated as invalid data. Similarly, When the clock beat count signal is 1 (i.e., the second clock beat), the second fgODUflex signal output by the second bit width conversion module 11 is selected. Since the second fgODUflex signals output by the second bit width conversion module 11 are all valid for four beats, the second fgODUflex signal of the second clock beat is selected. The second fgODUflex signals of the first, third, and fourth beats of the second bit width conversion module 11 are treated as invalid data. Similarly, the second fgODUflex signals output by the four bit width conversion modules 11 are integrated into a data bus to ensure that no data is discarded.

[0071] like Figure 2 The fgODUflex standard frame structure shown has four rows, each with 3824 columns. Based on the above description, the bit width conversion module 11 outputs 256-bit data. (4*3824*8 / 256 = 2*239.) Therefore, for ease of processing, the 4*3824 columns of data are converted into data blocks consisting of two rows and 239 columns, each containing 256 bits. Row and column counts are performed on the second fgODUflex signal output by the bit width conversion module 11. The resulting row and column counts are then used to determine the byte positions of the overhead bytes, thereby enabling overhead byte insertion.

[0072] One embodiment of the present application, such as Figure 5As shown, the framing module 12 includes a row counter 121, a column counter 122, and a first storage unit 123. The first storage unit 123 uses each channel number as a storage address. The storage space corresponding to each storage address stores the column count value and row count value corresponding to the channel number. The column counter 121 and the row counter 122 use a time division multiplexing method to perform column counting and row counting on the second fgODUflex signal of each channel number. The time division multiplexing method includes: for each channel number, determining the channel number, frame header indication, and second fgODUflex signal in the current clock cycle, the column counter 121 counts the second fgODUflex signal, performs an addition operation on the stored column count value to obtain a column count value, and converts the obtained column count value into a column count value. The data is stored in the storage space corresponding to the channel number in the first storage unit 123, and in the next clock cycle corresponding to the channel number, the column counter 121 accumulates the count on the column count value stored last time, and so on. In response to the column counter 121 reaching 238, the row counter 122 performs a plus-one operation on the basis of the stored row count value to obtain a row count value, and stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit 123, the column counter 121 is reset and counts from zero, and so on, until the row count value is 1 and the column count value reaches 238, the column counter 121 and the row counter 122 are reset, wherein, in the case of a frame header indication, the column count value and the row count value corresponding to the channel number in the first storage unit 123 are cleared.

[0073] In this embodiment, if a frame header indication is received, indicating that the second fgODUflex signal is frame header data, the row count value and column count value last stored in the first storage unit 123 are cleared, and the signal is counted again. If no frame header indication is received, counting is performed based on the row count value and column count value last stored in the first storage unit 123. This can prevent data from being in an erroneous state after an anomaly occurs. For example, in the event of an anomaly such as a lost data block or an erroneous frame header indication, the row and column count values in the first storage unit 123 may be inconsistent with the count values of the actual data stream. Therefore, the error correction mechanism of clearing the frame header indication can ensure that the stored row and column count values match the actual data stream. Moreover, since the signal is continuously transmitted, even if an error occurs in the initial stage, the signal can be immediately re-matched.

[0074] For example, Figure 6The timing diagram of row and column counting shown in FIG. This diagram illustrates the timing diagram of row and column counting for a single data stream. As can be seen from the diagram, the channel number corresponding to the current clock cycle is 0, and the second fgODUflex signal of channel number 0 is counted. The frame header indicator is high, indicating that the second fgODUflex signal is frame header data. Column counter 121 and row counter 122 restart counting and count the second fgODUflex signal (a). Column counter 121 begins counting and obtains a column count value of 0 (in this embodiment, the count value ranges from 0 to 238). Row counter 122 obtains a row count value of 0. The column count value 0 and the row count value 0 are stored in the storage space corresponding to the storage address of channel number 0 in the first storage unit 123. That is, the storage address is 0, the column count value written is 0, and the row count value written is 0. In the next clock cycle corresponding to channel number 0, the second fgODUflex signal (b) is counted. The column counter 121 adds 1 to the last stored column count value 0 to obtain a column count value 1, and the row count value is 0. Similarly, the column count value 1 and the row count value 0 are written to the storage space corresponding to storage address 0. Similarly, when the column count value of the column counter 121 reaches 238, the row counter 122 adds 1 to the row count value 0 to obtain a row count value 1. The column counter 121 is cleared and starts counting from 0. The row count value and the column count value are updated in storage address 0 at the same time. When the row count value is 1 and the column count value reaches 238, the counting of a complete fgODUflex frame structure is completed, the column counter 121 and the row counter 122 are reset, and the above embodiment is repeated.

[0075] For example, Figure 7 The timing diagram of row and column counting shown in the figure shows a schematic diagram of the timing of row and column counting for multiple data streams. As can be seen from the figure, in the first clock cycle, row and column counting are performed on the second fgODUflex signal (a) with channel number 0, and the resulting row count value 0 and column count value 0 are stored in the storage space with storage address 0 in the first storage unit 123. In the second clock cycle, row and column counting are performed on the second fgODUflex signal (b) with channel number 1, and the resulting row count value 0 and column count value 0 are stored in the storage space with storage address 1 in the first storage unit 123. And so on. In each clock cycle, row and column counting is performed on the second fgODUflex signal with the corresponding channel number, thus implementing a time division multiplexing technical solution without duplicating the counting circuit for each channel number, saving FPGA system resources.

[0076] The fgODUflex standard frame structure shows that the 1-byte multiframe indicator (MFAS) is located in row 1, column 7. The MFAS increments based on the fgODUflex frame and ranges from 0 to 255, indicating a 256-bit multiframe. The MFAS is located in the 7th byte of the frame header. Based on the description of the bit width conversion module 11 in the above embodiment, bytes 1-8 of the fgODUflex signal are transmitted first. Therefore, the MFAS is located in bits 207-200 of the 256-bit second fgODUflex signal. When the frame header indicator appears, the MFAS values for bits 207-200 of the second fgODUflex signal are obtained and written to memory. Multiframe counting is performed based on this MFAS value to ensure self-correction in the event of anomalies that cause multiframe counting errors. Because the processing of each overhead byte is related to the multiframe comparison, the multiframe count value obtained after each count is updated and stored to facilitate subsequent overhead byte processing.

[0077] One embodiment of the present application, such as Figure 8 As shown, the multiframe synchronization module 13 includes a second storage unit 132. The second storage unit 132 uses each channel number as a storage address. For each channel number, if there is a frame header indication in the current clock cycle, the second storage unit 132 obtains the corresponding channel number and the multiframe count value with bit positions 207 to 200 in the second fgODUflex signal. The obtained multiframe count value is stored in the storage space corresponding to the channel number in the second storage unit 132. In a clock cycle when the column count value is 238 and the row count value is 1, the stored multiframe count value is incremented by one as an updated multiframe count value, and the updated multiframe count value is stored in the storage space corresponding to the channel number in the second storage unit 132.

[0078] For example, Figure 9 In the multiframe counting timing diagram shown in FIG. 1 , the channel number corresponding to the current clock cycle is 0. The multiframe count value ax for bit positions 207 to 200 in the second fgODUflex signal is obtained, and ax is written to the storage address 0 corresponding to the channel number 0. When the column count value is 238 and the row count value is 1, the obtained multiframe count value ax is incremented by one as the updated multiframe count value ax+1, and ax+1 is written to the storage address 0 corresponding to the channel number 0.

[0079] As can be seen from the fgODUflex standard frame structure, fgODUflex overhead information is used for maintenance and operation functions to support fgODUflex connections. The fgODUflex overhead includes path monitoring (PM) and tandem connection monitoring (TCM1) and TCM2. The fgODUflex path monitoring overhead is generated and terminated at the source and sink of the fgODUflex path, respectively. The fgODUflex tandem connection monitoring overhead is generated and terminated at the source and sink of the corresponding tandem connection, respectively. The PM, TCM1, and TCM2 overhead fields include the following: Path Trace Identifier (TTI), Bit Parity Check (BIP-8), Backward Defect Indication (BDI), Backward Error Indication (BEI), Backward Input Alignment Error (BIAE), Status Indication (STAT) for maintenance signals, Delay Measurement (DM), and Automatic Protection Switching (APS). The fgODUflex overhead defines the bit interleaved parity (BIP). For PM (path monitoring), the BIP is located in the 11th byte column of the third row; for TCM1 (tandem connection monitoring), the BIP is located in the 8th byte column of the third row; and for TCM2 (tandem connection monitoring), the BIP is located in the 5th byte column of the third row.

[0080] The protocol specifies that BIP calculation is based on byte columns 15-1904 and byte columns 1919-3824 of the fgODUflex area of each frame. The BIP calculation result is generated in the i-2th frame and inserted into the overhead position of the BIP in the fgODUflex of the i-th frame. Therefore, it is necessary to store the BIP of the i-2th frame, the BIP of the i-1th frame, and the BIP of the i-th frame. When the BIP overhead of the current frame (i.e., the i-th frame) is inserted, the stored BIP of the i-2th frame is inserted into the corresponding overhead byte position.

[0081] As can be seen from the above embodiment, the received second fgODUflex signal is a 256-bit signal. The 256-bit signal may be entirely payload or may be a combination of overhead and payload. Therefore, when calculating the BIP, the complete second fgODUflex signal is calculated for the second fgODUflex signal that is entirely payload, and the 128-bit payload of the second fgODUflex signal that includes overhead needs to be calculated. Based on the position of each overhead byte in the fgODUflex standard frame structure and the bit position distribution of 256 bits, the column count value corresponding to each overhead byte can be determined, thereby realizing the BIP calculation. That is, when the column count value is 0, 59, 119, or 179, the corresponding second fgODUflex signal contains an overhead area. For the remaining column count values, the corresponding second fgODUflex signal is entirely payload data.

[0082] One embodiment of the present application, such as Figure 10As shown, the overhead processing module 14 includes a BIP overhead processing unit 141 and a third storage unit 142. For each channel number, if the column count value of the current clock cycle is the first value and the row count value is 0, or the column count value is the first value and the row count value is 1, the channel number corresponding to the clock cycle and the 144-bit payload signal in the second fgODUflex signal are obtained. If the column count value of the current clock cycle is the second value and the row count value is 0, or the column count value is the second value and the row count value is 1, the channel number corresponding to the clock cycle and the second fgODUflex signal are obtained, and the BIP-8 calculation is performed on each of the obtained 144-bit payload signals and each of the second fgODUflex signals to obtain the BIP overhead of the current frame. The BIP overhead of the frame is stored in the storage space corresponding to the channel number in the third storage unit 142. If the column count value of the current clock cycle is 0 and the row count value is 1, the channel number corresponding to the clock cycle and the second fgODUflex signal are obtained, and the BIP overhead of the previous frame corresponding to the channel number is inserted into the corresponding bit position in the second fgODUflex signal. The third storage unit 142 stores the BIP overhead of the previous frame, the previous frame, and the current frame corresponding to each channel number. The first value is one of the following: 0, 59, 119, or 179, and the second value is any value between 0 and 238 except the first value. The position of the BIP overhead byte is determined based on the column count value. If the first value is 0 or 179, the lower 144 bits of the second fgODUflex signal are obtained as the 144-bit payload signal. If the first value is 59 or 119, the upper 128 bits and lower 16 bits of the second fgODUflex signal are obtained as the 144-bit payload signal. It should be noted that, as can be seen from the above, the calculation of BIP is based on the 15th to 1904th byte columns and the 1919th to 3824th byte columns of the fgoduflex area of each frame. It can be seen from the structure of the fgoduflex frame that the 144-bit payload signal described in this embodiment refers to a 16-bit mapping signal including the 15th to 16th bytes in the frame structure and a 128-bit (17th to 24th byte) pure payload signal, or a 16-bit mapping signal including the 1919th to 1920th bytes in the frame structure and a 128-bit (1921st to 1928th byte) pure payload signal.

[0083] For example, Figure 11In the timing diagram of BIP overhead processing shown in FIG. 1 , the channel number (rx_tpid) corresponding to the current clock cycle is 0. The calculated BIP8 value of the i-th frame is written to the storage space at storage address 0 of the third storage unit 142. The previously calculated BIP8 values of the i-1th frame and the i-2th frame have already been stored in the storage space at storage address 0 of the third storage unit 142. Storage address 0 correspondingly stores the BIP8 values of the i-2th frame, the i-1st frame, and the i-th frame. When BIP overhead processing is performed on the fgoduflex signal of the current frame (the i-th frame), the calculated BIP8 value of the i-2th frame is inserted into the corresponding bit position of the corresponding second fgoduflex signal.

[0084] When packet services are mapped into fgODUflex frames, the mapping overhead area contains BWR overhead for lossless bandwidth adjustment. As shown in the standard fgODUflex frame structure, the BWR overhead is located in columns 15 of rows 1 to 3 and consists of 9 bits: BWR_IND (1 bit), NCS (1 bit), and CRC-3 (3 bits). BWR_IND is the lossless bandwidth adjustment indicator and is located in the first bit of row 1 and the first bit of row 2. The 3-bit CRC is used for error correction on bits 1 to 3 of rows 1 and 2 of the fgODUflex frame. When bits 1 to 3 of row 1 and bits 1 to 3 of row 2 are received, these 6 bits are stored and a CRC-3 calculation is performed on these 6 bits. The result is then checked against the CRC-3 data of row 3. If the checksum matches, the BWR_IND indicator is valid and the BWR_IND is retrieved for lossless bandwidth adjustment of the fgODUflex signal.

[0085] One embodiment of the present application, such as Figure 11As shown, the overhead processing module 14 includes a BWR overhead processing unit 143 and a fourth storage unit 144. The BWR processing unit 143 is configured to: for each channel number, if the column value in the current clock cycle is 0 and the row value is 0, obtain the corresponding channel number and the first 3-bit data with bit positions 143 to 141 in the second fgODUflex signal, and store the first 3-bit data in the storage space corresponding to the channel number in the third storage unit 144; if the column value in the current clock cycle is 119 and the row value is 0, obtain the corresponding channel number and the second fgO The second 3-bit data at bit positions 15 to 13 in the DUflex signal is stored in the storage space corresponding to the channel number in the third storage unit 144. If the column value in the current clock cycle is 0 and the row value is 1, the CRC-3 data at bit positions 143 to 141 of the corresponding channel number and the second fgODUflex signal is obtained. A CRC-3 calculation is performed on the stored first 3-bit data and the second 3-bit data. The calculated result is checked against the obtained CRC-3 data. If they are consistent, a bandwidth adjustment indication is output.

[0086] The Backward Defect Indication (BDI) overhead in the fgODUflex frame structure is used to transmit a signal fault status indication to the source end when a signal fault is detected at the sink end of a path or tandem connection. Setting BDI to "1" indicates fgODUflex Backward Defect Indication; otherwise, it is set to "0." For PM, the BDI is located in bit 5 of the 12th byte column of each row; for TCM1, the BDI overhead is located in bit 5 of the 13th byte column of each row; and for TCM2, the BDI overhead is located in bit 1 of the 13th byte column of each row. For PM, a 4-bit BEI (Backward Error Indication) overhead is defined in bits 1-4 of the 12th byte column of the 3rd row. For TCM1 and TCM2, a 4-bit BEI / BIAE (Backward Error Indication and Backward Input Alignment Error) overhead is defined for each TCM level, located in bits 1-4 of the 9th byte column of the 3rd row and bits 1-4 of the 6th byte column of the 3rd row, respectively.

[0087] One embodiment of the present application, such as Figure 10As shown, the overhead processing module 14 includes a return overhead processing unit 145 and a fifth storage unit 146. For each channel number, if the column value in the current clock cycle is 0 and the row count value is 0, the return overhead processing unit 145 obtains the channel number corresponding to the clock cycle, outputs an indication signal to the receiving side, and receives the return overhead output from the receiving side. The fifth storage unit 146 stores the return overhead in the storage space corresponding to the channel number. The return overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead. If the column count value in the current clock cycle is 0 and the row count value is 0, the channel number corresponding to the clock cycle and the second fgODUflex signal are obtained, and the PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead corresponding to the channel number are stored in the storage space corresponding to the channel number. The BDI overhead is respectively inserted into bit positions 163, 159 and 155 of the second fgODUflex signal; if the column count value in the current clock cycle is 119 and the row count value is 0, the channel number and the second fgODUflex signal corresponding to the clock cycle are obtained, and the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number are respectively inserted into bit positions 35, 31, and 27 of the second fgODUflex signal; if the column count value in the current clock cycle is 0 and the row count value is 1, the channel number and the second fgODUflex signal corresponding to the clock cycle are obtained, and the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number are respectively inserted into bit positions 163, 159, and 155 of the second fgODUflex signal; if the column count value in the current clock cycle is 119 and the row count value is 1, the channel number and the second fgODUflex signal corresponding to the clock cycle are obtained, and the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number are respectively inserted into bit positions 163, 159, and 155 of the second fgODUflex signal. The BDI overhead is inserted into bit positions 35, 31, and 27 of the second fgODUflex signal. If the column count value in the current clock cycle is 0 and the row count value is 1, the channel number corresponding to the clock cycle and the second fgODUflex signal are obtained, and the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to the channel number are inserted into bit positions 167-164, 215-212, and 191-188 of the second fgODUflex signal, respectively. The mapping of the BDI, BEI, and BIAE overheads is dependent on the receiving side. When processing these overhead bytes, the transmitting side outputs an indication signal to notify the receiving side of the need to map these overhead bytes. Upon receiving this indication signal, the receiving side transmits the relevant overhead bytes to the transmitting side, enabling the transmitting side to perform overhead byte processing.

[0088] Overhead in fgODUflex also includes configuration overhead, which is configured by external interfaces. Examples include TTI (Path Trace Identifier) overhead, STAT (Status Indicator for Maintenance Signal) overhead, and APS (Automatic Protection Switching) overhead. For PM, the TTI overhead is defined in the 8-byte TTI field in byte columns 1909-1910 of rows 1-4; for TCM1, the 8-byte TTI field is defined in byte columns 1913-1914 of rows 1-4; and for TCM2, the 8-byte TTI field is defined in byte columns 1911-1912 of rows 1-4. The complete 32-byte Path Trace Identifier information for PM, TCM1, or TCM2 is transmitted every four frames, indicated by MFAS [7, 8].

[0089] One embodiment of the present application, such as Figure 10As shown, the overhead processing module 14 includes a TTI overhead processing unit 147 and a sixth storage unit 148. The sixth storage unit 148 is used to store the configured TTI overhead. The sixth storage unit 148 uses the channel number + the least significant two bits of the multiframe indicator + the position sequence number as the storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number indicates the position sequence of the TTI overhead in the fgODUflex frame structure, and the position sequence numbers are 00, 01, 10, and 11. For each channel number, if the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, uses the channel number + the lowest two bits of the multiframe indicator + 00 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal, respectively; if the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, uses the channel number + the lowest two bits of the multiframe indicator + 01 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal, respectively. The TTI overhead is respectively inserted into bit positions 223-208, 207-192, and 191-176 of the second fgODUflex signal; if the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, uses the channel number + the two lowest bits of the multiframe indicator + 10 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95-80, 79-64, and 63-48 of the second fgODUflex signal; if the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, uses the channel number + the two lowest bits of the multiframe indicator + 11 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95-80, 79-64, and 63-48 of the second fgODUflex signal. The TTI overhead is inserted into bit positions 223-208, 207-192, and 191-176 of the second fgODUflex signal. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead. This implements the insertion of TTI overhead bytes.

[0090] The STAT (maintenance signal status indication) overhead defines a 3-bit status overhead (PM STAT) for PM, located in bits 6-8 of the 12th byte column of each row, for maintenance signal indication. Similarly, a 3-bit status overhead (TCM1 STAT and TSM2 STAT) is defined for each TCM. TCM1 STAT is located in bits 6-8 of the 13th byte column of each row. TCM2 STAT is located in bits 2-4 of the 13th byte column of each row.

[0091] One embodiment of the present application, such as Figure 10 As shown, the overhead processing module 14 includes a STAT overhead processing unit 149 and a seventh storage unit 14A. The seventh storage unit 14A is used to store the configured STAT overhead. The seventh storage unit 14A uses channel numbers as storage addresses, and the storage space corresponding to each storage address is used to store the corresponding STAT overhead. STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead. For each channel number, if the column count value in the current clock cycle is 0 and the row count value is 0, the STAT overhead processing unit 149 obtains the channel number and the second fgODUflex signal corresponding to the clock cycle, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 162-160, 158-156, and 154-152 of the second fgODUflex signal, respectively. If the column count value in the current clock cycle is 119 and the row count value is 0, the channel number and the second fgODUflex signal corresponding to the clock cycle are obtained, and the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number are inserted into bit positions 34-32, 30-28, and 26-24 of the second fgODUflex signal, respectively. If the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit 149 obtains the channel number and the second fgODUflex signal corresponding to the clock cycle, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 34-32, 30-28, and 26-24 of the second fgODUflex signal, respectively. The STAT overhead is respectively inserted into bit positions 162-160, 158-156, and 154-152 of the second fgODUflex signal. If the column count value in the current clock cycle is 119 and the row count value is 1, the channel number corresponding to the clock cycle and the second fgODUflex signal are obtained, and the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number are respectively inserted into bit positions 34-32, 30-28, and 26-24 of the second fgODUflex signal to implement STAT overhead insertion.

[0092] In the fgODUflex frame structure, the 2-byte PM APS (Automatic Protection Switching) overhead field is defined in the 9th-10th byte columns of the 4th row; the 2-byte TCM1 APS overhead field is defined in the 7th-8th byte columns of the 4th row; and the 2-byte TCM2 APS overhead field is defined in the 5th-6th byte columns of the 4th row.

[0093] One embodiment of the present application, such as Figure 10 As shown, the overhead processing module 14 includes an APS overhead processing unit 14B and an eighth storage unit 14C. The eighth storage unit 14C is used to store the configured APS overhead. The eighth storage unit 14C uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead. For each channel number, if the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit 14B obtains the channel number and the second fgODUflex signal corresponding to the clock cycle, and inserts the PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead corresponding to the channel number into bit positions 63-48, 95-80, and 79-64 of the second fgODUflex signal, respectively, to implement the insertion of the APS overhead byte.

[0094] Based on the same inventive concept, an embodiment of the present application also provides an overhead processing method for a fine-grained optical transport network based on FPGA. The implementation solution for solving the problem provided by this method is similar to the implementation solution recorded in the above-mentioned device. Therefore, the specific limitations of one or more embodiments of the overhead processing method for a fine-grained optical transport network based on FPGA provided below can be found in the above limitations on the overhead processing device for a fine-grained optical transport network based on FPGA, and will not be repeated here.

[0095] Please refer to Figure 12 The present application provides an overhead processing method for a fine-grained optical transport network based on an FPGA, the method comprising:

[0096] S1201: Convert a first fgODUflex signal having a first bit width into a second fgODUflex signal having a second bit width, and have each of the second fgODUflex signals occupy the same data bus in a time division multiplexing manner, wherein both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers.

[0097] S1202: For each clock cycle of the system clock, perform the following processing: obtain the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle; perform byte counting on the second fgODUflex signal in response to the frame header indication signal to obtain a column count value and a row count value corresponding to the channel number in the current clock cycle;

[0098] S1203: Obtain a channel number, a second fgODUflex signal, a column count value, and a row count value corresponding to the current clock cycle. When the column count value reaches a column count maximum value and the row count value reaches a row count maximum value, increment the multiframe count value corresponding to the channel number by one to obtain a multiframe count value corresponding to the channel number.

[0099] S1204: Obtain the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle, determine the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and perform overhead byte insertion at the position.

[0100] As an example, see Figure 13, which shows a schematic structural diagram of a communication device provided in an embodiment of the present application. The network device includes an FPGA-based fine-grained optical transport network overhead processing device 1301, a communication interface 1302, a processor 1303, a memory 1304, and a bus 1305. The processor 1303, the memory 1304, the communication interface 1302, and the FPGA-based fine-grained optical transport network overhead processing device 1301 are communicatively connected to each other via the bus 1305. The memory 1304 can be used to store computer programs, which may include instructions and data. In the embodiment of the present application, the memory 1304 can be various types of storage media, such as random access memory, static random access memory, non-volatile RAM, DDR, etc. The memory 1304 can include a hard disk and / or internal memory. The processor 1303 can be a general-purpose processor, which can be a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 1304). The general-purpose processor is used to process data output by the FPGA-based fine-grained optical transport network overhead processing device 1301. A general-purpose processor may be, for example, but not limited to, a central processing unit. In addition, the processor 1303 may also be a dedicated processor. A dedicated processor may be a processor specially designed to perform specific steps and / or operations. A dedicated processor may be, for example, but not limited to, an ASIC and an FPGA. In addition, the processor 1303 may also be a combination of multiple processors, such as a multi-core processor. The communication interface 1302 may include input / output interfaces, physical interfaces, and logical interfaces for interconnecting devices within a network device, as well as interfaces for interconnecting a network device with other devices (such as a network device). The physical interface may be a Gigabit Ethernet interface, which may be used to interconnect a network device with other devices, and the logical interface is an interface within a network device, which may be used to interconnect devices within a network device. The bus 1305 may be any type of communication bus, such as a system bus, for interconnecting the processor 1303, the memory 1304, the communication interface 1302, and the overhead processing device 1301 of the FPGA-based fine-grained optical transport network. The structure of the overhead processing device 1301 of the FPGA-based fine-grained optical transport network can refer to Figure 1 The embodiment shown in FIG. 1 is not described in detail here. The interconnection between any one of the processor 1303, the memory 1304, and the communication interface 1302 and the FPGA-based fine-grained optical transport network overhead processing device 1301 may specifically refer to the interconnection between any one of the devices and a device in the FPGA-based fine-grained optical transport network overhead processing device 1301.

[0101] The embodiments disclosed in the present application also provide a computer-readable storage medium having instructions stored therein. When the computer-readable storage medium is executed on a computer, the computer is enabled to execute the FPGA-based fine-grained optical transport network overhead processing method described in any of the above embodiments.

[0102] Although the preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application as disclosed in the accompanying claims.

Claims

1. An FPGA-based fine-grained optical transport network overhead processing device, characterized in that: The device comprises: multiple bit width conversion modules, configured to, for each bit width conversion module, convert a first fgODUflex signal having a first bit width into a second fgODUflex signal having a second bit width, and have each second fgODUflex signal occupy the same data bus in a time division multiplexing manner, wherein the first fgODUflex signal and the second fgODUflex signal both carry corresponding channel numbers; a framing module, configured to perform the following processing for each clock cycle of the system clock: obtaining a channel number, a second fgODUflex signal, and a frame header indication signal corresponding to the current clock cycle; performing byte counting on the second fgODUflex signal in response to the frame header indication signal, and obtaining a column count value and a row count value corresponding to the channel number in the current clock cycle; a multiframe synchronization module, configured to perform the following processing for each clock cycle of the system clock: obtaining a channel number, a second fgODUflex signal, a column count value, and a row count value corresponding to the current clock cycle; when the column count value reaches a column count maximum value and the row count value reaches a row count maximum value, incrementing the multiframe count value corresponding to the channel number by one to obtain a multiframe count value corresponding to the channel number; an overhead processing module, configured to perform the following processing for each clock cycle of the system clock: obtaining a channel number, a second fgODUflex signal, a column count value, a row count value, and a multiframe count value corresponding to the current clock cycle, determining a position of an overhead byte based on the column count value, the row count value, and the multiframe count value, and performing overhead byte insertion at the position; The bit width conversion module is specifically used for: A 64-bit first fgODUflex signal is input in each clock cycle, and four 64-bit first fgODUflex signals input in four consecutive clock cycles are combined into a 256-bit second fgODUflex signal. When the 64-bit first fgODUflex signal is input in the first clock cycle, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

2. The device according to claim 1, characterized in that The framing module includes a row counter, a column counter and a first storage unit. The first storage unit uses each channel number as a storage address. The storage space corresponding to each storage address stores the column count value and row count value corresponding to each channel number. For each channel number, the channel number, frame header indication, and second fgODUflex signal in the current clock cycle are determined. The column counter counts the second fgODUflex signal, adds one to the stored column count value corresponding to the channel number to obtain a column count value, and stores the obtained column count value in the storage space corresponding to the channel number in the first storage unit. In the next clock cycle corresponding to the channel number, the column counter adds one to the last stored column count value, and so on. In response to the column counter reaching 238, the row counter adds one to the stored row count value to obtain a row count value, and stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit. The column counter is reset and counts from zero again, and so on until the row count value reaches 1 and the column count value reaches 238. The column counter and the row counter are reset. In the case of a frame header indication, the column count value and the row count value corresponding to the channel number in the first storage unit are cleared to zero.

3. The device according to claim 1, wherein The multiframe synchronization module includes a second storage unit. For each channel number, if there is a frame header indication in the current clock cycle, the module obtains the corresponding channel number and the multiframe count value with bit positions 207 to 200 in the second fgODUflex signal, stores the obtained multiframe count value in the storage space corresponding to the channel number in the second storage unit, and increments the stored multiframe count value by one as an updated multiframe count value in a clock cycle when the column count value is 238 and the row count value is 1. The updated multiframe count value is then stored in the storage space corresponding to the channel number in the second storage unit.

4. The device according to claim 1, characterized in that The overhead processing module includes a BIP overhead processing unit and a third storage unit, wherein, for each channel number, If the column count value of the current clock cycle is the first value and the row count value is 0, or if the column count value of the current clock cycle is the first value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and a 144-bit payload signal in the second fgODUflex signal; If the column count value of the current clock cycle is the second value and the row count value is 0, or if the column count value of the current clock cycle is the second value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal; The BIP overhead processing unit performs BIP-8 calculation on each acquired 144-bit payload signal and each second fgODUflex signal to obtain a BIP overhead of the current frame, and stores the BIP overhead of the current frame in a storage space corresponding to the channel number in the third storage unit; If the column count value of the current clock cycle is 0 and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the BIP overhead of the previous frame corresponding to the channel number into the corresponding bit position of the second fgODUflex signal, wherein the third storage unit stores the BIP overhead of the previous frame, the BIP overhead of the previous frame, and the BIP overhead of the current frame corresponding to each channel number, wherein the first value is one of the following: 0, 59, 119, 179, and the second value is any value between 0 and 238 except the first value.

5. The device according to claim 1, characterized in that The overhead processing module includes a BWR overhead processing unit and a fourth storage unit, wherein, for each channel number, If the column value in the current clock cycle is 0 and the row value is 0, the BWR overhead processing unit obtains the first 3 bits of data at bit positions 143 to 141 of the corresponding channel number and the second fgODUflex signal, and stores the first 3 bits of data in the storage space corresponding to the channel number in the third storage unit 144; If the column value in the current clock cycle is 119 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the second 3-bit data at bit positions 15 to 13 in the second fgODUflex signal, and stores the second 3-bit data in the storage space corresponding to the channel number in the third storage unit 144; If the column value in the current clock cycle is 0 and the row value is 1, the BWR overhead processing unit obtains the corresponding channel number and the CRC-3 data with bit positions 143~141 in the second fgODUflex signal, performs CRC-3 calculation on the stored first 3-bit data and the second 3-bit data, and verifies the calculated result with the obtained CRC-3 data. If they are consistent, the bandwidth adjustment indication is output.

6. The device according to claim 1, characterized in that The overhead processing module includes a reporting overhead processing unit and a fifth storage unit. For each channel number, If the column value in the current clock cycle is 0 and the row count value is 0, the report overhead processing unit obtains the channel number corresponding to the clock cycle, outputs an indication signal to the receiving side, and receives the report overhead output from the receiving side, and the fifth storage unit stores the report overhead in the storage space corresponding to the channel number, wherein the report overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead; If the column count value and the row count value in the current clock cycle are 0 and 0, or if the column count value and the row count value in the current clock cycle are 0 and 1, the report overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 163, 159, and 155 of the second fgODUflex signal, respectively; If the column count value in the current clock cycle is 119 and the row count value is 0, or if the column count value in the current clock cycle is 119 and the row count value is 1, the report overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 35, 31, and 27 of the second fgODUflex signal, respectively; If the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to the channel number into bit positions 167-164, 215-212, and 191-188 of the second fgODUflex signal, respectively.

7. The device according to claim 1, wherein The pin processing module includes a TTI overhead processing unit and a sixth storage unit. The sixth storage unit uses the channel number, the least significant two bits of the multiframe indicator, and the position sequence number as a storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number is used to indicate the position sequence of the TTI overhead in the fgODUflex frame structure. The position sequence numbers are 00, 01, 10, and 11. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead. For each channel number, if the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 00 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal, respectively. If the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 01 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal, respectively. If the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 10 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal, respectively. If the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the least significant two bits of the multiframe indicator, and 11 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal, respectively.

8. The device according to claim 1, wherein The overhead processing module includes a STAT overhead processing unit 1 and a seventh storage unit. The seventh storage unit uses the channel number as a storage address. The storage space corresponding to each storage address is used to store the corresponding STAT overhead. The STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead. For each channel number, if the column count value in the current clock cycle is 0 and the row count value is 0, or if the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 162-160, 158-156, and 154-152 of the second fgODUflex signal, respectively; If the column count value in the current clock cycle is 119 and the row count value is 0, or the column count value in the current clock cycle is 119 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 34~32, 30~28, and 26~24 of the second fgODUflex signal, respectively.

9. The device according to claim 1, wherein The overhead processing module includes an APS overhead processing unit and an eighth storage unit. The eighth storage unit uses the channel number as a storage address. The storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead. For each channel number, if the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM ASP overhead, TCM2ASP overhead, and TCM1 ASP overhead corresponding to the channel number into bit positions 63 to 48, 95 to 80, and 79 to 64 of the second fgODUflex signal, respectively.

10. A method for processing overhead of a fine-grained optical transport network based on FPGA, characterized in that: The method comprises: Converting a first fgODUflex signal having a first bit width into a second fgODUflex signal having a second bit width, and having each second fgODUflex signal occupy the same data bus in a time division multiplexing manner, wherein both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers; For each clock cycle of the system clock, the following processing is performed: Obtaining a channel number, a second fgODUflex signal, and a frame header indication signal corresponding to a current clock cycle, performing byte counting on the second fgODUflex signal in response to the frame header indication signal, and obtaining a column count value and a row count value corresponding to the channel number in the current clock cycle; Obtaining the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches a column count maximum value and the row count value reaches a row count maximum value, incrementing the multiframe count value corresponding to the channel number by one to obtain the multiframe count value corresponding to the channel number. Obtaining a channel number, a second fgODUflex signal, a column count value, a row count value, and a multiframe count value corresponding to a current clock cycle, determining a position of an overhead byte based on the column count value, the row count value, and the multiframe count value, and performing overhead byte insertion at the position; in, A 64-bit first fgODUflex signal is input in each clock cycle, and four 64-bit first fgODUflex signals input in four consecutive clock cycles are combined into a 256-bit second fgODUflex signal. When the 64-bit first fgODUflex signal is input in the first clock cycle, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

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