Semiconductor structure and manufacturing method thereof
By growing and etching the sacrificial layer on the P-type semiconductor layer, forming a high-resistance zone and setting a protective layer, the problem of surface morphology deterioration in the preparation of P-type GaN materials is solved, and the reliability and electrical performance of the enhanced HEMT device are improved.
Patent Information
- Application Number
- CN202311846790.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-08
AI Technical Summary
It is difficult to prepare high-quality P-type GaN materials. The surface morphology deteriorates during the activation of P-type GaN materials with high temperature annealing, resulting in device leakage and pre-breakdown, affecting the reliability of enhanced HEMT devices.
By growing the sacrificial layer on the P-type semiconductor layer, magnesium ions are diffused into the sacrificial layer, and the sacrificial layer is repeatedly etched until the concentration of magnesium ion decreases to a preset value, a high resistance region is formed, and a protective layer is formed on the surface, and a source electrode, a drain electrode and a gate electrode are provided.
The magnesium ion concentration on the surface of the P-type semiconductor layer is reduced, the device's gate leakage current is small, the breakdown voltage is high, and the threshold voltage stability is improved, and the device's reliability and leakage voltage performance are improved.
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Figure CN120282466A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] Gallium nitride high electron mobility transistors (HEMTs) have advantages such as wide bandgap, high breakdown field strength, high electron mobility, and high energy conversion efficiency, and have great potential in high-frequency and high-power power electronics applications.
[0003] Conventional AlGaN / GaN high electron mobility transistors are normally-on devices. However, in actual application scenarios, considering factors such as actual cost and fault protection, enhanced HEMT devices are often required. After decades of development, currently, the methods for fabricating enhanced HEMT devices mainly include trench gates, fluoride ion implantation, and P-GaN gates, etc. Among them, P-GaN gate enhanced HEMT devices have been commercialized and shown broad development prospects.
[0004] However, it is difficult to fabricate high-quality P-type GaN materials. During the process of annealing at high temperature to activate Mg ions in the P-type GaN material, the surface of the P-type GaN will be damaged. The deterioration of the surface morphology will introduce a large number of defects, resulting in device leakage and pre-breakdown, and there will also be problems of reduced reliability. Summary of the Invention
[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to further improve the quality of P-type GaN in P-GaN gate enhanced HEMT devices.
[0006] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, characterized by including the following steps:
[0007] S1. Stack a substrate, a heterojunction structure layer, and a P-type semiconductor layer in sequence;
[0008] S2. Retain the P-type semiconductor layer in the gate region and etch the P-type semiconductor layer in the non-gate region;
[0009] S3. Grow a sacrificial layer on the protective layer, and magnesium ions on the surface of the P-type semiconductor layer diffuse into the sacrificial layer;
[0010] S4. Etch the sacrificial layer;
[0011] S5. Set a source electrode on the heterojunction structure layer in the source region, set a drain electrode on the heterojunction structure layer in the drain region, and set a gate electrode in the gate region;
[0012] Before entering step S5, steps S3 and S4 are repeated N times until the magnesium ion concentration on the surface of the P-type semiconductor layer is less than a preset value, forming a high-resistance region.
[0013] As an optional embodiment, the method of etching the sacrificial layer in step S4 is in-situ etching.
[0014] As an optional embodiment, after repeating steps S3 and S4 N times, step S3 is performed again, and the sacrificial layer is retained. The material of the sacrificial layer is AlN.
[0015] As an optional embodiment, after step S2 and before step S3, it further includes:
[0016] S21. A protective layer is conformally disposed on the P-type semiconductor layer.
[0017] As an optional embodiment, the materials of the sacrificial layer and the protective layer are different.
[0018] As an optional embodiment, the etching selectivity ratio of the sacrificial layer to the protective layer is greater than 1. The material of the sacrificial layer is GaN and the material of the protective layer is AlN, or
[0019] the material of the sacrificial layer is AlGaN and the material of the protective layer is AlN, or
[0020] the material of the sacrificial layer is GaN and the material of the protective layer is AlGaN.
[0021] As an optional embodiment, the material of the sacrificial layer is AlN and the material of the protective layer is AlGaN.
[0022] As an optional embodiment, the sacrificial layer is an unintentionally doped layer.
[0023] As an optional embodiment, the material of the protective layer is different from that of the P-type semiconductor layer.
[0024] As an optional embodiment, in step S2, the P-type semiconductor layer in the non-gate region is etched, and the etching depth is less than the thickness of the P-type semiconductor layer. The P-type semiconductor layer in the gate region is the first P-type region, and the P-type semiconductor layer remaining after etching in the non-gate region is the second P-type region.
[0025] As an optional embodiment, the thickness of the second P-type region is 1 - 50 nm.
[0026] As an optional embodiment, the thickness of the high-resistance region in the non-gate region is equal to the thickness of the second P-type region.
[0027] As an alternative embodiment, the thickness of the high-resistance region in the gate region is greater than or equal to the thickness of the second P-type region and less than the thickness of the first P-type region.
[0028] As an alternative embodiment, the magnesium ion concentration in the P-type semiconductor layer is greater than 1E17 / cm 3 .
[0029] As an alternative embodiment, the magnesium ion concentration in the high-resistance region is less than 1E15 / cm 3 .
[0030] As an alternative embodiment, along the direction from the substrate to the P-type semiconductor layer, the P-type semiconductor layer includes a low-resistance region and the high-resistance region stacked thereon, and the magnesium ion concentration in the low-resistance region gradually decreases along the direction from the substrate to the P-type semiconductor layer.
[0031] As an alternative embodiment, before the step S5, further included is:
[0032] Annealing the P-type semiconductor layer to activate the magnesium ions in the P-type semiconductor layer.
[0033] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized by including the semiconductor structure obtained by using the manufacturing method of any one of the above semiconductor structures, including:
[0034] A substrate, a heterojunction structure layer, and a P-type semiconductor layer stacked in sequence, the P-type semiconductor layer is located in the gate region, and the surface of the P-type semiconductor layer is a high-resistance region;
[0035] A source electrode on the heterojunction structure layer in the source region, a drain electrode on the heterojunction structure layer in the drain region, and a gate electrode in the gate region.
[0036] As an alternative embodiment, the P-type semiconductor layer includes a first P-type region in the gate region and a second P-type region in the non-gate region, and the thickness of the first P-type region is greater than the thickness of the second P-type region.
[0037] As an alternative embodiment, along the direction from the substrate to the P-type semiconductor layer, the P-type semiconductor layer includes a low-resistance region and the high-resistance region stacked thereon, and the magnesium ion concentration in the low-resistance region gradually decreases along the direction from the substrate to the P-type semiconductor layer.
[0038] The present disclosure provides a semiconductor structure and a manufacturing method thereof. A substrate, a heterojunction structure layer, and a P-type semiconductor layer are sequentially stacked; the P-type semiconductor layer in the gate region is retained, and the P-type semiconductor layer in the non-gate region is etched; a sacrificial layer is grown on the P-type semiconductor layer, and magnesium ions on the surface of the P-type semiconductor layer diffuse into the sacrificial layer; the sacrificial layer is etched; the growth and etching of the sacrificial layer are repeated N times until the magnesium ion concentration on the surface of the P-type semiconductor layer is less than a preset value to form a high-resistance region; a source electrode, a drain electrode, and a gate electrode are provided.
[0039] The present disclosure reduces the magnesium ions on the surface of the P-type semiconductor layer by repeatedly growing and then etching the sacrificial layer, and forms a high-resistance region on the surface of the P-type semiconductor layer, so as to obtain an enhanced HEMT device with small gate leakage current, high breakdown voltage, and stable threshold voltage.
[0040] The setting of the protective layer in the present disclosure can, on the one hand, protect the P-type semiconductor layer, reduce the damage caused to the P-type semiconductor layer during the annealing process, improve the quality of the surface topography of the P-type semiconductor layer, thereby improving the device leakage voltage and pre-breakdown problems, and improving the reliability of the device; on the other hand, it can act as an etching stop layer to avoid damaging the P-type semiconductor layer when etching the sacrificial layer subsequently. Description of the Drawings
[0041] Figure 1 The figure shows a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure.
[0042] Figures 2 to 7 As shown Figure 1 The figure shows a schematic diagram of an intermediate structure corresponding to the shown process.
[0043] Figures 8 to 10 The figure shows a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present disclosure.
[0044] Figures 11 to 13 The figure shows a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present disclosure. Detailed Embodiments
[0045] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
[0046] In order to further improve the quality of P-type GaN in a P-GaN gate-enhanced HEMT device, the present disclosure provides a semiconductor structure and a manufacturing method thereof, which sequentially stack a substrate, a heterojunction structure layer, and a P-type semiconductor layer; retain the P-type semiconductor layer in the gate region and etch the P-type semiconductor layer in the non-gate region; grow a sacrificial layer on the P-type semiconductor layer, and magnesium ions on the surface of the P-type semiconductor layer diffuse into the sacrificial layer; etch the sacrificial layer; repeat the growth and etching of the sacrificial layer N times until the magnesium ion concentration on the surface of the P-type semiconductor layer is less than a preset value to form a high-resistance region; and set a source electrode, a drain electrode, and a gate electrode. The present disclosure reduces the magnesium ions on the surface of the P-type semiconductor layer by growing and etching the sacrificial layer multiple times, and forms a high-resistance region on the surface of the P-type semiconductor layer, so as to obtain an enhanced HEMT device with small gate leakage current, high breakdown voltage, and stable threshold voltage.
[0047] The following further exemplifies Figures 1 to 13 a semiconductor structure and a manufacturing method thereof mentioned in the present disclosure.
[0048] Figure 1 The figure shows a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 7 The figure shows Figure 1 a schematic diagram of an intermediate structure corresponding to the shown process. As Figure 1 shown, a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
[0049] Step S1: Sequentially stack a substrate, a heterojunction structure layer, and a P-type semiconductor layer.
[0050] Specifically, as Figure 2 shown, a substrate 10, a heterojunction structure layer 20, and a P-type semiconductor layer 30 are sequentially stacked. The material of the substrate 10 includes any one or a combination of multiple of Si, Al2O3, GaN, SiC, or AlN. The heterojunction structure layer 20 includes a channel layer and a barrier layer stacked in a direction away from the substrate 10, and the bandgap width of the material of the barrier layer is greater than that of the material of the channel layer. The material of the channel layer and the material of the barrier layer may include group III nitride materials, and a two-dimensional electron gas may be formed at the interface between the channel layer and the barrier layer. In an alternative solution, the channel layer is a GaN layer and the barrier layer is an AlGaN layer. In other alternative solutions, the material combination of the channel layer and the barrier layer may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The material of the P-type semiconductor layer 30 includes group III nitride materials, and the magnesium ion concentration in the P-type semiconductor layer 30 is greater than 1E17 / cm 3 .
[0051] Step S2: Retain the P-type semiconductor layer in the gate region and etch the P-type semiconductor layer in the non-gate region.
[0052] Specifically, as Figure 3 shown, retain the P-type semiconductor layer 30 in the gate region and etch the P-type semiconductor layer 30 in the non-gate region.
[0053] Step S3: Grow a sacrificial layer on the P-type semiconductor layer, and magnesium ions on the surface of the P-type semiconductor layer diffuse into the sacrificial layer.
[0054] Specifically, as Figure 4 shown, grow a sacrificial layer 50 on the P-type semiconductor layer 30, and magnesium ions on the surface of the P-type semiconductor layer 30 diffuse into the sacrificial layer 50. The sacrificial layer 50 is an unintentionally doped layer. Magnesium ions on the surface of the P-type semiconductor layer 30 will diffuse into the sacrificial layer 50, and impurity ions in the epitaxial cavity can also diffuse into the sacrificial layer 50, thereby reducing the concentration of magnesium ions on the surface of the P-type semiconductor layer 30 and the concentration of impurity ions in the epitaxial cavity. Optionally, the sacrificial layer 50 is carbon-doped, iron-doped, or iron-carbon co-doped. Further, the carbon doping, iron doping, or iron-carbon co-doping of the sacrificial layer 50 is a graded doping. Doping iron or carbon in the sacrificial layer 50 can form deep-level traps, thereby providing recombination centers to capture holes on the surface of the P-type semiconductor layer 30, thereby reducing the concentration of magnesium ions on the surface of the P-type semiconductor layer 30 and simultaneously reducing the concentration of impurity ions in the epitaxial cavity.
[0055] Step S4: Etch the sacrificial layer.
[0056] Specifically, etch the sacrificial layer 50 to form an intermediate structure as Figure 3 shown. The method for etching the sacrificial layer 50 is in-situ etching. The in-situ etching method will not introduce impurities, can reduce the interface state density, and is beneficial to reducing the current collapse effect and leakage current of the subsequent fabricated device.
[0057] Repeat step S3 and step S4 for N times until the concentration of magnesium ions on the surface of the P-type semiconductor layer 30 is less than a preset value, and a high-resistance region 31 is formed, as Figure 5 shown. The preset value is 1E15 / cm 3 . The concentration of magnesium ions in the P-type semiconductor layer 30 is greater than 1E17 / cm 3 . After multiple growths and etchings of the sacrificial layer 50, the concentration of magnesium ions on the surface of the P-type semiconductor layer 30 can be reduced to less than 1E15 / cm 3 , that is, the concentration of magnesium ions in the high-resistance region 31 is less than 1E15 / cm 3 . As Figure 5As shown, in the direction from the substrate 10 towards the P-type semiconductor layer 30, the P-type semiconductor layer 30 includes a low-resistance region 32 and a high-resistance region 31 which are stacked. The growth and etching of the multiple sacrificial layers 50 can also make the magnesium ion concentration in the low-resistance region 32 gradually decrease in the direction from the substrate 10 towards the P-type semiconductor layer 30, further reducing the gate leakage current of the subsequently prepared semiconductor structure. After repeating steps S3 and S4 for N times, step S3 is executed again. As Figure 6 shown, the last grown sacrificial layer 50 is retained. The material of the sacrificial layer 50 is AlN. At this time, the sacrificial layer 50 can act as a protective layer to prevent the surface morphology of the P-type semiconductor layer 30 from deteriorating during the annealing process, resulting in device leakage. Before preparing the electrodes, the P-type semiconductor layer 30 is annealed to activate the magnesium ions in the P-type semiconductor layer 30, so as to deplete the two-dimensional electron gas in the gate region of the heterojunction structure layer 20 and realize an enhancement-mode device.
[0058] Step S6: A source electrode is provided on the heterojunction structure layer in the source region, a drain electrode is provided on the heterojunction structure layer in the drain region, and a gate electrode is provided in the gate region.
[0059] Specifically, a source electrode 61 is provided on the heterojunction structure layer 20 in the source region, a drain electrode 62 is provided on the heterojunction structure layer 20 in the drain region, and a gate electrode 63 is provided in the gate region to form a semiconductor structure as Figure 7 shown.
[0060] Figures 8 to 10 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, after step S2 and before step S3, it further includes: step S21: conformally providing a protective layer on the P-type semiconductor layer. As Figure 8 shown, a protective layer 40 is conformally provided on the P-type semiconductor layer 30. The material of the protective layer 40 is different from that of the P-type semiconductor layer 30. The sacrificial layer 50 is grown on the protective layer 40 multiple times. After etching the sacrificial layer 50, an intermediate structure as Figure 9 shown is formed. The material of the sacrificial layer 50 is different from that of the protective layer 40, and the etching selectivity ratio of the sacrificial layer 50 to the protective layer 40 is greater than 1. For example, the material of the sacrificial layer 50 is GaN and the material of the protective layer 40 is AlN, or the material of the sacrificial layer 50 is AlGaN and the material of the protective layer 40 is AlN, or the material of the sacrificial layer 50 is GaN and the material of the protective layer 40 is AlGaN. After repeating the growth and etching of the sacrificial layer 50 multiple times and then setting the electrodes, a semiconductor structure as Figure 10The semiconductor structure shown. In this embodiment, the setting of the protective layer 40 can, on the one hand, protect the P-type semiconductor layer 30, reduce the damage caused to the P-type semiconductor layer 30 during the annealing process, improve the quality of the surface morphology of the P-type semiconductor layer 30, thereby improving the problems of device leakage voltage and pre-breakdown, and improving the reliability of the device; on the other hand, it can act as an etch stop layer to avoid damaging the P-type semiconductor layer during subsequent etching of the sacrificial layer.
[0061] Figures 11 to 13 The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as Figure 11 shown, in step S2, the P-type semiconductor layer 30 in the non-gate region is etched, and the etching depth is less than the thickness of the P-type semiconductor layer 30. The P-type semiconductor layer 30 in the gate region is the first P-type region 301, and the P-type semiconductor layer 30 remaining after etching in the non-gate region is the second P-type region 302. The thickness of the second P-type region 302 is 1-50 nm. The P-type semiconductor layer 30 in the non-gate region is not completely etched to form the second P-type region 302, which will not damage the surface quality of the heterojunction structure layer 20, and the second P-type region 302 will form a high-resistance region later, which can ensure the channel conduction ability. After growing the sacrificial layer 50 on the P-type semiconductor layer 30 and etching the sacrificial layer 50 repeatedly N times, a semiconductor intermediate structure as Figure 12 shown is formed. The thickness of the second P-type region 302 is small and can completely become the high-resistance region 31, that is, the thickness of the high-resistance region 31 in the non-gate region is equal to the thickness of the second P-type region 302. Only the surface of the first P-type region 301 becomes the high-resistance region 31, and the thickness of the high-resistance region 31 in the gate region is greater than or equal to the thickness of the second P-type region 302 and less than the thickness of the first P-type region 301. Then, the protective layer 40 and the P-type semiconductor layer 30 in the source region and the drain region are etched to expose the heterojunction structure layer 20. A source electrode 61 is provided in the source region, a drain electrode 62 is provided in the drain region, and a gate electrode 63 is provided in the gate region to form a semiconductor structure as Figure 13 shown.
[0062] According to another aspect of the present disclosure, the present disclosure also provides a semiconductor structure, as Figure 7 shown, the semiconductor structure is a semiconductor structure obtained by the manufacturing method of the above semiconductor structure, including: a substrate 10, a heterojunction structure layer 20, and a P-type semiconductor layer 30 stacked in sequence. The P-type semiconductor layer 30 is at least located in the gate region. The surface of the P-type semiconductor layer 30 is a high-resistance region 31. A source electrode 61 is provided on the heterojunction structure layer 20 in the source region, a drain electrode 62 is provided on the heterojunction structure layer 20 in the drain region, and a gate electrode 63 is provided in the gate region.
[0063] In this embodiment, in the direction from the substrate 10 towards the P-type semiconductor layer 30, the P-type semiconductor layer 30 includes a low-resistance region 32 and a high-resistance region 31 which are stacked, and the magnesium ion concentration in the low-resistance region 32 gradually decreases in the direction from the substrate 10 towards the P-type semiconductor layer 30.
[0064] In one embodiment, as Figure 11 shown, the P-type semiconductor layer 30 includes a first P-type region 301 located in the gate region and a second P-type region 302 located in the non-gate region. The thickness of the first P-type region 301 is greater than the thickness of the second P-type region 302. After growing and etching the sacrificial layer 50 multiple times, electrodes are provided to form a semiconductor structure as Figure 13 shown.
[0065] The present disclosure provides a semiconductor structure and a manufacturing method thereof. A substrate, a heterojunction structure layer, and a P-type semiconductor layer are sequentially stacked; the P-type semiconductor layer in the gate region is retained, and the P-type semiconductor layer in the non-gate region is etched; a sacrificial layer is grown on the P-type semiconductor layer, and magnesium ions on the surface of the P-type semiconductor layer diffuse into the sacrificial layer; the sacrificial layer is etched; the growth and etching of the sacrificial layer are repeated N times until the magnesium ion concentration on the surface of the P-type semiconductor layer is less than a preset value to form a high-resistance region; a source electrode, a drain electrode, and a gate electrode are provided.
[0066] Through the method of first growing the sacrificial layer and then etching it multiple times, the present disclosure reduces the magnesium ions on the surface of the P-type semiconductor layer and forms a high-resistance region on the surface of the P-type semiconductor layer, and an enhanced HEMT device with small gate leakage current, high breakdown voltage, and stable threshold voltage can be obtained.
[0067] The setting of the protective layer in the present disclosure can, on the one hand, protect the P-type semiconductor layer, reduce the damage caused to the P-type semiconductor layer during the annealing process, improve the quality of the surface topography of the P-type semiconductor layer, thereby improving the problems of device leakage voltage and pre-breakdown, and improving the reliability of the device; on the other hand, it can act as an etching stop layer to avoid damaging the P-type semiconductor layer when etching the sacrificial layer subsequently.
[0068] It should be understood that the term "including" and its variants used in the present disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0069] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A manufacturing method of a semiconductor structure, characterized in that, It includes the following steps: S1. Stack a substrate (10), a heterojunction structure layer (20), and a P-type semiconductor layer (30) in sequence; S2. Retain the P-type semiconductor layer (30) in the gate region, and etch the P-type semiconductor layer (30) in the non-gate region; S3. Grow a sacrificial layer (50) on the P-type semiconductor layer (30), and magnesium ions on the surface of the P-type semiconductor layer (30) diffuse into the sacrificial layer (50); S4. Etch the sacrificial layer (50); S5. Set a source electrode (61) on the heterojunction structure layer (20) in the source region, set a drain electrode (62) on the heterojunction structure layer (20) in the drain region, and set a gate electrode (63) in the gate region; Before entering step S5, repeat step S3 and step S4 for N times until the magnesium ion concentration on the surface of the P-type semiconductor layer (30) is less than a preset value to form a high-resistance region (31).
2. The manufacturing method of the semiconductor structure according to claim 1, wherein, The method for etching the sacrificial layer (50) in step S4 is in-situ etching.
3. The manufacturing method of the semiconductor structure according to claim 1, wherein, After repeating step S3 and step S4 for N times, perform step S3 again, retain the sacrificial layer (50), and the material of the sacrificial layer (50) is AlN.
4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The sacrificial layer (50) is an unintentionally doped layer.
5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, After step S2 and before step S3, it further includes: S21. Conformally set a protective layer (40) on the P-type semiconductor layer (30).
6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, The material of the sacrificial layer (50) is different from that of the protective layer (40).
7. The manufacturing method of the semiconductor structure according to claim 6, wherein, The etching selectivity of the sacrificial layer (50) to the protective layer (40) is greater than 1, the material of the sacrificial layer (50) is GaN and the material of the protective layer (40) is AlN, or, The material of the sacrificial layer (50) is AlGaN and the material of the protective layer (40) is AlN, or, The material of the sacrificial layer (50) is GaN and the material of the protective layer (40) is AlGaN.
8. The manufacturing method of the semiconductor structure according to claim 6, wherein, The material of the sacrificial layer (50) is AlN and the material of the protective layer (40) is AlGaN.
9. The manufacturing method of the semiconductor structure according to claim 5, wherein, The material of the protective layer (40) is different from that of the P-type semiconductor layer (30).
10. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, In step S2, when etching the P-type semiconductor layer (30) in the non-gate region, the etching depth is less than the thickness of the P-type semiconductor layer (30), the P-type semiconductor layer (30) in the gate region is the first P-type region (301), and the P-type semiconductor layer (30) retained after etching in the non-gate region is the second P-type region (302).
11. The manufacturing method of the semiconductor structure according to claim 10, characterized in that, The thickness of the second P-type region (302) is 1 - 50 nm.
12. The manufacturing method of the semiconductor structure according to claim 10, wherein, The thickness of the high-resistance region (31) in the non-gate region is equal to the thickness of the second P-type region (302).
13. The manufacturing method of the semiconductor structure according to claim 10, wherein, The thickness of the high-resistance region (31) in the gate region is greater than or equal to the thickness of the second P-type region (302) and less than the thickness of the first P-type region (301).
14. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The magnesium ion concentration in the P-type semiconductor layer (30) is greater than 1E17 / cm 3 .
15. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The magnesium ion concentration in the high-resistance region (31) is less than 1E15 / cm 3 .
16. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, In the direction from the substrate (10) towards the P-type semiconductor layer (30), the P-type semiconductor layer (30) includes a low-resistance region (32) and the high-resistance region (31) which are stacked, and the magnesium ion concentration in the low-resistance region (32) gradually decreases in the direction from the substrate (10) towards the P-type semiconductor layer (30).
17. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Before the step S5, it further includes: Annealing the P-type semiconductor layer (30) to activate the magnesium ions in the P-type semiconductor layer (30).
18. A semiconductor structure, characterized in that, The semiconductor structure obtained by using the manufacturing method of the semiconductor structure according to any one of claims 1-17 includes: The substrate (10), the heterojunction structure layer (20) and the P-type semiconductor layer (30) which are stacked in sequence, the P-type semiconductor layer (30) is at least located in the gate region, and the surface of the P-type semiconductor layer (30) is the high-resistance region (31); The source electrode (61) on the heterojunction structure layer (20) in the source region, the drain electrode (62) on the heterojunction structure layer (20) in the drain region, and the gate electrode (63) in the gate region.
19. The semiconductor structure according to claim 18, wherein, The P-type semiconductor layer (30) includes a first P-type region (301) in the gate region and a second P-type region (302) in the non-gate region, and the thickness of the first P-type region (301) is greater than the thickness of the second P-type region (302).
20. The semiconductor structure according to claim 18, wherein, In the direction from the substrate (10) towards the P-type semiconductor layer (30), the P-type semiconductor layer (30) includes a low-resistance region (32) and the high-resistance region (31) which are stacked, and the magnesium ion concentration in the low-resistance region (32) gradually decreases in the direction from the substrate (10) towards the P-type semiconductor layer (30).