TopCon battery and preparation method thereof

Abstract

The invention discloses a TopCon battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate; the N-type silicon substrate comprises a front surface and a back surface; preparing a front surface field layer and a suede structure on the front surface; preparing a first tunneling oxide layer and a first doping layer on the back surface; carrying out passivation and hydrogenation treatment on the N-type silicon substrate by using a preset process; preparing a first protection layer on the surface of one side, deviating from the N-type silicon substrate, of the textured structure; and performing silk-screen printing and high-temperature sintering on the N-type silicon substrate to form a first electrode in contact with the first doping layer on the back surface and form a second electrode in contact with the front surface field layer on the front surface. According to the method, the N-type silicon substrate is passivated and hydrotreated before the first protection layer is prepared on the front side, so that the iron ion passivation rate and the dislocation passivation rate are improved, the attenuation rate is reduced, and the stability and the conversion efficiency of the cell are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and particularly relates to a TopCon cell and a preparation method thereof. Background Art

[0002] With the continuous growth of the global demand for clean energy, solar energy, as an inexhaustible and renewable energy source, has attracted much attention.

[0003] In the development of solar cell technology, for TopCon cells, usually after forming a textured surface on the front side, an alumina passivation layer is directly formed on the side of the textured structure away from the substrate by the ALD process. However, this process will cause impurities and defects in the substrate not to be pre-activated, and hydrogen atoms are difficult to be fully passivated, resulting in a low passivation rate; at the same time, it will also cause insufficient degradation inhibition, resulting in too high an attenuation rate and affecting the conversion efficiency of the cell. Summary of the Invention

[0004] The present invention provides a TopCon cell and a preparation method thereof, which improve the iron ion passivation rate and dislocation passivation rate, reduce the attenuation rate, and improve the stability and conversion efficiency of the cell by passivating and hydrogenating the N-type silicon substrate before preparing the first protective layer on the front side.

[0005] In a first aspect, the present invention provides a preparation method of a TopCon cell, including:

[0006] Providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side;

[0007] Preparing a front surface field layer and a textured structure on the front side;

[0008] Preparing a first tunneling oxide layer and a first doping layer on the back side;

[0009] Using a preset process to passivate and hydrogenate the N-type silicon substrate;

[0010] Preparing a first protective layer on the side surface of the textured structure facing away from the N-type silicon substrate;

[0011] Performing screen printing and high-temperature sintering on the N-type silicon substrate to form a first electrode in contact with the first doping layer on the back side and a second electrode in contact with the front surface field layer on the front side.

[0012] Optionally, using a preset process to passivate and hydrogenate the N-type silicon substrate includes:

[0013] Using a preset activation process to passivate the N-type silicon substrate under a first preset condition;

[0014] Using a preset hydrogenation process to hydrogenate the N-type silicon substrate under a second preset condition;

[0015] Using the liquid nitrogen injection process, the N-type silicon substrate is rapidly cooled under the third preset condition.

[0016] Optionally, the second preset condition includes introducing a mixed gas formed by hydrogen with a flow rate of 1000 sccm / min - 3000 sccm / min and argon with a flow rate of 3000 sccm / min - 8000 sccm / min into the reaction chamber of the hydrogenation furnace equipment, the second preset temperature is 280°C - 350°C, and the hydrogenation time is 1 min - 5 min.

[0017] Optionally, the third preset condition includes a cooling rate of 50°C / s - 100°C / s.

[0018] Optionally, the preset activation process includes a low-temperature relaxation process and a high-temperature activation process;

[0019] Using the preset activation process, the N-type silicon substrate is passivated under the first preset condition, including:

[0020] Using the preset low-temperature relaxation process, the lattice stress of the N-type silicon substrate is released under the first preset low-temperature condition;

[0021] Using the high-temperature activation process, the defects of the N-type silicon substrate are activated under the first preset high-temperature condition to passivate the N-type silicon substrate.

[0022] Optionally, the first preset low-temperature condition includes introducing nitrogen with a flow rate of 5000 sccm / min - 10000 sccm / min into the tube furnace equipment, the first preset low temperature is 50°C - 70°C, and the first low-temperature time is 8 min - 15 min.

[0023] Optionally, the first preset high-temperature condition includes the first preset high temperature of 75°C - 90°C and the first low-temperature time of 12 min - 20 min.

[0024] Optionally, preparing the front surface field layer and the textured structure on the front surface includes:

[0025] Using the boron diffusion process, boron doping is carried out on the front surface to form a front surface field layer on the front surface;

[0026] Using the texturing process, texturing is carried out on the front surface field layer and the back surface to form a textured structure.

[0027] Optionally, preparing the first tunneling oxide layer and the first doping layer on the back surface includes:

[0028] Removing the textured structure on the back surface to expose the N-type silicon substrate on the back surface;

[0029] Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are deposited on the surface of the exposed backside of the N-type silicon substrate;

[0030] Using a phosphorus diffusion process, the first intrinsic silicon layer is doped with phosphorus to form a first doped layer and a first mask layer on the backside;

[0031] Remove the first mask layer.

[0032] Optionally, after preparing a first protective layer on the surface of the side of the textured structure facing away from the N-type silicon substrate, it further includes:

[0033] Prepare a second protective layer on the surface of the side of the first doped layer facing away from the N-type silicon substrate.

[0034] In a second aspect, the present invention provides a TopCon battery, which is obtained by using the preparation method of the TopCon battery described above.

[0035] The technical solution of the present invention provides an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side; a front surface field layer and a textured structure are prepared on the front side; a first tunneling oxide layer and a first doped layer are prepared on the back side; using a preset process, the N-type silicon substrate is passivated and hydrogenated; a first protective layer is prepared on the surface of the side of the textured structure facing away from the N-type silicon substrate; screen printing and high-temperature sintering are performed on the N-type silicon substrate to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the front surface field layer on the front side. By using the above method, by passivating and hydrogenating the N-type silicon substrate before preparing the first protective layer on the front side, the iron ion passivation rate and dislocation passivation rate are improved, the attenuation rate is reduced, and the stability and conversion efficiency of the battery are improved.

[0036] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a flowchart of a preparation method of a TopCon battery provided by an embodiment of the present invention;

[0039] Figure 2 It is a process flowchart of a preparation process of a TopCon battery provided by an embodiment of the present invention;

[0040] Figure 3 Schematic diagram of the structure of a TopCon battery provided by an embodiment of the present invention;

[0041] Figure 4 Flow chart of the preparation method of the second TopCon battery provided by an embodiment of the present invention;

[0042] Figure 5 Flow chart of the preparation method of the third TopCon battery provided by an embodiment of the present invention. Detailed implementation manners

[0043] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, preparation method, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] In one embodiment, Figure 1 Flow chart of the preparation method of a TopCon battery provided by an embodiment of the present invention, Figure 2 Process flow chart of the preparation of a TopCon battery provided by an embodiment of the present invention, Figure 3 Schematic diagram of the structure of a TopCon battery provided by an embodiment of the present invention. This embodiment is applicable to the situation of improving the iron ion passivation rate and dislocation passivation rate in the TopCon battery, reducing the attenuation rate, and thus improving the stability and conversion efficiency of the battery, such as Figures 1 to 3 As shown, the method includes:

[0046] S110. Provide an N-type silicon substrate.

[0047] Among them, referring toFigure 2 As shown in FIG. a), the N-type silicon substrate 1 includes a front surface and a back surface.

[0048] S120. Prepare a front surface field layer and a textured structure on the front surface.

[0049] Among them, the front surface field layer 31 refers to a highly doped region formed by element doping on the front surface of the N-type silicon substrate 1. Usually, a p+ front surface field layer is formed by boron doping on the front surface of the N-type silicon substrate 1 to prevent the surface recombination of photo-generated carriers, improve the carrier lifetime and diffusion length, and enhance the collection efficiency of photo-generated carriers. The textured structure 32 refers to a microscopic structure in the shape of a pyramid or similar fluff formed on the surface of the front surface field layer 31 through processes such as etching, so as to reduce the reflection of sunlight, increase the optical path and light absorption, and improve the short-circuit current of the battery.

[0050] Specifically, referring to Figure 2 As shown in FIG. b), when forming the front surface field layer 31 on the front surface, the boron diffusion process can be used to perform boron doping on the N-type silicon substrate 1 on the front surface, thereby forming the front surface field layer 31. The front surface field layer 31 and the N-type silicon substrate 1 form a PN junction, and the PN junction is responsible for separating photo-generated carriers (electron-hole pairs) to achieve photoelectric conversion. After forming the front surface field layer 31, the texturing process is used to texture the surface of the front surface field layer 31 away from the N-type silicon substrate 1 to form a pyramid-shaped textured structure 32.

[0051] S130. Prepare a first tunneling oxide layer and a first doped layer on the back surface.

[0052] Among them, the first tunneling oxide layer 21 is usually a very thin insulating layer composed of silicon dioxide (SiO2), which is used to allow the majority carriers (electrons) to pass through smoothly through the tunneling effect, and at the same time prevent the recombination of minority carriers (holes), so as to achieve the selective transport of carriers, reduce the surface recombination, improve the open-circuit voltage and fill factor of the battery, and enhance the photoelectric conversion efficiency. The first doped layer 22 is a phosphorus-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping phosphorus elements.

[0053] Specifically, referring to Figure 2 As shown in FIG. c), using the deposition process, the first tunneling oxide layer 21 and the first intrinsic silicon layer are sequentially deposited on the back surface, and the first intrinsic silicon layer is element-doped so that the first intrinsic silicon layer forms the first doped layer 22 after doping. Among them, the methods for depositing the first tunneling oxide layer 21 and the first intrinsic silicon layer include but are not limited to low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc., which can be specifically determined according to the actual situation and are not limited here.

[0054] S140. Use a preset process to passivate and hydrogenate the N-type silicon substrate.

[0055] Among them, the purpose of passivation and hydrogenation treatment is to activate the impurities and defects in the N-type silicon substrate 1, improve the passivation efficiency, at the same time improve the stability of the silicon-hydrogen bond, reduce the attenuation rates of light-induced degradation (LID) and temperature-induced degradation (LeTID), and improve the cell conversion efficiency.

[0056] Specifically, before preparing the first protective layer 4 on the surface of the textured structure 32, use a preset process to passivate and hydrogenate the N-type silicon substrate 1. The preset process may include but is not limited to a pre-activation process, a passivation process, and a cooling process to improve the passivation efficiency and reduce the attenuation rate.

[0057] S150. Prepare a first protective layer on the side surface of the textured structure facing away from the N-type silicon substrate.

[0058] Among them, the first protective layer 4 at least includes a passivation layer and may also include an antireflection layer, which is used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of the cell, at the same time reduce surface recombination, increase the mobility of carriers, and improve the overall performance of the cell. Among them, the components of the passivation layer may include but are not limited to alumina, silica, or a combination of alumina and silica, and the components of the antireflection layer may include but are not limited to silicon nitride, or a combination of silicon nitride and silica, or silicon oxynitride. The thickness of the passivation layer can be 5 nm, and the thickness of the antireflection layer can be 70 nm.

[0059] Specifically, referring to Figure 2 as shown in Figure d) of, after forming the textured structure on the front side, it is necessary to prepare a first protective layer 4 on the side surface of the textured structure 32 on the front side facing away from the N-type silicon substrate 1 to reduce the surface reflection of the TopCon cell, increase the surface area of the TopCon cell, reduce the reflection of sunlight, improve the light trapping effect of the cell and the absorption rate of sunlight, generate more photo-generated carriers, and improve the conversion efficiency of the TopCon cell. Specifically, it can be prepared by processes such as deposition, which is not limited here.

[0060] S160. Screen-print and perform high-temperature sintering on the N-type silicon substrate to form a first electrode in contact with the first doping layer on the back surface and a second electrode in contact with the front surface field layer on the front surface.

[0061] Among them, screen printing is one of the core processes in the manufacturing process of TopCon solar cells, mainly used for electrode forming of TopCon solar cells. During the printing process, the paste is precisely extruded through the mesh holes of the screen onto the N-type silicon substrate 1 to form the required electrode pattern. Generally, the paste for screen printing can include but is not limited to silver paste or aluminum paste, etc. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed on the surface of the solar cell at high temperature to form a good ohmic contact. Among them, the materials of the metal grid lines of the first electrode 6 and the second electrode 7 can be the same or different. In this embodiment, the materials of both the first electrode 6 and the second electrode 7 are silver.

[0062] Specifically, as shown in Figure e) of Figure 2 After the photo-generated carriers generated by the light energy of solar energy are converted into current, they flow to the external circuit for the purpose of forming electrodes on the front and back surfaces. In this embodiment, screen printing is performed on the surfaces of the first protective layer 4 on the front surface and the first doped layer 22 on the back surface, so that metal grid lines are formed on the surfaces of the first doped layer 22 and the first protective layer 4. The metal grid lines include fine grids and main grids. After the metal grid lines are formed, high-temperature sintering needs to be performed on the formed metal grid lines, that is, sintering for 5-10 minutes under the high-temperature sintering conditions of 750°C - 850°C, so that the metal grid lines after high-temperature sintering can enter the first doped layer 22 and the front surface field layer 31, and make the metal grid lines contact with the first doped layer 22 and the front surface field layer 31 to form an ohmic contact. Specifically, after high-temperature sintering, the first electrode 6 in contact with the first doped layer 22 is formed on the back surface, and the second electrode 7 in contact with the front surface field layer 31 is formed on the front surface, thus preparing a TopCon solar cell. In addition, the polarities of the first electrode 6 and the second electrode 7 are opposite. When the first electrode 6 is the positive electrode, the corresponding second electrode 7 is the negative electrode; when the first electrode 6 is the negative electrode, the corresponding second electrode 7 is the positive electrode. In this embodiment, the first electrode 6 is the negative electrode and the second electrode 7 is the positive electrode.

[0063] The technical solution of the embodiment of the present invention provides an N-type silicon substrate; the N-type silicon substrate includes a front surface and a back surface; a front surface field layer and a textured structure are prepared on the front surface; a first tunneling oxide layer and a first doped layer are prepared on the back surface; the N-type silicon substrate is passivated and hydrogenated by a preset process; a first protective layer is prepared on the surface of the textured structure facing away from the N-type silicon substrate; screen printing and high-temperature sintering are performed on the N-type silicon substrate to form a first electrode in contact with the first doped layer on the back surface and a second electrode in contact with the front surface field layer on the front surface. By using the above method, by passivating and hydrogenating the N-type silicon substrate before preparing the first protective layer on the front surface, the iron ion passivation rate and dislocation passivation rate are improved, the attenuation rate is reduced, and the stability and conversion efficiency of the solar cell are improved.

[0064] Figure 4 This is the flowchart of the second preparation method of the TopCon cell provided by the embodiment of the present invention. This embodiment refines the preparation method of the TopCon cell in the above embodiment. For the content not detailed in this embodiment, reference can be made to the above embodiment, which will not be elaborated here. As Figure 3 and Figure 4 shown, the method includes:

[0065] S210. Provide an N-type silicon substrate.

[0066] S220. Prepare a front surface field layer and a textured structure on the front surface.

[0067] S230. Prepare a first tunneling oxide layer and a first doping layer on the back surface.

[0068] S240. Use a preset activation process to passivate the N-type silicon substrate under a first preset condition.

[0069] Among them, this step can be refined as: use a preset low-temperature relaxation process to release the lattice stress of the N-type silicon substrate under a first preset low-temperature condition; use a high-temperature activation process to activate the defects of the N-type silicon substrate under a first preset high-temperature condition, so as to passivate the N-type silicon substrate.

[0070] Optionally, the first preset low-temperature condition includes introducing nitrogen with a flow rate of 5000 sccm / min - 10000 sccm / min into the tube furnace equipment, the first preset low temperature is 50°C - 70°C, and the first low-temperature time is 8 min - 15 min.

[0071] Optionally, the first preset high-temperature condition includes the first preset high temperature of 75°C - 90°C and the first low-temperature time of 12 min - 20 min.

[0072] Among them, the preset activation process includes a low-temperature relaxation process and a high-temperature activation process. The preset low-temperature relaxation process is a process of heat-treating the material at a relatively low temperature to reduce or eliminate the residual stress inside the N-type silicon substrate 1 and improve the overall stability. The preset high-temperature activation process is a process of heat-treating the material at a higher temperature to activate impurities and defects (such as dislocations, etc.).

[0073] Specifically, when passivating the N-type silicon substrate 1, first, using a preset low-temperature relaxation process, nitrogen gas with a volume of 5L - 8L and a flow rate of 5000 sccm / min - 10000 sccm / min is introduced into the tube furnace equipment. Under the first preset low-temperature condition of 50°C - 70°C and the first low-temperature time of 8 min - 15 min, the lattice pressure of the N-type silicon substrate 1 is released to ensure that the tube furnace is in an inert environment. After completion, the temperature of the tube furnace equipment is then raised to 75°C - 90°C and maintained for 12 min - 20 min to activate the impurities and defects in the N-type silicon substrate 1 and maintain the inert environment to prevent impurities from entering during this process.

[0074] It should be noted that the essence of passivating the N-type silicon substrate 1 in the inert environment of nitrogen gas in this step is that the inert environment can prevent the N-type silicon substrate 1 from being oxidized during the heating process and generating unnecessary impurities.

[0075] S250. Using a preset hydrogenation process, hydrogenate the N-type silicon substrate under the second preset conditions.

[0076] Optionally, the second preset conditions include introducing a mixed gas formed by hydrogen with a flow rate of 1000 sccm / min - 3000 sccm / min and argon with a flow rate of 3000 sccm / min - 8000 sccm / min into the reaction chamber of the hydrogenation furnace equipment, the second preset temperature is 280°C - 350°C, and the hydrogenation time is 1 min - 5 min.

[0077] Among them, the preset hydrogenation process refers to making hydrogen atoms diffuse into the interior of the N-type silicon substrate 1 through a chemical reaction with molecular hydrogen to improve the passivation effect and reduce the attenuation rate.

[0078] Specifically, when hydrogenating the N-type silicon substrate 1, using the preset hydrogenation process, a mixed gas formed by hydrogen with a flow rate of 1000 sccm / min - 3000 sccm / min and argon with a flow rate of 3000 sccm / min - 8000 sccm / min is introduced into the reaction chamber of the hydrogenation furnace equipment. Under the second preset conditions of the second preset temperature of 280°C - 350°C and the hydrogenation time of 1 min - 5 min, the hydrogenation of the N-type silicon substrate 1 is achieved. During the hydrogenation process, by precisely controlling the temperature and accurately adjusting the gas flow rate, it is ensured that hydrogen atoms are evenly diffused into the interior of the N-type silicon substrate 1 to achieve an efficient passivation effect and reduce the attenuation rate.

[0079] It should be noted that in this hydrogenation process, argon is a dilution gas. Usually, the proportion of hydrogen is 1 / 3 and the proportion of argon is 2 / 3 to ensure a stable hydrogenation environment.

[0080] S260. Use the liquid nitrogen injection process to rapidly cool the N-type silicon substrate under the third preset condition.

[0081] Optionally, the third preset condition includes a cooling rate of 50°C / s - 100°C / s.

[0082] Among them, the liquid nitrogen injection process uses liquid nitrogen (boiling point of -196°C) as the cooling medium. Through the injection device, liquid nitrogen is sprayed onto the surface of the object to be cooled or frozen, and the cooling effect generated by its rapid evaporation is used to achieve temperature reduction.

[0083] Specifically, after passivating and hydrogenating the N-type silicon substrate 1, the preset passivation effect and attenuation rate have been achieved at this time. To ensure the passivation efficiency and attenuation rate achieved at this time and prevent hydrogen from overflowing, it is necessary to perform post-treatment on the N-type silicon substrate 1, that is, use the liquid nitrogen injection process to rapidly cool the N-type silicon substrate 1 under the third preset condition that the cooling rate of liquid nitrogen is 50°C / s - 100°C / s, so as to strengthen the hydrogenation effect and prevent hydrogen from overflowing.

[0084] S270. Screen-print and high-temperature sinter the N-type silicon substrate to form a first electrode in contact with the first doping layer on the back surface and a second electrode in contact with the front surface field layer on the front surface.

[0085] The technical solution of the embodiment of the present invention uses a preset activation process to passivate the N-type silicon substrate under the first preset condition; uses a preset hydrogenation process to hydrogenate the N-type silicon substrate under the second preset condition; uses the liquid nitrogen injection process to rapidly cool the N-type silicon substrate under the third preset condition. By using the above method, pre-activation treatment and hydrogenation cooling of the N-type silicon substrate are realized, the passivation rate is improved, and the attenuation rate is reduced.

[0086] Figure 5 This is the flowchart of the third preparation method of the TopCon battery provided by the embodiment of the present invention. This embodiment refines the preparation method of the TopCon battery in the above embodiment. For the content not detailed in this embodiment, reference can be made to the above embodiment, which will not be elaborated here. As Figure 3 and Figure 5 shown, the method includes:

[0087] S310. Provide an N-type silicon substrate.

[0088] Among them, the N-type silicon substrate 1 can be a single crystal silicon with a size of 182mm × 182mm, a thickness of 160um - 200um, a resistivity of 1.0Ω·cm - 1.2Ω·cm, and a minority carrier lifetime ≥ 2500us.

[0089] S320. Use the boron diffusion process to perform boron doping on the front surface to form a front surface field layer on the front surface.

[0090] Specifically, when forming the front surface field layer 31 on the front side, a boron diffusion process can be utilized. By introducing a certain flow rate of boron trichloride gas and oxygen into the reaction chamber of the boron diffusion process, under certain diffusion conditions, through the chemical reaction between boron trichloride, oxygen, and the N-type silicon substrate 1, boron diffuses into the N-type silicon substrate 1 on the front side, thereby forming a front surface field layer with a certain thickness on the front side.

[0091] It should be noted that since boron cannot be completely diffused into the N-type silicon substrate 1 during boron diffusion, there will be a certain residue on its surface. The residual boron will react chemically with the introduced oxygen to form a mask layer, namely a borosilicate glass layer (BSG). To form a textured surface structure in the subsequent texturing process, the formed borosilicate glass layer needs to be removed by methods such as acid etching, and only the front surface field layer 31 is retained.

[0092] S330. Utilize the texturing process to texture the front surface field layer and the back side to form a textured surface structure.

[0093] Among them, the texturing process can include but is not limited to processes such as trough texturing.

[0094] Specifically, during front side texturing, by adding a mixed solution formed by adding a certain volume of sodium hydroxide and a texturing additive into the reaction chamber of the texturing process, and carrying out the process at a texturing temperature of 75°C - 85°C for 10 min - 15 min, a pyramidal textured surface structure is simultaneously prepared on the front side and the back side to increase the surface area of the N-type silicon substrate 1 and improve the light absorption efficiency.

[0095] S340. Remove the textured surface structure on the back side to expose the N-type silicon substrate on the back side.

[0096] Specifically, after forming the textured surface structure on the back side, since the first tunneling oxide layer 21 and the first doping layer 22 need to be prepared on the back side subsequently, it is necessary to remove the textured surface structure on the back side to expose the N-type silicon substrate 1 on the back side, so as to prepare for the subsequent preparation of the first tunneling oxide layer 21 and the first doping layer 22. Among them, the methods for removing the textured surface structure on the back side can include but are not limited to wet chemical etching and alkali polishing, etc., and can be specifically determined according to the actual situation, and are not limited here.

[0097] S350. Utilize the deposition process to deposit and form a first tunneling oxide layer and a first intrinsic silicon layer on the surface of the N-type silicon substrate exposed on the back side.

[0098] Among them, the first intrinsic silicon layer is a silicon material layer with amorphous intrinsic semiconductor characteristics. An intrinsic semiconductor refers to those semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and its conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself.

[0099] Specifically, using a deposition process such as thermal oxidation, a first tunneling oxide layer 21 and a first intrinsic silicon layer are deposited on the exposed back surface. First, a certain flow rate of oxygen is introduced into the reaction chamber of the deposition process. Under the deposition conditions of a deposition temperature of 900°C - 950°C and a deposition time of 30 min - 40 min, a first tunneling oxide layer 21 with a thickness of 1.0 nm - 2.0 nm is formed on the back surface. After forming the first tunneling oxide layer 21, continue to use a deposition process such as low-pressure chemical vapor deposition. By introducing silane gas with a flow rate of 800 sccm / min - 1200 sccm / min into the reaction chamber of the deposition process, under the deposition conditions of a deposition temperature of 600°C - 650°C and a deposition time of 800 s - 1500 s, a first intrinsic silicon layer with a thickness of 70 nm - 130 nm is formed on the surfaces of the first tunneling oxide layer 21 on both the front and back surfaces away from the N-type silicon substrate 1 side.

[0100] S360. Use a phosphorus diffusion process to perform phosphorus doping on the first intrinsic silicon layer to form a first doped layer and a first mask layer on the back surface.

[0101] Among them, the phosphorus diffusion process is a process of forming a polysilicon layer by phosphorus diffusion on the N-type silicon substrate 1.

[0102] Specifically, after depositing and forming the first intrinsic silicon layer, phosphorus doping needs to be performed on the first intrinsic silicon layer. First, place the N-type silicon substrate 1 into the reaction chamber for phosphorus doping, and introduce a certain flow rate of phosphorus oxychloride and oxygen into the reaction chamber. Under the diffusion conditions of a diffusion time of 60 min - 90 min and a diffusion temperature of 600°C - 650°C, use the chemical reaction between phosphorus oxychloride, oxygen and the N-type silicon substrate 1 to make phosphorus diffuse into the first intrinsic silicon layer at high temperature to form a first doped layer 22. Since phosphorus cannot completely diffuse into the first intrinsic silicon layer during phosphorus diffusion, there will be a certain residue on its surface. The residual phosphorus will react with the introduced oxygen to generate a first mask layer with a certain thickness, that is, a phosphorus silicate glass layer (PSG). In this embodiment, the doping concentration of the first doped layer 22 is 1*10 20 cm -3 -5*10 20 cm -3 。

[0103] S370. Remove the first mask layer.

[0104] Specifically, the method for removing the first mask layer may include but is not limited to acid etching removal, etc. The solution for acid etching removal may include but is not limited to hydrofluoric acid, nitric acid, hydrochloric acid, etc.

[0105] S380. Use a preset process to passivate and hydrogenate the N-type silicon substrate.

[0106] S390. Prepare a first protective layer on the surface of the matte structure facing away from the N-type silicon substrate.

[0107] S400. Prepare a second protective layer on the surface of the first doped layer facing away from the N-type silicon substrate.

[0108] Among them, the second protective layer 5 includes an antireflection layer, which is used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of the battery, reduce surface recombination at the same time, increase the mobility of carriers, and improve the overall performance of the battery. Among them, the components of the antireflection layer may include, but are not limited to, silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon oxynitride. In this embodiment, the thickness of the second protective layer 5 can be 80 nm.

[0109] Specifically, after preparing the first protective layer 4 on the surface of the matte structure facing away from the N-type silicon substrate 1, it is necessary to prepare the second protective layer 5 on the surface of the first doped layer 22 facing away from the N-type silicon substrate 1. Using a deposition process, such as plasma-enhanced chemical vapor deposition (PECVD), at a temperature of 300 °C - 350 °C, using silane (SiH4), ammonia (NH3), and nitrogen (N2) as source gases, with a deposition time of 30 min - 45 min, deposit a silicon nitride antireflection layer with a thickness of 80 nm on the back surface to further improve the passivation and antireflection performance of the battery.

[0110] S410. Perform screen printing and high-temperature sintering on the N-type silicon substrate to form a first electrode in contact with the first doped layer on the back surface and a second electrode in contact with the front surface field layer on the front surface.

[0111] The technical solution of the embodiment of the present invention, by using the boron diffusion process, performs boron doping on the front surface to form a front surface field layer on the front surface; uses the texturing process to texture the front surface field layer and the back surface to form a matte structure; removes the matte structure on the back surface to expose the N-type silicon substrate on the back surface; uses the deposition process to deposit and form a first tunneling oxide layer and a first intrinsic silicon layer on the surface of the exposed N-type silicon substrate on the back surface; uses the phosphorus diffusion process to perform phosphorus doping on the first intrinsic silicon layer to form a first doped layer and a first mask layer on the back surface; removes the first mask layer; prepares a second protective layer on the surface of the first doped layer facing away from the N-type silicon substrate. Using the above method, the preparation of the TopCon battery is realized, and the passivation effect and conversion efficiency of the battery are improved.

[0112] In another specific embodiment, the present embodiment also provides a preparation method flow of a TopCon battery, and the specific flow includes:

[0113] S1. Prepare silicon wafers: This step belongs to the silicon wafer pretreatment process. Select N-type silicon wafers with a size of 182mm×182mm, a thickness of 180μm, a resistivity of about 1.1Ω·cm, and a minority carrier lifetime of 2500μs. The selection of this silicon wafer is based on a comprehensive consideration of battery performance. Specific resistivity and minority carrier lifetime help improve the overall performance of the battery.

[0114] S2. Surface texturing treatment: It belongs to the silicon wafer surface treatment process. By using a mixed solution formed by NaOH solution and texturing additives, the silicon wafer is treated at 80°C for 12 minutes to form a specific textured surface structure on both the front and back sides, increasing the surface area of the silicon wafer and improving the light absorption efficiency.

[0115] S3. Remove the back-side textured surface structure.

[0116] S4. Tunneling oxide layer deposition: Adopt the thermal oxidation method. Under a high-temperature environment of 900°C - 950°C, the silicon wafer is treated in an oxygen atmosphere for 30 - 40 minutes to form a tunneling oxide layer with a thickness of 1.5nm. This oxide layer thickness is optimized to effectively achieve passivated contacts.

[0117] S5. Doped layer deposition: Using low-pressure chemical vapor deposition (LPCVD) technology, at 620°C, with silane (SiH4) and phosphorus oxychloride (POCl3) as source gases, and a deposition time of 60 - 90 minutes, a doped polysilicon layer with a thickness of 100nm and a phosphorus doping concentration of 3×10 20 cm -3 is formed.

[0118] S6. Pre-activation treatment (Adv.Pre-Deg):

[0119] Equipment: Use a tube furnace with a precise temperature control system, which can accurately control temperature changes and meet the temperature requirements at different stages.

[0120] Environment: Conduct under the protection atmosphere of nitrogen (N2) to prevent the silicon wafer from being oxidized during the heating process.

[0121] First step: Put the battery with the prepared basic structure into the tube furnace, heat up to 50°C, and maintain at this temperature for 10 minutes. The purpose is to release lattice stress. During this process, nitrogen is continuously introduced, and the flow rate is controlled at 8000sccm / min to ensure an inert environment inside the tube furnace.

[0122] Second step: After the first step is completed, raise the temperature of the tube furnace to 75°C and maintain for 15 minutes to activate the impurities and defects in the N-type silicon matrix, maintain the inert atmosphere, and prevent the introduction of impurities.

[0123] S7. Hydrogenation treatment:

[0124] Equipment: A dedicated hydrogenation furnace is adopted, equipped with a gas flow control system and an accurate temperature control system.

[0125] Environment: It is carried out in a mixed gas environment of H2 / Ar. The volume ratio of H2 in the mixed gas is 1 / 3, and the volume ratio of argon is 2 / 3. Ar is used as a dilution gas to provide a stable reaction environment.

[0126] Operation: Put the battery after Adv.Pre-Deg treatment into the hydrogenation furnace, heat it up to 300 °C, introduce the H2 / Ar mixed gas, control the hydrogen gas flow at 2000 sccm / min, and control the argon gas flow at 6000 sccm / min, and carry out hydrogenation treatment for 2 minutes. During the hydrogenation process, through accurate temperature control and gas flow regulation, ensure that hydrogen atoms are evenly diffused into the battery interior to achieve an efficient passivation effect.

[0127] S8. Rapid cooling: Adopt the liquid nitrogen injection method, with a cooling rate of 80 °C / s. It belongs to the post-treatment process to prevent hydrogen from escaping and fix the hydrogenation effect.

[0128] S9. Deposit an aluminum oxide passivation layer with a thickness of 5 nm on the front side by ALD.

[0129] S10. Deposition of SiNx antireflection layer: Adopt plasma-enhanced chemical vapor deposition (PECVD) technology. At 330 °C, using silane (SiH4), ammonia (NH3) and nitrogen (N2) as source gases, the deposition time is 40 minutes. Deposit a SiNx antireflection layer with a thickness of 70 nm on the front side of the battery and 80 nm on the back side to further improve the passivation and antireflection performance of the battery.

[0130] S11. Screen printing and sintering: Use silver paste for screen printing to form an electrode pattern, and then sinter it at 750 - 850 °C for 5 - 10 minutes to form an electrode, completing the preparation of the TopCon battery.

[0131] Performance test: Conduct performance tests on the prepared TopCon battery. The results show that the passivation rate of interstitial iron (Fe + ) inside the battery increases from 30.3% to 89.1%, the passivation rate of dislocation defects increases from 21.92% to 46.18%, the strength of the Si-H bond increases significantly, the conversion efficiency of the battery increases by 0.2% in absolute value compared with the TopCon battery without Adv.Pre-Deg treatment, and after a certain period of light and temperature tests, the attenuation inhibition effects on LID and LeTID are obvious.

[0132] Based on the same inventive concept, continue to refer to Figure 3, the present invention provides a TopCon battery, which is prepared by using the above-mentioned preparation method of the TopCon battery and has the corresponding functional modules and beneficial effects of the implementation method.

[0133] It should be understood that various forms of processes shown above can be used, and steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0134] The above specific implementation manners do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A preparation method of a TopCon battery, characterized in that, Comprising: Providing an N-type silicon substrate; The N-type silicon substrate includes a front surface and a back surface; Preparing a front surface field layer and a textured structure on the front surface; Preparing a first tunneling oxide layer and a first doping layer on the back surface; Using a preset process to passivate and hydrogenate the N-type silicon substrate; Preparing a first protective layer on the surface of the textured structure facing away from the N-type silicon substrate; Performing screen printing and high-temperature sintering on the N-type silicon substrate to form a first electrode in contact with the first doping layer on the back surface and a second electrode in contact with the front surface field layer on the front surface.

2. The preparation method according to claim 1, characterized in that, Using a preset process to passivate and hydrogenate the N-type silicon substrate, including: Using a preset activation process to passivate the N-type silicon substrate under a first preset condition; Using a preset hydrogenation process to hydrogenate the N-type silicon substrate under a second preset condition; Using a liquid nitrogen injection process to rapidly cool the N-type silicon substrate under a third preset condition.

3. The preparation method according to claim 2, characterized in that, The second preset condition includes introducing a mixed gas formed by hydrogen with a flow rate of 1000 sccm / min - 3000 sccm / min and argon with a flow rate of 3000 sccm / min - 8000 sccm / min into the reaction chamber of the hydrogenation furnace equipment, a second preset temperature of 280°C - 350°C, and a hydrogenation time of 1 min - 5 min.

4. The preparation method according to claim 2, characterized in that, The third preset condition includes a cooling rate of 50°C / s - 100°C / s.

5. The preparation method according to claim 2, wherein The preset activation process includes a low-temperature relaxation process and a high-temperature activation process; Using a preset activation process to passivate the N-type silicon substrate under a first preset condition, including: Using a preset low-temperature relaxation process to release lattice stress of the N-type silicon substrate under a first preset low-temperature condition; Using the high-temperature activation process to activate defects of the N-type silicon substrate under a first preset high-temperature condition to passivate the N-type silicon substrate.

6. The preparation method according to claim 5, characterized in that, The first preset low-temperature condition includes introducing nitrogen with a flow rate of 5000 sccm / min - 10000 sccm / min into the tube furnace equipment, a first preset low temperature of 50°C - 70°C, and a first low-temperature time of 8 min - 15 min.

7. The preparation method according to claim 5, characterized in that, The first preset high-temperature condition includes a first preset high temperature of 75°C - 90°C and a first low-temperature time of 12 min - 20 min.

8. The preparation method according to claim 1, characterized in that Preparing a front surface field layer and a textured structure on the front surface, including: Using a boron diffusion process to perform boron doping on the front surface to form the front surface field layer on the front surface; Using a texturing process to texture the front surface field layer and the back surface to form the textured structure.

9. The preparation method according to claim 8, characterized in that, Preparing a first tunneling oxide layer and a first doping layer on the back surface, including: Removing the textured structure on the back surface to expose the N-type silicon substrate on the back surface; Using a deposition process to deposit and form the first tunneling oxide layer and a first intrinsic silicon layer on the surface of the N-type silicon substrate exposed on the back surface; Using a phosphorus diffusion process to perform phosphorus doping on the first intrinsic silicon layer to form the first doping layer and a first mask layer on the back surface; Removing the first mask layer.

10. The preparation method according to claim 1, characterized in that, After preparing the first protective layer on the surface of the matte structure facing away from the N-type silicon substrate, it further includes: Preparing a second protective layer on the surface of the first doped layer facing away from the N-type silicon substrate.

11. A TopCon battery, characterized in that, Prepared by the method for manufacturing a TopCon battery according to any one of claims 1-10.

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