Preparation method of half-piece BC battery

Abstract

The invention discloses a preparation method of a half-piece BC battery, which belongs to the technical field of BC battery manufacturing, and comprises the following steps: depositing and sequentially laminating a first tunneling oxide layer and a Poly layer on the back surface of a single crystal wafer; doping to form a first doped region; performing film opening patterning processing to form a protection area and a non-protection area; a kerf area is reserved between the two half-piece areas; etching the non-protection area to the substrate layer, and then performing low-temperature alkali polishing; depositing a second tunneling oxide layer and a Poly layer which are laminated in sequence; performing doping on the second tunneling oxide layer; performing laser drawing film opening on the left side and the right side of the non-protection area; performing laser film opening in the protection area; carrying out chain etching by using hydrofluoric acid; and after laser is used for local heating along the kerf area, the single crystal wafer obtained in the step S9 is divided into two half pieces along the kerf area through cooling induced thermal stress. And the cracks are promoted to expand by utilizing non-uniform distribution of thermal stress generated by laser irradiation, so that controllable crack track cutting is realized, and the manufacturing of the half BC battery is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of BC cell manufacturing, especially a preparation method for half-cell BC cells. Background Art

[0002] BC cells, whose full name is back contact cells, are a type of solar cell that transfers all the front electrode grid lines to the back, with the PN junction and metal contacts all located on the back of the cell, arranged in a finger-like pattern, thus reducing the shading of sunlight by the cell grid lines and improving the conversion efficiency of the cell. Given that the front of the BC cell structure has no grid lines, BC cells can eliminate the shading loss caused by the grid line electrodes, achieve the maximum utilization of incident photons, bring more effective power generation area, have high conversion efficiency, and are more aesthetically pleasing in appearance. With the development of the photovoltaic silicon wafer industry, the size of semiconductor silicon wafers has been continuously increasing: for upstream silicon wafer manufacturers, the increase in silicon wafer size can reduce the three major costs of silicon wafer enterprises: silicon materials, crystal pulling, and slicing. With the same amount of silicon materials, when the diameter of the silicon rod becomes larger, the number of crystal pulling times can be reduced, energy consumption can be reduced, and thus the crystal pulling cost can be reduced. At the same time, large-sized silicon wafers can reduce the number of slicing times, reduce the slicing cost and the cost per watt of the silicon wafer; for midstream and downstream cell and module manufacturers, the increase in silicon wafer size can speed up the production speed from silicon wafers to modules, which will also bring about a reduction in production operation costs such as labor and hydropower, spread the non-silicon costs in the cell module production link, and with the increase in the size of a single silicon wafer, the number of cell wafers in a single module will decrease accordingly, the number of silicon wafers will decrease correspondingly, the effective light-emitting area of the module will increase, which will bring an increase in conversion efficiency and power, and the cost per watt will also decrease; for power station customers, under the same power station scale, the larger the module size, the fewer the required number of modules, thus reducing the corresponding costs of brackets, busbar boxes, cables, and transportation and installation costs, etc. At the same time, large-sized silicon wafers will, to a certain extent, improve the power and quality of the module, while reducing the power station cost and increasing the power generation of the power station.

[0003] During production, it was found that if large-sized cell wafers were directly encapsulated as modules as a whole, the encapsulation loss and reliability would be affected. Technicians tried to cut them into half-cells and then encapsulate them. It was found during the trial production that: before cutting, the silicon wafer was completely covered by the passivation film layer, which would not affect the reliability of the module after encapsulation; but after cutting, the cut surface of the C-Si substrate was exposed to the air, as Figure 1 shown. In this way, for the cell wafers with the exposed side parts untreated, due to the attachment of water vapor containing impurities on the silicon surface and the formation of dangling bonds caused by the fracture of the crystal silicon lattice, the photoelectric conversion efficiency of the cell is reduced, and the reliability of the module encapsulation will also be greatly affected. Therefore, a preparation method for half-cell BC cells needs to be designed. Summary of the Invention

[0004] In view of at least one of the above technical problems, the present invention provides a method for preparing a half - piece BC cell, which uses the uneven distribution of thermal stress generated by laser irradiation to promote crack propagation and separates brittle materials by a cutting technique. When the silicon wafer is irradiated by a laser, due to the high energy at the laser position and low energy elsewhere, an uneven temperature field is generated in the workpiece. The uneven temperature field generates a temperature gradient, and the temperature gradient induces the generation of thermal stress. When the thermal stress reaches the fracture strength of the material, the material will fracture, thereby achieving the cutting of a controllable crack trajectory. Then, by using ALD to passivate Al2O3 to passivate and cover the cut surface C - Si substrate after cutting, the loss during the cutting and packaging of the component end can be effectively reduced, the cutting process of the component can be saved, and the cost can be reduced. The specific technical solution is as follows: A method for preparing a half - piece BC cell, comprising the following steps: S1, double - side polish a single - crystal wafer; S2, deposit a first tunneling oxide layer and a Poly layer Ⅰ in sequence on the back of the single - crystal wafer in a stacked manner; S3, dope the first tunneling oxide layer to form a first doping region with a different polarity from the single - crystal wafer; S4, perform opening - film patterning to form two left - and - right half - piece regions. One side of each half - piece region is a protection region, and the other side is a non - protection region; a cutting - slit region is left between the two half - piece regions; S5, etch the non - protection region to the single - crystal wafer and then perform low - temperature alkaline polishing; S6, deposit a second tunneling oxide layer and a Poly layer in sequence in a stacked manner; S7, dope the second tunneling oxide layer to form a second doping region with a different polarity from the first tunneling oxide layer; S8, perform laser drawing and opening - film on both sides of the non - protection region; perform laser opening - film on the protection region; S9, perform chain etching with hydrofluoric acid; remove the second tunneling oxide layer and the Poly layer deposited in step S6 in the protection region with a strong corrosive acid; S10, after locally heating the single - crystal wafer along the cutting - slit region by laser, induce thermal stress through cooling to divide the single - crystal wafer into two half - pieces along the cutting - slit region.

[0005] In some embodiments of the present disclosure, in step S3, the single - crystal wafer is a P - type single - crystal wafer or an N - type single - crystal wafer. The first doping region is formed by high - temperature boron doping or phosphorus doping deposition to form a boron - doped or phosphorus - doped amorphous silicon layer and an oxide layer. The thickness of the first doping region is 10 - 20 nm, and the thickness of the oxide layer is 2 - 20 nm; when it is an N - type single - crystal wafer, the first doping region in step S3 is a P + poly layer; when it is a P - type single - crystal wafer, the doping region in step S3 is an N + poly layer.

[0006] In some embodiments of the present disclosure, in step S4, a green laser or an ultraviolet laser is used for film opening, and the film opening width is 80 - 300 um; the laser power is 20 - 80 W, the repetition frequency is 100 - 2000 KHZ, and the speed is 10000 - 60000 mm / min.

[0007] In some embodiments of the present disclosure, in step S5, the etching is carried out by chain etching with hydrofluoric acid to remove the first doped region in the non - protected area. All the film layers will be removed by strong acid corrosion until the single crystal wafer.

[0008] In some embodiments of the present disclosure, when the film layer is removed by strong acid corrosion, 0.5 - 2 um thickness of the single crystal wafer is removed by corrosion.

[0009] In some embodiments of the present disclosure, in step S5, the temperature of the low - temperature alkaline polishing is 65 - 80 °C.

[0010] In some embodiments of the present disclosure, in step S6, the thickness of the second tunneling oxide layer is 0.8 - 3 nm.

[0011] In some embodiments of the present disclosure, in step S8, a green laser or an ultraviolet laser is used for film opening, and the film opening width is 80 - 300 um; the laser power is 20 - 60 W, the repetition frequency is 100 - 2000 KHZ, and the speed is 10000 - 60000 mm / min.

[0012] In some embodiments of the present disclosure, when laser heating is carried out in step S10, the temperature is controlled at 150 - 250 °C; the spot width is 30 um - 50 um; the depth is 60 um - 90 um; the laser power is 15 - 25 W; the frequency is 30 kHz - 45 kHz.

[0013] Compared with the prior art, the preparation method of the above - mentioned half - piece BC cell has the following beneficial effects: In this technical solution, the uneven distribution of thermal stress generated by laser irradiation is utilized to promote crack propagation, so that an uneven temperature field is generated in the single crystal wafer. The uneven temperature field will generate a temperature gradient, and the temperature gradient induces the generation of thermal stress, thereby realizing the cutting of a controllable crack trajectory and completing the manufacture of the half - piece BC cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the state to be separated in the structure of the present invention; Explanation of reference numerals in the figure: 1. Single crystal wafer; 2. First tunneling oxide layer; 3. Poly layer I; 4. Slit area; 5. Second tunneling oxide layer; 6. Poly layer II. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] In order to better understand the purpose, structure and function of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below.

[0016] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The terms "including" and "provided with" and any variations thereof in this application are in an open-ended writing and are intended to cover non-exclusive inclusion.

[0017] The serial numbers assigned to the components herein are only used to distinguish the objects described and do not have any sequential or technical meaning. And the "connection" mentioned in this disclosure, unless otherwise specifically described, includes both direct and indirect "connections". In the description of this application, it should be understood that the orientation terms such as "front" and "back" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. Figure 1 The upper part is the front and the lower part is the back, which is only for the convenience of description and does not indicate or imply that the device or unit referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application.

[0018] As shown in the attached drawings Figure 1 This embodiment discloses a preparation method of a half-piece BC cell, including the following steps: S1, Select a P or N-type single crystal wafer and perform double-sided polishing on the front and back of the single crystal wafer 1; S2, Then form a first tunneling oxide layer 2 on the back of the single crystal wafer in the LPCVD manner, and then form a Poly layer Ⅰ 3; S3, After forming the first tunneling oxide layer 2 on the back of the single crystal wafer 1, form a boron-doped or phosphorus-doped amorphous silicon layer and an oxide layer by high-temperature boron doping or phosphorus doping deposition. The thickness of the first doping region is 10-20 nm, and the thickness of the oxide layer is 2-20 nm; when it is an N-type single crystal wafer, the first doping region in step S3 is a P+poly layer; when it is a P-type single crystal wafer, the doping region in step S3 is an N+poly layer; S4, Perform film opening and patterning on the oxide layer to form two left and right half-piece regions. One side of each half-piece region is a protection region, and the other side is a non-protection region; a cutting seam region 4 is left between the two half-piece regions; the pattern is divided into two upper and lower patterns, and they are not connected in the middle. Use a green skin or ultraviolet laser to perform film opening, where the width of the film opening is 80-300 um; the laser power is 20-80 W, the repetition frequency is 100-2000 KHZ, and the speed is 10000-60000 mm / min.

[0019] S5. After the film is removed, the silicon wafer is etched by hydrofluoric acid in a chain reaction to remove the boron-doped or phosphorus-doped amorphous silicon in the unprotected area of the silicon wafer. After laser film removal, the film layer in the unprotected area will be removed by strong acid corrosion until the single crystal wafer. Further, the silicon wafer can be etched to a thickness of 0.5 - 2 μm. The single crystal wafer is subjected to low-temperature alkaline polishing in an alkali + additive tank at a temperature of 65 - 80 °C. Since there is an oxide layer formed during the high-temperature process on the back side, it can withstand the low-temperature alkaline texturing. At the same time, the unprotected tunneling oxide and Poly layer I3 on the back side of the silicon wafer are completely cleaned using an HF tank.

[0020] S6. Then, a second tunneling oxide layer 5 and Poly layer II 6 are formed on the back side of the silicon wafer by LPCVD. The thickness of the second tunneling oxide layer 5 is 0.8 - 3 nm. S7. A boron-doped or phosphorus-doped amorphous silicon layer and an oxide layer are formed by high-temperature boron doping or phosphorus doping deposition to form a second doping region with a different polarity from the first tunneling oxide layer 2. Thus, a boron-doped amorphous silicon region and a phosphorus-doped amorphous silicon region are respectively formed, and a cross-shaped back emitter structure is formed by means of patterned doping. S8. A second local laser scribing film removal is performed on the silicon wafer with each layer deposited on the back side to form a patterned structure of protected and unprotected regions. Since the laser power and frequency are low this time, only the second tunneling oxide layer 5 and Poly layer II 6 in the protected area of the first film removal are removed, without affecting the first tunneling oxide layer 2 and Poly layer I3. And the width of the film removal pattern this time needs to be 50 - 200 nm larger than the width of the first film removal pattern. Therefore, a certain width will be left on both sides of the regions of the two film removals as unprotected areas. The pattern is divided into two upper and lower patterns, which are not connected in the middle. A green skin or ultraviolet laser is used for film removal, with a laser power of 20 - 60 W, a repetition frequency of 100 - 2000 KHZ, and a speed of 10000 - 60000 mm / min. S9. After film removal, chain etching is performed with hydrofluoric acid; the second tunneling oxide layer 5 and Poly layer II 6 deposited in the protected area in step S6 are removed with strong corrosive acid; the boron-doped or phosphorus-doped amorphous silicon in the unprotected area of the silicon wafer. After laser film removal, the patterned film removal part is the unprotected area, and the second tunneling oxide layer 5 and Poly layer II 6 in the protected area of the first film removal and the film layer in the unprotected area will be removed by strong acid corrosion; the single crystal wafer 1 will not be corroded this time. S10. Use a laser to locally and rapidly heat the middle slit area 4 of the silicon wafer. The subsequent supporting cooling technology generates a non-uniform temperature field. This temperature field will generate a temperature gradient on the surface of the single crystal wafer 1, thereby inducing the generation of thermal stress, which will cause the single crystal wafer 1 to break. The break will steadily expand along with the moving track of the laser and subsequent cooling, so that the single crystal wafer 1 is divided into two half wafers. The temperature is controlled at 150 - 250 °C, the spot width is 30 - 50 μm, the depth is 60 - 90 μm, the laser power is 15 - 25 W, and the frequency is 30 - 45 kHz.

[0021] After that, in this embodiment, the single crystal wafer 1 cut into half wafers is subjected to front surface texturing using a trough type machine tool. While forming a pyramid-shaped textured surface on the front surface, the cutting surface can also be used to remove the damaged layer and form a textured surface structure. Use an ALD passivation device to deposit double-sided Al2O3 to form a front surface Al2O3 layer and a back surface Al2O3 layer, so that the laser cutting surface can also be effectively coated with an Al2O3 layer with a thickness of about 2 - 5 nm. Use a PECVD device to deposit and form at least one of the compositions of front surface SixNy, SiO2, and SiO N layers with a thickness of 55 - 110 nm, and deposit and form a back surface SiNx layer with a thickness of 75 - 110 nm. The coated cell wafers are used to prepare the metal electrodes for the back surface P region and N region by screen printing and sintering. By using ALD passivated Al2O3, the cut c-Si substrate of the cutting surface is passivated and covered, which will effectively reduce the loss during the cutting and encapsulation of the module end, save the module cutting process, and reduce costs.

[0022] This technical solution realizes the cutting of a controllable crack trajectory by using the non-uniform distribution of thermal stress generated by laser irradiation to promote crack propagation, causing the single crystal wafer 1 to generate a non-uniform temperature field. The non-uniform temperature field will generate a temperature gradient, and the temperature gradient induces the generation of thermal stress, thereby completing the manufacturing of a half-cell BC battery. It can be understood that the above description is only for explaining the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered within the disclosure scope of the present application.

Claims

1. A preparation method of a half-piece BC cell, characterized in that, It includes the following steps: S1, double-side polish a single crystal wafer (1); S2, deposit on the back of the single crystal wafer (1), and stack a first tunneling oxide layer (2) and a Poly layer I (3) in sequence; S3, dope the first tunneling oxide layer (2) to form a first doped region with a polarity different from that of the single crystal wafer (1); S4, perform film opening patterning to form two left and right half wafers. One side of each half wafer is a protection area, and the other side is a non-protection area; a cutting slot area (4) is left between the two half wafers; S5, etch the non-protection area to the single crystal wafer (1), and perform low-temperature alkaline polish; S6, deposit and stack a second tunneling oxide layer (5) and a Poly layer II (6) in sequence; S7, dope the second tunneling oxide layer (5) to form a second doped region with a polarity different from that of the first tunneling oxide layer (2); S8, perform laser scribing film opening on the left and right sides of the non-protection area; perform laser film opening on the protection area; S9, perform chain etching with hydrofluoric acid; use a strong etching acid to remove the second tunneling oxide layer (5) and the Poly layer II (6) deposited in step S6 in the protection area; S10, after locally heating the single crystal wafer (1) along the cutting slot area (4) by laser, divide the single crystal wafer (1) into two half wafers along the cutting slot area (4) by inducing thermal stress through cooling.

2. The preparation method of the half BC cell according to claim 1, wherein In step S3, the single crystal wafer (1) is a P-type single crystal wafer or an N-type single crystal wafer. The first doped region is formed by depositing a boron-doped or phosphorus-doped amorphous silicon layer and an oxide layer through high-temperature boron doping or phosphorus doping. The thickness of the first doped region is 10 - 20 nm, and the thickness of the oxide layer is 2 - 20 nm; when it is an N-type single crystal wafer, the first doped region in step S3 is a P+poly layer; when it is a P-type single crystal wafer, the doped region in step S3 is an N+poly layer.

3. The preparation method of the half BC cell according to claim 1, characterized in that, In step S4, a green laser or an ultraviolet laser is used for film opening. The film opening width is 80 - 300 um; the laser power is 20 - 80 W, the repetition frequency is 100 - 2000 KHZ, and the speed is 10000 - 60000 mm / min.

4. The manufacturing method of the half BC cell according to claim 1, characterized in that, In step S5, the etching is chain etching with hydrofluoric acid to remove the first doped region in the non-protection area. All film layers will be removed by strong acid corrosion until the single crystal wafer.

5. The preparation method of the half BC cell according to claim 4, wherein, When all film layers are removed by strong acid corrosion, 0.5 - 2 um thickness of the single crystal wafer is removed by corrosion.

6. The preparation method of the half BC cell according to claim 1, characterized in that, In step S5, the temperature of the low-temperature alkaline polish is 65 - 80 °C.

7. The preparation method of the half BC cell according to claim 1, characterized in that, The thickness of the second tunneling oxide layer (5) in step S6 is 0.8 - 3 nm.

8. The preparation method of the half BC cell according to claim 1, characterized in that, In step S8, a green laser or an ultraviolet laser is used for film opening. The film opening width is 80 - 300 um; the laser power is 20 - 60 W, the repetition frequency is 100 - 2000 KHZ, and the speed is 10000 - 60000 mm / min.

9. The preparation method of the half BC cell according to claim 1, characterized in that When laser heating in step S10, the temperature is controlled at 150 - 250 °C; the spot width is 30 um - 50 um; the depth is 60 um - 90 um; the laser power of the laser is 15 - 25 W; the frequency is 30 kHz - 45 kHz.

10. The preparation method of the half BC cell according to claim 1, wherein, In step S10, passivate and cover the cross-section of the half wafer.

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