System and method for testing clock synchronization of distributed control system

Abstract

The invention relates to the technical field of distributed control systems, in particular to a system and method for testing clock synchronism of a distributed control system, and the system comprises a clock server which is used for providing reference time; the multi-channel data acquisition unit is used for acquiring data information of transmission channels corresponding to a plurality of tested devices in the distributed control system; and the test board is used for sending a test instruction to each tested device in different test modes, receiving and processing the data information, acquired by the multi-channel data acquisition unit, of the transmission channels corresponding to the plurality of tested devices in the distributed control system, and calculating the time synchronization precision, the time keeping precision and the channel transmission delay of the plurality of devices in the distributed control system. According to the invention, comprehensive, accurate and efficient measurement and evaluation can be carried out on the clock time keeping precision, the time setting precision and the transmission time delay compensation precision of multiple devices of the distributed control system, the monitoring level of the clock synchronization performance of the distributed control system is effectively improved, and stable and efficient operation of the system is facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of distributed control systems, and in particular to a system and method for testing clock synchronization of distributed control systems. Background Art

[0002] Distributed control systems (DCS) are widely used in many industrial fields such as power, chemical industry, and petroleum. The clock synchronization between the internal devices directly affects the key performance indicators of the system, such as the control accuracy, event sequence recording accuracy, and fault diagnosis effectiveness. In actual operation, due to the large scale of the system, the wide distribution of equipment, and the complex communication network, ensuring the accurate synchronization of the clocks between channels faces many challenges.

[0003] In the related art, the measurement of clock accuracy is mostly carried out on a certain aspect, and the measurement objects are relatively small, and most of them are one-to-one clock accuracy measurements between a reference time and a device or between devices.

[0004] However, the clock synchronization test methods in related technologies are mostly carried out on a certain aspect, and often have defects such as insufficient test coverage, limited accuracy, and difficulty in comprehensive evaluation of multiple channels at the same time. They cannot meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and it is difficult to ensure the stability and reliability of the clock synchronization system in the distributed control system, which needs to be solved urgently. Summary of the invention

[0005] The present application provides a system and method for testing the clock synchronization of a distributed control system, so as to solve the problems that the clock synchronization test methods in the related art are mostly carried out on a certain aspect, often have defects such as insufficient test coverage, limited accuracy and difficulty in comprehensively evaluating multiple channels at the same time, cannot meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and are difficult to ensure the stability and reliability of the operation of the clock synchronization system in the distributed control system.

[0006] The first aspect of the present application provides a system for testing the clock synchronization of a distributed control system, comprising: a clock server for providing a timing reference time; a multi-channel data acquisition unit for collecting data information of transmission channels corresponding to multiple devices under test in the distributed control system; a test bench for selecting at least one master timing terminal from the multiple devices under test when the test mode is a multi-channel timing accuracy measurement mode, and receiving clock deviation values ​​between multiple slave timing terminals other than the at least one master timing terminal and the master timing terminal collected by the multi-channel data acquisition unit, so as to calculate the timing accuracy of the multiple slave timing terminals according to the clock deviation values, wherein the clock deviation values ​​are determined by comparing the multiple slave timing terminals with the timing reference time.

[0007] Optionally, in an embodiment of the present application, the test bench is further configured to calculate the time synchronization optimized clock frequencies of the multiple slave time synchronization terminals according to the clock deviation values, so as to correct the time synchronization accuracy of the multiple devices under test according to the time synchronization optimized clock frequencies.

[0008] Optionally, in an embodiment of the present application, when the test mode is the multi-channel clock timekeeping accuracy measurement mode, the test bench is further configured to send the timekeeping reference time to the multiple devices under test, and receive the counter start times of the multiple devices under test collected by the multi-channel data acquisition unit, so as to calculate the timekeeping deviation data of the multiple devices under test according to the timekeeping reference time, the counter start times and the test duration, and determine the timekeeping accuracy of the multiple devices under test according to the timekeeping deviation data, wherein the timekeeping reference time is provided by the clock server.

[0009] Optionally, in an embodiment of the present application, the test bench is further configured to calculate the timekeeping optimized clock frequencies of the multiple devices under test according to the timekeeping deviation data, so as to adjust the clock frequencies of the multiple devices under test to make the timekeeping deviation rates of the multiple devices under test converge to the target range of timekeeping accuracy according to the timekeeping optimized clock frequencies.

[0010] Optionally, in an embodiment of the present application, when the test mode is the multi-channel transmission delay measurement mode, the test bench is further configured to select at least one sending terminal and at least one receiving terminal from the multiple devices under test, and calculate the one-way channel transmission delay between the at least one sending terminal and the at least one receiving terminal according to the data packet sending time of the at least one sending terminal, the data packet receiving time of the at least one receiving terminal, and the feedback data packet receiving time of the at least one sending terminal.

[0011] Optionally, in an embodiment of the present application, the test bench is further configured to adjust the transmission delay compensation parameters of the distributed control system according to the one-way channel transmission delay to meet the preset transmission delay requirements of the distributed control system.

[0012] The second aspect of the present application provides a method for testing the clock synchronization of a distributed control system, using the system for testing the clock synchronization of a distributed control system as described above. Wherein, the method includes the following steps: obtaining the time synchronization reference time and / or the timekeeping reference time and / or the data packet sending time, the data packet receiving time, and the feedback data packet receiving time; based on the time synchronization reference time, determining the clock deviation value data of multiple devices under test in the distributed control system, and / or based on the timekeeping reference time, determining the timekeeping deviation data of multiple devices under test in the distributed control system, and / or based on the data packet sending time, the data packet receiving time, and the feedback data packet receiving time, determining the channel transmission delay data of the transmission channels corresponding to multiple devices under test in the distributed control system; calculating the time synchronization accuracy of multiple devices under test in the distributed control system according to the clock deviation value data, and / or calculating the timekeeping accuracy of multiple devices under test in the distributed control system according to the timekeeping deviation data, and / or calculating the one-way channel transmission delay of the transmission channels corresponding to multiple devices under test in the distributed control system according to the channel transmission delay data.

[0013] Optionally, in an embodiment of the present application, it further includes: calculating the time synchronization optimized clock frequency of multiple devices under test in the distributed control system according to the clock deviation value data, so as to correct the time synchronization accuracy of the multiple devices under test according to the optimized clock frequency; calculating the timekeeping optimized clock frequency of multiple devices under test in the distributed control system according to the timekeeping deviation data, so as to adjust the clock frequencies of the multiple devices under test to the timekeeping deviation rate of the multiple devices under test converging to the target range of timekeeping accuracy according to the timekeeping optimized clock frequency; adjusting the transmission delay compensation parameter of the distributed control system according to the one-way channel transmission delay to meet the preset transmission delay requirement of the distributed control system.

[0014] The third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the method for testing the clock synchronization of a distributed control system as described in the above embodiments.

[0015] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program, and when the program is executed by a processor, it implements the method for testing the clock synchronization of a distributed control system as described above.

[0016] The fifth aspect of the present application provides a computer program product, including a computer program, and when the computer program is executed, it is used to implement the method for testing the clock synchronization of a distributed control system as described above.

[0017] Embodiments of the present application can form a system for testing the clock synchronization of a distributed control system through a clock server, a multi-channel data acquisition unit, a test bench, etc. Thus, it realizes comprehensive, accurate, and efficient measurement and evaluation of the clock holding accuracy, time synchronization accuracy, and transmission delay compensation accuracy of multiple devices in the distributed control system, thereby effectively improving the monitoring level of the clock synchronization performance of the distributed control system and ensuring the reliability and stability of the overall operation of the distributed control system. Thereby, it solves the problems in the related art that most clock synchronization testing methods focus on a certain aspect, often having defects such as insufficient test coverage, limited accuracy, and difficulty in comprehensively evaluating multiple channels simultaneously, being unable to meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and being difficult to ensure the stability and reliability of the clock synchronization system operation in the distributed control system.

[0018] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present application. Brief Description of the Drawings

[0019] The above and / or additional aspects and advantages of the present application will become apparent and be easily understood from the following description of the embodiments in conjunction with the drawings, wherein:

[0020] Figure 1 Schematic structural diagram of a system for testing the clock synchronization of a distributed control system according to an embodiment of the present application

[0021] Figure 2 Schematic architecture diagram of a system for testing the clock synchronization of a distributed control system according to an embodiment of the present application;

[0022] Figure 3 Flowchart of measuring the multi-channel clock holding accuracy according to an embodiment of the present application;

[0023] Figure 4 Flowchart of measuring the multi-channel clock holding accuracy according to an embodiment of the present application;

[0024] Figure 5 Flowchart of measuring the multi-channel transmission delay according to an embodiment of the present application;

[0025] Figure 6 Flowchart of a method for testing the clock synchronization of a distributed control system according to an embodiment of the present application;

[0026] Figure 7 Schematic structural diagram of an electronic device according to an embodiment of the present application.

[0027] Reference Signs:

[0028] System for testing clock synchronization of a distributed control system: 100 - clock server, 200 - multi-channel data acquisition unit, and 300 - test bench; 701 - memory, 702 - processor, and 703 - communication interface. Detailed implementation manners

[0029] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as a limitation of the present application.

[0030] The system and method for testing clock synchronization of a distributed control system according to an embodiment of the present application will be described below with reference to the accompanying drawings. In view of the deficiencies in the prior art clock synchronization test methods, such as being often carried out for only one aspect, having insufficient test coverage, limited accuracy, and difficulty in comprehensively evaluating multiple channels simultaneously, being unable to meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and being difficult to ensure the stability and reliability of the clock synchronization system operation in the distributed control system, the present application provides a system for testing clock synchronization of a distributed control system. In this method, a system for testing clock synchronization of a distributed control system can be composed of a clock server, a multi-channel data acquisition unit, and a test bench, etc. Thus, comprehensive, accurate, and efficient measurement and evaluation of the clock keeping accuracy, time synchronization accuracy, and transmission delay compensation accuracy of multiple devices in the distributed control system can be achieved, thereby effectively improving the monitoring level of the clock synchronization performance of the distributed control system and ensuring the reliability and stability of the overall operation of the distributed control system. Thereby, the problems in the prior art clock synchronization test methods, such as being often carried out for only one aspect, having insufficient test coverage, limited accuracy, and difficulty in comprehensively evaluating multiple channels simultaneously, being unable to meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and being difficult to ensure the stability and reliability of the clock synchronization system operation in the distributed control system, are solved.

[0031] Specifically, Figure 1 FIG. is a schematic structural diagram of a system for testing clock synchronization of a distributed control system provided by an embodiment of the present application.

[0032] As Figure 1 shown, the system 10 for testing clock synchronization of a distributed control system includes:

[0033] A clock server 100 for providing a time synchronization reference time.

[0034] In some embodiments, the clock synchronization among devices within the distributed control system directly affects key performance indicators such as the control accuracy of the system, the accuracy of event sequence recording, and the effectiveness of fault diagnosis. To have a corresponding reference for measuring the clock synchronization of devices in the distributed control system, this application can set up a clock server 100 to provide multiple reference times, such as the time synchronization reference time.

[0035] Furthermore, as the provider of the reference time for the entire test system, to ensure that the clock server 100 has extremely high frequency stability and accuracy, in the embodiments of this application, the clock server 100 can but is not limited to adopt high-precision clock servers such as atomic clocks, high-precision GPS timing modules, or Beidou satellite timing modules, so as to continuously output accurate clock signals and provide a unified time reference for each device under test.

[0036] It should be noted that the high-precision clock server 100 in the embodiments of this application can, in addition to providing the time synchronization reference time, also provide other reference times for clock synchronization measurement, such as the timekeeping reference time, other reference times, or the reference time for clock synchronization measurement. Among them, the time synchronization reference time can be understood here as the reference time used when measuring the time synchronization among multiple devices in the distributed control system. The timekeeping reference time can be understood here as the reference time used when measuring the timekeeping performance of multiple devices in the distributed control system.

[0037] The embodiments of this application can set up a certain high-precision clock server 100 in the system for testing the clock synchronization of the distributed control system, which can provide high-precision reference times for various clock synchronization measurements, thereby improving the accuracy of the clock synchronization measurement results.

[0038] The multi-channel data acquisition unit 200 is used to acquire the data information of the transmission channels corresponding to multiple devices under test in the distributed control system.

[0039] In some embodiments, during the actual operation of the distributed control system, due to the large scale and wide distribution of the distributed control system, the communication networks among devices will cross-connect with each other, which is extremely complex.

[0040] Based on this, to facilitate the acquisition of data information related to the time of each device, the embodiments of this application can design a multi-channel data acquisition unit 200 in the system for testing the clock synchronization of the distributed control system. Through this multi-channel data acquisition unit 200, the data information of the transmission channels corresponding to multiple devices under test in the distributed control system can be acquired.

[0041] Specifically, the multi-channel data acquisition unit 200 in the embodiments of the present application has multiple independent data acquisition channels, and can simultaneously connect to and acquire clock-related data of multiple devices under test (devices under test), such as timestamps and frequency information of clock signals, and transmit the acquired data to the test bench 300 in real time through a high-speed data transmission link. Among them, the sampling frequency and resolution adopted by the multi-channel acquisition unit when acquiring this data can be flexibly adjusted by professionals in the field according to test requirements to meet the test requirements of different accuracy levels, and the embodiments of the present application do not make specific limitations.

[0042] In addition, the devices under test mentioned in the embodiments of the present application are the devices located at key positions of each channel of the distributed control system. These devices can receive the clock signals of the high-precision clock server 100 and cooperate with other devices under test during the test. Each device under test is equipped with a high-precision clock counter and a data communication module. On the one hand, it can accurately record the deviation information between its own clock and the reference clock, and on the other hand, it can interact with other devices under test for clock synchronization signals and data transmission, so as to test the time synchronization accuracy and transmission delay compensation accuracy.

[0043] The embodiments of the present application can set the multi-channel data acquisition unit 200 to acquire clock-related data of the transmission channels corresponding to multiple devices in the distributed control system. Thus, while ensuring the interconnection between devices, the clock-related data of each device can be quickly and accurately obtained, providing data support for various clock synchronization tests of each device.

[0044] The test bench 300 is used to select at least one master time synchronization terminal from multiple devices under test and receive the clock deviation values between multiple slave time synchronization terminals and the master time synchronization terminal except for at least one master time synchronization terminal collected by the multi-channel data acquisition unit 200 when the test mode is the multi-channel time synchronization accuracy measurement mode, so as to calculate the time synchronization accuracy of multiple slave time synchronization terminals according to the clock deviation values. Among them, the clock deviation values are determined by the comparison results of multiple slave time synchronization terminals and the time reference.

[0045] In the actual implementation process, when measuring the clock synchronization between multiple devices, it is necessary to perform certain processing and analysis on various reference times and the data information collected by the multi-channel data acquisition unit 200. Therefore, the present application can also set up a test bench 300 to undertake the management and control tasks of the test process, including but not limited to generating test plans, sending test instructions to each device under test, receiving and processing the data collected by the multi-channel data acquisition unit 200, and using the built-in data analysis algorithm to deeply analyze and comprehensively evaluate the test results, and finally generate a detailed test report and other tasks. In addition, the test bench 300 in the embodiment of the present application is also equipped with a powerful computing and processing ability, a large-capacity storage device, and rich communication interfaces, which can ensure efficient data interaction with other components. Figure 2 FIG. is a schematic diagram of the architecture of a system for testing the clock synchronization of a distributed control system according to an embodiment of the present application. The relationship among the clock server 100, the test bench 300, and multiple field control stations (devices) is as Figure 2 shown.

[0046] For example, in the case where the test mode is the multi-channel pair-wise accuracy measurement mode, that is, when it is necessary to measure the time synchronization between multiple devices in the distributed control system, the embodiment of the present application can use the test bench 300 to generate a certain test plan. Figure 3 FIG. is a flowchart of multi-channel clock holdover accuracy measurement according to an embodiment of the present application. As Figure 3 shown, the process can but is not limited to be expressed as follows:

[0047] The specific plan and the actual implementation process can but is not limited to be expressed as follows:

[0048] Step 301, the test bench 300 can randomly select one device under test from multiple devices under test as the master time synchronization terminal, and the remaining devices under test as slave time synchronization terminals.

[0049] Among them, the selection of the master time synchronization terminal is not only based on randomness, but also can be comprehensively evaluated in combination with the historical clock stability and communication link quality of the device. For example, the test bench 300 can preferentially select the device with the lowest deviation rate and the smallest communication delay as the master terminal by real-time monitoring the clock deviation records and network delay data of each device. If the master terminal has an abnormality (such as communication interruption or clock deviation exceeding the threshold) during the test, the test bench 300 automatically triggers the master-slave switching mechanism to select a standby master terminal to continue the test, ensuring the continuity and reliability of the test.

[0050] Furthermore, the test bench 300 can also perform initialization and calibration on the master and slave terminals. For example, when the master and slave terminals are initialized, the test bench 300 calibrates the initial clock deviation through two-way timestamp exchange. The master terminal sends a calibration request to the slave terminal, and the slave terminal returns its local timestamp. The master terminal calculates the round-trip delay and corrects the initial deviation. The formula can be expressed but is not limited to the following:

[0051]

[0052] where ΔT int is the round-trip delay between the master terminal and the slave terminal, T send is the time when the master terminal sends, and T reply is the time when the slave terminal replies.

[0053] Step 302, the master time synchronization terminal sends a time synchronization request to the high-precision clock server 100, thereby obtaining the current accurate time provided by the high-precision clock server 100 as the time synchronization reference time T b , and broadcasts this time synchronization reference time to each slave time synchronization terminal through the communication network inside the distributed control system, thereby eliminating the influence of possible time errors of the master terminal itself on the calculation results and more accurately evaluating the time synchronization accuracy of the slave terminal.

[0054] Furthermore, the test bench 300 can also design the reference time message. For example, the reference time broadcast adopts the extended format of IEEE 1588 PTP (Precision Time Protocol), and the message includes but is not limited to the following fields:

[0055] Sync message: includes the timestamp T m of the master terminal.

[0056] Follow_Up message: attaches the accurate reference time T b and the master terminal clock frequency information.

[0057] Delay_Req / Delay_Resp message: used to measure the transmission delay between the master and slave terminals and further correct the clock deviation.

[0058] where the message uses CRC-32 checksum and encryption signature to ensure the integrity and security of data transmission.

[0059] In addition, the test bench 300 can also consider dynamic compensation for network delay, that is, the test bench 300 monitors the network delay between the master and slave terminals in real time and dynamically updates the delay estimation value using the sliding window averaging method (window size is 10 seconds). The delay compensation formula can be expressed but is not limited to:

[0060]

[0061] Among them, D up and D down are the uplink and downlink delays respectively, T b is the time synchronization reference time, and T b_corrected is the delay compensation.

[0062] Step 303: After each slave time synchronization terminal receives the time synchronization reference time, it immediately compares the clock of its own device with the time synchronization reference time and records the clock deviation value ΔT ij (where j represents the jth slave time synchronization terminal). Meanwhile, the multi-channel data acquisition unit 200 acquires the clock deviation values of each slave time synchronization terminal and transmits them to the test bench 300.

[0063] Step 304: The test bench 300 receives the clock deviation values between multiple slave time synchronization terminals and the master time synchronization terminal acquired by the multi-channel data acquisition unit 200, and performs statistical analysis on the clock deviation values of all the acquired slave time synchronization terminals to calculate the time synchronization accuracy of multiple slave time synchronization terminals. That is, multiple measurements of the time deviation values between the master terminal and the slave terminals are performed, and statistical analysis is performed on these measurement values to obtain the degree of closeness (time synchronization accuracy) between the slave terminal time and the master terminal time, which can reflect the accuracy of the slave terminal time synchronization.

[0064] For example, the test bench 300 performs statistical analysis on the clock deviation values of each slave terminal in multiple time synchronization measurement modes, and calculates the mean absolute deviation (MAD), root mean square error (RMSE), and peak-to-peak value of multiple clock deviation values. The calculation formulas can be expressed as follows:

[0065]

[0066] Peak-to-peak = max(ΔT ij ) - min(ΔT ij ),

[0067] After obtaining the mean absolute deviation, root mean square error, and peak-to-peak value of the clock deviation value of each slave terminal, the test bench 300 can identify abnormal deviation values through box plot analysis, and combine the physical location and network topology of the device to locate potential problem nodes of the slave terminal. Thus, the time fluctuation of the slave terminal is analyzed from multiple dimensions, ensuring the accuracy of the located potential problem nodes of the slave terminal.

[0068] In the embodiments of the present application, a test bench 300 can be set up in a system for testing the clock synchronization of a distributed control system. It integrates multiple functions and has powerful processing and data storage capabilities. It can select the device with the lowest deviation rate and the smallest communication delay as the master terminal, and other devices as slave terminals. While ensuring efficient data interaction with other components, it can quickly and accurately process the data received from the master terminal and slave terminals. The obtained time synchronization accuracy helps to optimize the master terminal and slave terminals, thereby ensuring the clock synchronization among multiple devices under test in the distributed control system.

[0069] Optionally, in an embodiment of the present application, the test bench 300 is further configured to calculate the time synchronization optimized clock frequencies of multiple slave time synchronization terminals according to the clock deviation values, so as to correct the time synchronization accuracies of multiple devices under test according to the time synchronization optimized clock frequencies.

[0070] In other embodiments, considering that after calculating the time synchronization accuracy between the master terminal and slave terminals, there may be a large gap in the time synchronization accuracy between some slave terminals and the master terminal, that is, the time synchronization of some slave terminals is poor. Therefore, the test bench 300 in the present application can also calculate the time synchronization optimized clock frequencies of multiple slave time synchronization terminals according to the clock deviation values, so as to correct the time synchronization accuracies of multiple devices under test according to the time synchronization optimized clock frequencies.

[0071] For example, the test bench 300 can dynamically adjust the clock frequencies of the slave terminals according to the clock deviation values by using a PID control algorithm. The PID parameters (proportional, integral, and differential coefficients) are adaptively optimized according to the historical time synchronization deviation data to ensure rapid convergence to the target accuracy. Among them, the adjustment formula can be but is not limited to being expressed as:

[0072]

[0073] where e(t) is the current clock deviation, k p 、k i 、k d are tuning parameters, f old is the historical clock frequency of the slave terminal, and f new is the new clock frequency of the slave terminal, that is, the time synchronization optimized clock frequency.

[0074] The test bench 300 in the embodiments of the present application can calculate the time synchronization optimized clock frequencies of multiple slave time synchronization terminals according to the clock deviation values, and then correct the time synchronization accuracies of multiple devices under test according to the time synchronization optimized clock frequencies. Thereby, the clock synchronization of multiple slave time synchronization terminals can be improved, which helps to ensure the stable operation of the distributed control system.

[0075] Optionally, in an embodiment of the present application, the test bench 300 is further configured to, when the test mode is the multi-channel clock timekeeping accuracy measurement mode, send the timekeeping reference time to multiple devices under test, and receive the counter start times of the multiple devices under test collected by the multi-channel data acquisition unit 200, so as to calculate the timekeeping deviation data of the multiple devices under test according to the timekeeping reference time, the counter start times, and the test duration, and determine the timekeeping accuracy of the multiple devices under test, where the timekeeping reference time is provided by the clock server 100.

[0076] In some embodiments, in addition to measuring the time synchronization accuracy of multiple devices in the distributed control system, the test bench 300 in the present application can also be used to measure the timekeeping accuracy of multiple devices in the distributed control system.

[0077] Specifically, when the test mode is the multi-channel clock timekeeping accuracy measurement mode, the test bench 300 can send the timekeeping reference time to multiple devices under test, and then can use the multi-channel data acquisition unit 200 to collect the counter start times recorded by the multiple devices under test themselves. The test bench 300 then calculates the timekeeping deviation data of the multiple devices under test based on the timekeeping reference time, the counter start times, and the measurement duration of the multi-channel clock timekeeping accuracy measurement, so as to determine the timekeeping accuracy of the multiple devices under test.

[0078] For example, Figure 4 is a flowchart of the multi-channel clock timekeeping accuracy measurement according to an embodiment of the present application, as Figure 4 shown, the process can but is not limited to be expressed as follows:

[0079] Step S401, test environment initialization and reference time acquisition.

[0080] First, prepare the test environment (test environment initialization): The test bench 300 first performs an initialization check on all devices under test in the distributed control system to ensure that the clock modules, communication modules, and counter functions of each device are normal. In addition, the test bench 300 can also confirm the physical locations and communication link states of the devices under test through network topology scanning, and generate a device distribution map for subsequent data analysis.

[0081] Next, acquire the reference time and synchronize and broadcast it: The test bench 300 sends a clock synchronization request to a high-precision clock source (such as an atomic clock or a GPS timing module) to acquire the current accurate reference time T0. The accuracy of the reference time should reach the nanosecond level to ensure the accuracy of the test. Among them, the test bench 300 can but is not limited to broadcast the reference time T0 to each device under test through the IEEE 1588PTP protocol or NTP (Network Time Protocol).

[0082] Step S402, clock synchronization of devices under test and counter start.

[0083] Clock synchronization of the device under test: That is, after each device under test receives the reference time T0, it immediately synchronizes its own clock with the reference time. During the synchronization process, the device records the synchronization completion time Tsync and calculates the synchronization deviation ΔTsync = Tsync - T0. Also, in this process, the test bench 300 can further correct the synchronization deviation through two-way timestamp exchange to minimize the initial clock deviation of each device under test.

[0084] Counter start: After each device under test completes clock synchronization, it starts the internal high-precision clock counter to start recording time. The resolution of the counter should reach the nanosecond level to ensure the accuracy of subsequent measurements. The test bench 300 records the counter start time T start of each device under test and uses it as a reference point for subsequent data analysis.

[0085] Step S403, long-term timekeeping test and data acquisition and storage

[0086] Long-term timekeeping test: The test bench 300 sets the test duration T (such as 24 hours, 7 days, or 30 days) according to the system requirements and sends heartbeat signals to each device under test regularly (such as every hour) during the test to ensure the normal operation of the device. And the test bench 300 in this application supports segmented testing, that is, testing is carried out separately in different time periods (such as day and night) to evaluate the influence of environmental factors (such as temperature, electromagnetic interference) on the timekeeping accuracy.

[0087] Data acquisition and storage: The multi-channel data acquisition unit 200 collects the clock counter values C i of each device under test in real time during the test and uploads the data to the test bench 300 through a high-speed data transmission link. The test bench 300 stores the collected data in the local database and supports querying and analysis according to dimensions such as time and device ID.

[0088] Step S404, timekeeping deviation calculation and statistical analysis

[0089] Timekeeping deviation calculation: The test bench 300 can but is not limited to calculate the clock timekeeping deviation rate ΔT of each device under test according to the following formula i :

[0090]

[0091] where C i is the counter value of the i-th device under test, T0 is the reference time, and T is the test duration.

[0092] The test bench 300 supports real-time deviation monitoring. When the deviation rate of a certain device under test exceeds the preset threshold (such as ±1×10-8), it immediately triggers an alarm and records the abnormal event.

[0093] Statistical analysis: The test bench 300 performs statistical analysis on the collected timekeeping deviation data and calculates the following indicators:

[0094] Average value: Reflects the average timekeeping deviation rate of each device under test.

[0095] Standard deviation: Reflects the degree of dispersion of the timekeeping deviation of each device under test.

[0096] Maximum and minimum values: Reflect the extreme situations of the timekeeping deviation of each device under test.

[0097] Peak-to-Peak: Reflects the fluctuation range of the timekeeping deviation of each device under test.

[0098] The test bench 300 generates a timekeeping deviation distribution diagram to visually display the deviation situations of each device under test, facilitating the positioning of problem nodes.

[0099] In the embodiment of the present application, the test bench 300 can measure the timekeeping accuracy of multiple devices in the distributed control system in combination with the high-precision clock server 100 and the multi-channel data acquisition unit 200. Through the initialization of the test environment, high-precision accurate time, counters, etc., the accuracy of the timekeeping deviation data is effectively improved. Combining the calculation of various indicators, the accuracy of the measurement results of the multi-channel timekeeping accuracy of the distributed control system is greatly improved. Moreover, the test bench 300 in the embodiment of the present application can also preset the duration of the timekeeping accuracy measurement, effectively meeting the measurement requirements of different distributed control systems, without repeated processing, and improving the measurement efficiency.

[0100] Optionally, in an embodiment of the present application, the test bench 300 is further configured to calculate the timekeeping optimized clock frequencies of multiple devices under test according to the timekeeping deviation data, so as to adjust the clock frequencies of multiple devices under test according to the timekeeping optimized clock frequencies until the timekeeping deviation rates of multiple devices under test converge to the target range of timekeeping accuracy.

[0101] Based on the related descriptions of other embodiments, it can be understood that when measuring the time synchronization accuracy of multiple slave terminals in the distributed control system, the test bench 300 in the present application can calculate the time synchronization optimized clock frequencies according to the clock deviation values and correct the time synchronization accuracy of multiple devices under test according to the time synchronization optimized clock frequencies, thereby improving the clock synchronization of multiple slave time synchronization terminals and contributing to ensuring the stable operation of the distributed control system.

[0102] Similarly, the test bench 300 in the embodiment of the present application can also calculate the timekeeping optimized clock frequencies of multiple devices under test according to the timekeeping deviation data, so as to adjust the clock frequencies of multiple devices under test according to the timekeeping optimized clock frequencies until the timekeeping deviation rates of multiple devices under test converge to the target range of timekeeping accuracy.

[0103] For example, the test bench 300 in this application can, but is not limited to, use an adaptive filtering algorithm (such as Kalman filtering) to perform real-time processing on the timekeeping deviation data and dynamically adjust the clock frequencies of each device under test. First, predict the current state based on the previous state and update the uncertainty of the state estimate. Then, dynamically adjust the trust weight of the filter and use the measured deviation to correct the state estimate. Finally, compensate the corrected frequency deviation to the clock source through negative feedback. The adjustment formula can, but is not limited to, be expressed as:

[0104]

[0105] Wherein, represents the state vector ( is the clock deviation estimate, is the frequency deviation estimate); is the state transition matrix (Δt is the sampling interval); H = [1, 0], representing the observation matrix (only observing the clock deviation); Q = diag(qθ, qf), representing the process noise covariance matrix; R represents the measurement noise covariance; K freq represents the frequency adjustment gain coefficient (usually taking values from 0.5 to 1).

[0106] It should be noted that the test bench 300 in the embodiments of this application supports multiple rounds of iterative adjustment until the timekeeping deviation rates of each device under test converge within the target range of timekeeping accuracy. Herein, the target range of timekeeping accuracy can be understood as the accuracy range that the timekeeping deviation rates of multiple devices under test in the distributed control system should meet. For example, 0.003% etc. Specifically, it can be set or adjusted by professionals in this field according to the actual situation. Here, only an exemplary illustration is given without specific limitation.

[0107] In addition, the test bench 300 in the embodiments of this application can also generate an optimization plan based on the test results to help the system improve the timekeeping accuracy of each device. For example:

[0108] Hardware upgrade: Replace the high-precision clock module or add a temperature compensation device;

[0109] Software optimization: Adjust the clock synchronization frequency or enable a more accurate synchronization protocol (such as PTP);

[0110] Environment improvement: Optimize the device layout, reduce the influence of electromagnetic interference or temperature fluctuations on the clock accuracy, etc.

[0111] The test bench 300 in the embodiments of this application can perform real-time processing on the timekeeping deviation data, dynamically adjust the clock frequencies of each device under test, effectively guarantee the timekeeping accuracy of multiple devices in the distributed control system, and can give a certain optimization plan, which helps the distributed control system to adjust the system's hardware facilities, software, and device environment in a timely manner according to the optimization plan.

[0112] Optionally, in an embodiment of the present application, the test bench 300 is further configured to, when the test mode is the multi-channel transmission delay measurement mode, select at least one sending terminal and at least one receiving terminal from multiple devices under test, and calculate the one-way channel transmission delay between at least one sending terminal and at least one receiving terminal according to the data packet sending time of at least one sending terminal, the data packet receiving time of at least one receiving terminal, and the feedback data packet receiving time of at least one sending terminal.

[0113] In some embodiments, the present application can also measure the transmission delays of the transmission channels corresponding to multiple devices in a distributed control system. The test mode at this time is the multi-channel transmission delay measurement mode. In this case, the test bench 300 can select at least one sending terminal and at least one receiving terminal from multiple devices under test. Then, the sending terminal can send a data packet containing the sending time to the receiving terminal. After receiving the data packet, the receiving terminal adds the time when the data packet is received to the data packet and then sends it to the sending terminal. Thus, the initial data packet sending time of the sending terminal, the data packet receiving time of the receiving terminal, and the feedback data packet receiving time when the sending terminal receives the data packet fed back by the receiving terminal can be transmitted to the test bench 300 through the multi-channel data acquisition unit 200. The test bench 300 can calculate the one-way channel transmission delay between at least one sending terminal and at least one receiving terminal according to this information.

[0114] For example, Figure 5 is a flowchart of the multi-channel transmission delay measurement for an embodiment of the present application, as Figure 5 shown, and the specific process can but is not limited to being represented as follows:

[0115] Step S501, terminal selection and initialization.

[0116] Terminal selection: The test bench 300 selects two specific devices under test from the distributed control system, and marks them as the sending terminal Ts and the receiving terminal Tr respectively. The sending terminal is responsible for sending test data packets, and the receiving terminal is responsible for receiving and retransmitting the data packets.

[0117] Initialization settings: The test bench 300 sends initialization instructions to the sending terminal and the receiving terminal through the communication network to ensure that the two terminal devices are in a synchronous test preparation state. The clock counters of the sending terminal and the receiving terminal are cleared, and the internal clock synchronization module is started.

[0118] Step S502, test data packet generation, sending and receiving.

[0119] Data packet generation: The sending terminal Ts generates a data packet containing an accurate timestamp T according to the instruction of the test bench 300 s1The test data packet. Timestamp T s1 Generated by the high-precision clock counter of the sending terminal, with the precision reaching the nanosecond level.

[0120] Data packet sending: The sending terminal Ts sends the test data packet to the receiving terminal Tr through the communication network (such as Ethernet, optical fiber, etc.) inside the distributed control system. The sending terminal records the sending time Ts1 and attaches it to the data packet.

[0121] Data packet reception: After receiving the test data packet, the receiving terminal Tr immediately records the reception time T r1 , and returns the data packet containing T s1 and T r1 to the sending terminal Ts.

[0122] Step S503, Delay calculation and data upload.

[0123] Received return data packet: After receiving the return data packet, the sending terminal Ts records the reception time T s2 , and transmits the T s1 , T r1 and T s2 information to the test bench 300 through the multi-channel data acquisition unit 200.

[0124] One-way transmission delay calculation: The test bench 300 calculates the one-way transmission delay D from the sending terminal Ts to the receiving terminal Tr according to the following formula:

[0125]

[0126] where, T s2 is the time when the sending terminal receives the return data packet, T s1 is the time when the sending terminal sends the test data packet, and T r1 is the time when the receiving terminal receives the test data packet.

[0127] Step S504, Multiple groups of tests and statistical analysis

[0128] Multiple groups of tests: The test bench 300 conducts multiple tests between different pairs of DUTs to obtain multiple groups of transmission delay data. The sending terminal and the receiving terminal for each group of tests can be different to comprehensively evaluate the transmission delay compensation performance of the multi-channel of the distributed control system.

[0129] Statistical analysis: The test bench 300 conducts statistical analysis on the collected transmission delay data, and calculates indicators such as the average transmission delay, delay standard deviation, maximum delay, and minimum delay. For example, the smaller the average transmission delay, the higher the transmission efficiency of the system; the smaller the delay standard deviation, the better the transmission stability of the system.

[0130] In the embodiments of the present application, the test bench 300 can be combined with the multi-channel data acquisition unit 200 to measure the transmission delay accuracy of the transmission channels corresponding to multiple devices in the distributed control system, so as to timely understand the communication conditions of each device, avoid the influence of the channel transmission delay on the communication interaction between devices and the accuracy of the time synchronization measurement result and the holdover accuracy measurement result, and help improve the operation efficiency of the distributed control system while maintaining its stable operation.

[0131] Optionally, in an embodiment of the present application, the test bench 300 is further configured to adjust the transmission delay compensation parameters of the distributed control system according to the one-way channel transmission delay until the preset transmission delay requirements of the distributed control system are met.

[0132] In some embodiments, the test bench 300 in the present application can also compensate and optimize the channel transmission delay of the transmission channels corresponding to each device in the distributed control system until the preset transmission delay requirements of the distributed control system are met. Herein, the preset transmission delay requirements can be understood as the requirements that the channel transmission delays of the transmission channels corresponding to each device in the distributed control system should meet. For example, within a certain channel transmission delay range, etc. Specifically, it can be determined or adjusted by those skilled in the art according to the actual situation. Only exemplary explanations are provided here, without specific limitations.

[0133] For example, according to the calculated one-way channel transmission delay accuracy, the test bench 300 can dynamically adjust the transmission delay compensation parameters of the distributed control system, such as the delay compensation value, compensation frequency, etc., to further optimize the transmission delay compensation performance of the system.

[0134] In addition, the test bench 300 can also generate a certain test report and provide optimization suggestions, such as optimizing the network topology structure, adding redundant communication links, etc., to improve the transmission delay compensation accuracy of the system.

[0135] The test bench 300 in the embodiments of the present application can compensate and optimize the delay of the transmission channels in the distributed control system, ensure the real-time performance and accuracy of data transmission between devices, enable the system to operate in coordination, and improve the overall performance; it can also reduce the uncertainty of data transmission, reduce the risk of system failures caused by delays, and enhance the stability and reliability of the system.

[0136] The system for testing the clock synchronization of a distributed control system according to an embodiment of the present application can form a system for testing the clock synchronization of a distributed control system through a clock server, a multi-channel data acquisition unit, a test bench, etc. Thus, it realizes comprehensive, accurate and efficient measurement and evaluation of the clock keeping accuracy, time synchronization accuracy and transmission delay compensation accuracy of multiple devices in the distributed control system, thereby effectively improving the monitoring level of the clock synchronization performance of the distributed control system and ensuring the reliability and stability of the overall operation of the distributed control system. Therefore, it solves the problems in the related art that most clock synchronization testing methods are carried out for a certain aspect, often having defects such as insufficient test coverage, limited accuracy and difficulty in comprehensively evaluating multiple channels simultaneously, being unable to meet the strict requirements of modern distributed control systems for high-precision clock synchronization, and being difficult to ensure the stability and reliability of the clock synchronization system operation in the distributed control system.

[0137] Next, a method for testing the clock synchronization of a distributed control system according to an embodiment of the present application will be described with reference to the accompanying drawings.

[0138] Figure 6 It is a schematic structural diagram of a method for testing the clock synchronization of a distributed control system according to an embodiment of the present application.

[0139] As Figure 6 shown, the method for testing the clock synchronization of a distributed control system adopts a system for testing the clock synchronization of a distributed control system, wherein the method includes the following steps:

[0140] In step S601, obtain the time synchronization reference time and / or the time keeping reference time and / or the data packet sending time, data packet receiving time, feedback data packet receiving time.

[0141] Step S602, based on the time synchronization reference time, determine the clock deviation value data of multiple devices under test in the distributed control system, and / or based on the time keeping reference time, determine the time keeping deviation data of multiple devices under test in the distributed control system, and / or based on the data packet sending time, data packet receiving time, feedback data packet receiving time, determine the channel transmission delay data of the corresponding transmission channels of multiple devices under test in the distributed control system.

[0142] Step S603, calculate the time synchronization accuracy of multiple devices under test in the distributed control system according to the clock deviation value data, and / or calculate the time keeping accuracy of multiple devices under test in the distributed control system according to the time keeping deviation data, and / or calculate the one-way channel transmission delay of the corresponding transmission channels of multiple devices under test in the distributed control system according to the channel transmission delay data.

[0143] Optionally, in an embodiment of the present application, it further includes:

[0144] Calculate the time synchronization optimized clock frequencies of multiple devices under test in the distributed control system according to the clock deviation value data, so as to correct the time synchronization accuracy of the multiple devices under test according to the time synchronization optimized clock frequencies.

[0145] Calculate the timekeeping optimized clock frequencies of multiple devices under test in the distributed control system according to the timekeeping deviation data, so as to adjust the clock frequencies of the multiple devices under test to the timekeeping deviation rates of the multiple devices under test converging to the target range of timekeeping accuracy according to the timekeeping optimized clock frequencies.

[0146] Adjust the transmission delay compensation parameters of the distributed control system according to the one-way channel transmission delay to meet the preset transmission delay requirements of the distributed control system.

[0147] It should be noted that the above explanation of the system embodiment for testing the clock synchronization of the distributed control system also applies to the method for testing the clock synchronization of the distributed control system in this embodiment, and will not be elaborated here.

[0148] According to the method for testing the clock synchronization of the distributed control system proposed in the embodiment of the present application, a system for testing the clock synchronization of the distributed control system can be composed of a clock server, a multi-channel data acquisition unit, a test bench 300, etc. Thus, comprehensive, accurate and efficient measurement and evaluation of the clock timekeeping accuracy, time synchronization accuracy and transmission delay compensation accuracy of multiple devices in the distributed control system are realized, so that the monitoring level of the clock synchronization performance of the distributed control system can be effectively improved, and the reliability and stability of the overall operation of the distributed control system can be ensured. Thus, the problems in the related art that most of the clock synchronization test methods are carried out for a certain aspect, often there are defects such as insufficient test coverage, limited accuracy and difficulty in comprehensively evaluating multiple channels at the same time, which cannot meet the strict requirements of modern distributed control systems for high-precision clock synchronization and are difficult to ensure the stability and reliability of the clock synchronization system operation in the distributed control system are solved.

[0149] Figure 7 The structural schematic diagram of the electronic device provided by the embodiment of the present application. The electronic device may include:

[0150] A memory 701, a processor 702, and a computer program stored on the memory 701 and executable on the processor 702.

[0151] When the processor 702 executes the program, it implements the method for testing the clock synchronization of the distributed control system provided in the above embodiment.

[0152] Further, the electronic device further includes:

[0153] A communication interface 703 for communication between the memory 701 and the processor 702.

[0154] A memory 701 for storing a computer program that can run on a processor 702.

[0155] The memory 701 may include a high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0156] If the memory 701, the processor 702, and the communication interface 703 are implemented independently, the communication interface 703, the memory 701, and the processor 702 can be interconnected via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0157] Optionally, in a specific implementation, if the memory 701, the processor 702, and the communication interface 703 are integrated on a single chip, the memory 701, the processor 702, and the communication interface 703 can communicate with each other through an internal interface.

[0158] The processor 702 may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0159] The embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the method for testing the clock synchronization of a distributed control system is implemented as described above.

[0160] The embodiments of the present application also provide a computer program product, including a computer program that can run computer instructions, and when the computer instructions are executed by a processor, the method for testing the clock synchronization of a distributed control system provided by the embodiments of the present application is implemented.

[0161] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0162] In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0163] Any process or method description depicted in a flowchart or otherwise described herein may be understood to represent a module, segment, or portion of code including one or N executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of this application includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of this application pertain.

[0164] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, which can be embodied specifically in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection portion (electronic device) having one or N wirings, a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0165] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or a combination of the following techniques known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), and the like.

[0166] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried out in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0167] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, may exist separately as individual physical units, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0168] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A system for testing the clock synchronization of a distributed control system, characterized in that, Including: A clock server for providing a time reference for time synchronization; A multi-channel data acquisition unit for acquiring data information of transmission channels corresponding to multiple devices under test in a distributed control system; A test bench, which, when the test mode is a multi-channel time synchronization accuracy measurement mode, selects at least one master time synchronization terminal from the multiple devices under test, and receives clock deviation values between multiple slave time synchronization terminals other than the at least one master time synchronization terminal and the master time synchronization terminal collected by the multi-channel data acquisition unit, so as to calculate the time synchronization accuracy of the multiple slave time synchronization terminals according to the clock deviation values, wherein the clock deviation values are determined by comparison results between the multiple slave time synchronization terminals and the time reference for time synchronization.

2. The system for testing the clock synchronization of a distributed control system according to claim 1, characterized in that, The test bench is further configured to calculate a time synchronization optimized clock frequency of the multiple slave time synchronization terminals according to the clock deviation values, so as to correct the time synchronization accuracy of the multiple devices under test according to the time synchronization optimized clock frequency.

3. The system for testing the clock synchronization of a distributed control system according to claim 1, wherein The test bench is further configured to, when the test mode is a multi-channel clock holdover accuracy measurement mode, send a holdover reference time to the multiple devices under test, and receive the counter start times of the multiple devices under test collected by the multi-channel data acquisition unit, so as to calculate holdover deviation data of the multiple devices under test according to the holdover reference time, the counter start times and the test duration, and determine the holdover accuracy of the multiple devices under test according to the holdover deviation data, wherein the holdover reference time is provided by the clock server.

4. The system for testing the clock synchronization of a distributed control system according to claim 3, characterized in that The test bench is further configured to calculate a holdover optimized clock frequency of the multiple devices under test according to the holdover deviation data, so as to adjust the clock frequencies of the multiple devices under test to make the holdover deviation rates of the multiple devices under test converge to a target range of holdover accuracy according to the holdover optimized clock frequency.

5. The system for testing the clock synchronization of a distributed control system according to claim 1, wherein The test bench is further configured to, when the test mode is a multi-channel transmission delay measurement mode, select at least one sending terminal and at least one receiving terminal from the multiple devices under test, and calculate a one-way channel transmission delay between the at least one sending terminal and the at least one receiving terminal according to the data packet sending time of the at least one sending terminal, the data packet receiving time of the at least one receiving terminal, and the feedback data packet receiving time of the at least one sending terminal.

6. The system for testing the clock synchronization of a distributed control system according to claim 5, characterized in that, The test bench is further configured to adjust transmission delay compensation parameters of the distributed control system according to the one-way channel transmission delay to meet preset transmission delay requirements of the distributed control system.

7. A method for testing the clock synchronization of a distributed control system, characterized in that, Using the system for testing clock synchronization of a distributed control system as described in any one of claims 1-6, wherein the method includes the following steps: Obtaining the time reference for time synchronization and / or the holdover reference time and / or the data packet sending time, the data packet receiving time, and the feedback data packet receiving time; Based on the time synchronization reference time, determine the clock deviation value data of multiple devices under test in the distributed control system, and / or based on the timekeeping reference time, determine the timekeeping deviation data of multiple devices under test in the distributed control system, and / or based on the data packet sending time, data packet receiving time, and feedback data packet receiving time, determine the channel transmission delay data of the transmission channels corresponding to multiple devices under test in the distributed control system; Calculate the time synchronization accuracy of multiple devices under test in the distributed control system according to the clock deviation value data, and / or calculate the timekeeping accuracy of multiple devices under test in the distributed control system according to the timekeeping deviation data, and / or calculate the one-way channel transmission delay of the transmission channels corresponding to multiple devices under test in the distributed control system according to the channel transmission delay data.

8. The method according to claim 7, wherein Further comprising: Calculate the time synchronization optimized clock frequency of multiple devices under test in the distributed control system according to the clock deviation value data, so as to correct the time synchronization accuracy of the multiple devices under test according to the optimized clock frequency; Calculate the timekeeping optimized clock frequency of multiple devices under test in the distributed control system according to the timekeeping deviation data, so as to adjust the clock frequencies of the multiple devices under test to the timekeeping deviation rate of the multiple devices under test converging to the target range of timekeeping accuracy according to the timekeeping optimized clock frequency; Adjust the transmission delay compensation parameters of the distributed control system according to the one-way channel transmission delay to meet the preset transmission delay requirements of the distributed control system.

9. An electronic device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the method for testing the clock synchronization of a distributed control system according to any one of claims 7 or 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to be used for implementing the method for testing the clock synchronization of a distributed control system according to any one of claims 7 or 8.

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