Data processing method and related device

Abstract

The invention discloses a data processing method and a related device, and belongs to the technical field of computers, the disclosed related device comprises a storage device, and the storage device comprises a data storage unit used for storing data; the first instruction storage unit is used for obtaining and storing a plurality of data processing instructions transmitted by an external device in a batch transmission mode; and the processing unit is used for responding to first indication information for indicating to execute a data processing instruction, and executing an operation corresponding to the data processing instruction in the first instruction storage unit so as to carry out data processing on the data in the storage unit.

Description

[0001] This application is a divisional application of the application with the application date of October 16, 2024, the application number of 202411448224.9, and the invention creation name of "A Data Processing Method and Related Device". Technical Field

[0002] This application belongs to the field of computer technology, and particularly relates to a data processing method and related device. Background Art

[0003] Currently, storage chips such as LP-DDR (Low Power Double Data Rate SDRAM) are provided with PIM (Process in memery) processing units locally, which can be used for local operations on the data in the storage chips. When the known technology downloads data processing instructions to the storage chip to enable the storage chip to perform local data operations based on the PIM processing unit, there is a loss in the bandwidth efficiency of the transmission of the data processing instructions, resulting in low bandwidth efficiency and affecting the execution efficiency of the LP-PIM data processing instructions at the same time. Summary of the Invention

[0004] For this reason, the present application discloses the following technical solutions:

[0005] A storage device, comprising:

[0006] A data storage unit for storing data;

[0007] A first instruction storage unit for obtaining and storing multiple data processing instructions transmitted by an external device through a batch transmission method;

[0008] A processing unit for, in response to first indication information for indicating the execution of a data processing instruction, performing an operation corresponding to the data processing instruction in the first instruction storage unit to perform data processing on the data in the storage unit.

[0009] Optionally, the storage device further comprises a register unit and a control unit;

[0010] The register unit comprises a first sub-register unit and a second sub-register unit;

[0011] The control unit is configured to, in response to detecting that first indication information for indicating the execution of a data processing instruction is written in the first sub-register unit, control the processing unit to perform an operation corresponding to the data processing instruction in the first instruction storage unit; and to determine an execution status of the data processing instruction in the first instruction storage unit and write the execution status into the second sub-register unit for providing the execution status to the external device other than the storage device.

[0012] Optionally, the control unit is further configured to: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-register unit, perform a data access operation indicated by the second indication information on the data storage unit.

[0013] Wherein, the second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit is in a non-access state according to the execution status of the data processing instruction stored in the second sub-register unit.

[0014] Optionally, the first instruction storage unit includes a first queue for storing multiple data processing instructions transmitted by a bulk transfer method based on the execution order between the data processing instructions.

[0015] A control chip includes:

[0016] A second instruction storage unit for storing multiple data processing instructions to be sent to a storage device;

[0017] A storage controller for obtaining multiple data processing instructions in the second instruction storage unit and transmitting the multiple data processing instructions to the storage device based on a bulk transfer method, so that a processing unit in the storage device, in response to first indication information for indicating the execution of a data processing instruction, performs an operation corresponding to each received data processing instruction to perform data processing on data stored in a data storage unit of the storage device.

[0018] Optionally, when transmitting the multiple data processing instructions to the storage device based on a bulk transfer method, the storage controller is specifically configured to:

[0019] Obtain an execution status of a data processing instruction in the storage device;

[0020] In response to the execution status satisfying a status condition, transmit multiple data processing instructions in the control chip to the storage device based on a bulk transfer method.

[0021] Optionally, the storage controller is further configured to perform at least one of the following:

[0022] Send first indication information to the storage device to instruct the storage device to execute each received data processing instruction;

[0023] Send second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit included therein;

[0024] Wherein, the second indication information is sent to the storage device by the storage controller when it is determined according to the execution status of the data processing instructions in the storage device that the data in the data storage unit in the storage device is in a non-access state.

[0025] Optionally, the second instruction storage unit includes a second queue for storing multiple data processing instructions to be sent to the storage device based on the execution order between the data processing instructions.

[0026] An electronic device includes a storage controller and a storage device, and the storage device includes a first instruction storage unit, a processing unit, and a data storage unit;

[0027] The storage controller is configured to obtain multiple data processing instructions and transmit the multiple data processing instructions to the storage device based on a bulk transfer mode;

[0028] The storage device is configured to receive and store the multiple data processing instructions transmitted by the storage controller based on the first instruction storage unit, and in response to first indication information for instructing the execution of a data processing instruction, perform an operation corresponding to the data processing instruction based on the processing unit to perform data processing on the data stored in the data storage unit.

[0029] A data processing method is applied to a storage device, and the method includes:

[0030] Obtain and store multiple data processing instructions transmitted by an external device based on a bulk transfer mode;

[0031] In response to first indication information for instructing the execution of a data processing instruction, use the processing unit of the storage device to perform an operation corresponding to the multiple data processing instructions, so as to process the data stored in the data storage unit of the storage device by performing an operation corresponding to each data processing instruction.

[0032] A data processing method is applied to a control chip, and the method includes:

[0033] Obtain multiple data processing instructions to be sent to a storage device;

[0034] Based on the batch transfer mode, multiple data processing instructions are transferred to the storage device, so that the processing unit in the storage device responds to the first indication information for indicating the execution of the data processing instruction, and executes the operations corresponding to the received data processing instructions to perform data processing on the data stored in the data storage unit of the storage device.

[0035] A data processing method, applied to an electronic device, includes:

[0036] The storage controller obtains multiple data processing instructions, and based on the batch transfer mode, transfers the multiple data processing instructions to the storage device;

[0037] The storage device receives and stores the multiple data processing instructions transferred based on the batch transfer mode based on the included first instruction storage unit, and in response to the first indication information for indicating the execution of the data processing instruction, based on the included processing unit, executes the operations corresponding to the data processing instruction to perform data processing on the data in the included data storage unit.

[0038] Optionally, the transferring the multiple data processing instructions to the storage device based on the batch transfer mode includes:

[0039] The storage controller obtains the execution status of the data processing instructions in the storage device, and in response to the execution status satisfying the status condition, based on the batch transfer mode, transfers multiple data processing instructions in the control chip to the storage device.

[0040] Optionally, the data processing method further includes at least one of the following:

[0041] The storage controller sends the first indication information to the storage device to instruct the storage device to execute each received data processing instruction;

[0042] The storage controller sends the second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit included;

[0043] Wherein, the second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution status of the data processing instructions in the storage device. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application or in the related art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the related art. Obviously, the accompanying drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0045] Figure 1 is a schematic structural diagram of a composition of a storage device provided by the present application;

[0046] Figure 2 is another schematic structural diagram of a composition of a storage device provided by the present application;

[0047] Figure 3 is a schematic structural diagram of a composition of a control chip provided by the present application;

[0048] Figure 4 is an exemplary implementation structural diagram of a storage device and a control chip provided by the present application;

[0049] Figure 5 is a schematic structural diagram of the composition of LP-DDR and SOC in the known technology provided by the present application;

[0050] Figure 6 is a schematic structural diagram of an electronic device provided by the present application;

[0051] Figure 7 is a flowchart of a data processing method applied to a storage device provided by the present application;

[0052] Figure 8 is a flowchart of a data processing method applied to a control chip provided by the present application;

[0053] Figure 9 is a flowchart of a data processing method applied to an electronic device provided by the present application. Detailed implementation manners

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0055] Embodiments of the present application provide a data processing method and related devices, which are used to solve the problems in the prior art that when the processing unit in a storage chip needs to perform local processing of memory data by executing instructions, the transmission efficiency of the data processing instructions is low, there is a loss in bandwidth efficiency, and at the same time, the execution efficiency of the data processing instructions is affected. The solutions of the embodiments of the present application can be applied to electronic devices in many general or special computing device environments or configurations, such as: personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor devices, and so on.

[0056] The related device provided by the embodiments of the present application includes a storage device, a control chip, and an electronic device.

[0057] Among them, the storage device can be a storage chip with local computing capabilities of the electronic device, specifically, but not limited to, a memory chip with local computing capabilities or a chip in a non-memory storage scenario, such as a HBM (High Bandwidth Memory) with a HBM-PIM processing unit, and LP DDR, low-power DDR, etc. with an LP DDR-PIM processing unit applicable to mobile terminals. In the embodiments of the present application, the storage device being a memory chip with local computing capabilities will be mainly used as an example to illustrate the solution.

[0058] For ease of description, in the embodiments of the present application, a memory chip with local computing capabilities, such as a memory chip with a PIM processing unit, is referred to as a memory-computation integrated chip.

[0059] The control chip can be, but not limited to, the SOC (System on Chip) of the electronic device.

[0060] See Figure 1 Referring to the schematic diagram of the composition structure of the storage device shown, in the embodiments of the present application, the storage device at least includes a data storage unit 11, a first instruction storage unit 12, and a processing unit 13.

[0061] Among them, the data storage unit 11 is used to store data.

[0062] The number of data storage units 11 included in the storage device is not limited and can be one or more.

[0063] Optionally, the data storage unit 11 can be a Bank in the memory-computation integrated chip. A memory-computation integrated chip usually includes multiple Banks, and each Bank is composed of multiple memory units. A memory unit is the basic unit in the memory used to store data. However, it is not limited to this. The data storage unit can also correspond to a memory die, and each memory die includes multiple Banks.

[0064] The first instruction storage unit 12 is configured to obtain and store multiple data processing instructions transmitted by an external device in a bulk transfer manner.

[0065] Optionally, the first instruction storage unit includes a first queue, which is specifically configured to store multiple data processing instructions transmitted in a bulk transfer manner based on the execution order between the data processing instructions.

[0066] The external device may be, but is not limited to, a control chip such as an SOC.

[0067] In the storage devices such as the memory - in - computing chips in the prior art, the first instruction storage unit 12 is not included. In the embodiments of the present application, by adding the first instruction storage unit 12 in the storage device, such as adding a first queue, the storage device is capable of storing multiple data processing instructions transmitted in a bulk transfer manner based on the added first instruction storage unit 12. Furthermore, based on this capability, data processing instructions can be transmitted between the storage device and an external device such as a control chip like an SOC in a bulk transfer manner.

[0068] Among them, the multiple data processing instructions transmitted in a bulk transfer manner may include data processing instructions involved in AI (Artificial Intelligence) operations in AI application scenarios, and / or data operation instructions involved in data operations in non - AI application scenarios (i.e., conventional application scenarios).

[0069] The data processing instructions in the first instruction storage unit 12 may include data transfer instructions for instructing data transfer between the data storage unit 11 and the processing unit 13 of the storage device, and data operation instructions for instructing the processing unit 13 to execute data operations.

[0070] Furthermore, the data transfer instructions can be further divided into data read instructions and data write instructions. Among them, the data read instructions are used to instruct the processing unit 13 to read data from the data storage unit 11 for data operations, and the data write instructions are used to instruct the processing unit 13 to write data (such as operation result data, intermediate data, etc.) into the data storage unit 11 for data storage. The data operation instructions may include, but are not limited to, instructions for instructing multiplication operations and accumulation operations (i.e., sum operations) on data, which can be determined according to actual operation requirements.

[0071] The processing unit 13 is configured to, in response to the first indication information for instructing the execution of data processing instructions, execute the operations corresponding to the data processing instructions in the first instruction storage unit 12 to process the data in the storage unit 11.

[0072] Optionally, the processing unit 13 can be a PIM processing unit in the memory-computing integrated chip, such as a programmable computing unit (PCU), which can be used to perform local operations on the data in the memory-computing integrated chip. By performing local operations on the data in the memory-computing integrated chip, the computing pressure on external devices such as control chips like SOC in the memory-computing integrated chip can be reduced. At the same time, the data transmission volume between the memory-computing integrated chip and external devices such as SOC can be decreased, saving bandwidth and reducing data latency.

[0073] Optionally, multiple processing units can correspond to one first instruction storage unit, and each or multiple data storage units can correspond to one processing unit.

[0074] For the case where the storage device is DDR, the data storage unit is a Bank in DDR, the processing unit is a PIM processing unit (or called PIM processor) in DDR, and the first instruction storage unit is an additional first queue, in an optional implementation manner, several DDR modules can be set for each Channel (memory channel). Correspondingly, each Channel includes multiple Banks, each or multiple Banks correspond to one PIM processing unit, and a first queue can be configured for each Channel. The first queue configured for each Channel corresponds to each PIM processing unit in the Channel and is used to store operation instructions corresponding to each PIM processing unit.

[0075] For example, assuming that the system of the electronic device supports dual-channel memory and there are four memory slots on the motherboard, then each Channel can have two slots, and correspondingly, two memory-computing integrated chips can be corresponded to.

[0076] The PIM processing units on each Channel usually execute the same instructions simultaneously for synchronous computing.

[0077] In addition, a register group can also be set in each Channel for storing relevant information (such as the first indication information for indicating the execution of data processing instructions, or the second indication information for indicating data access). And for multiple Channels, a local memory controller (Control) can be set for the memory-computing integrated chip with PIM processing units. This memory controller, namely Control, can be used as an interface to connect multiple Channels and can provide the required control functions for the processing units, data storage units, etc. on each Channel.

[0078] In some implementations, for a processing-in-memory chip, when it comes to local PIM operations, data processing instructions can be transmitted to the processing-in-memory chip one by one, and another instruction will not be transmitted until the operation of one instruction is completed, so as to avoid instruction conflicts. Obviously, this method has a loss in bandwidth efficiency, resulting in low bandwidth efficiency and affecting the execution efficiency of data processing instructions at the same time.

[0079] In the embodiment of the present application, by adding a first instruction storage unit such as a first queue in the storage device, the storage device is enabled to store multiple data processing instructions transmitted in a batch transmission manner, and supports the transmission of data processing instructions between the storage device and its external devices such as a control chip like SOC based on the batch transmission manner. Based on this design, when a storage device such as a processing-in-memory chip is involved in local operations such as local PIM calculations, data processing instructions can be transmitted to the storage device in a batch transmission manner, instead of transmitting the data processing instructions one by one, thereby improving the transmission efficiency of data processing instructions, avoiding bandwidth efficiency losses, and avoiding affecting the execution efficiency of data processing instructions in the storage device, and improving the execution efficiency of data processing instructions.

[0080] In an optional embodiment, referring to Figure 2 the schematic structural diagram of the composition of the storage device shown, the storage device provided in the present application further includes a register unit 14 and a control unit 15.

[0081] Among them, the register unit 14 includes a first sub-register unit 141 for storing indication information and a second sub-register unit 142 for storing status information.

[0082] The indication information stored in the first sub-register unit may include, but is not limited to, a first indication information for indicating the execution of a data processing instruction sent by an external device of the storage device such as SOC, and a second indication information for indicating data access to the storage device sent by the external device.

[0083] The status information stored in the second sub-register unit may include, but is not limited to, the execution status information of data processing instructions in the first instruction storage unit 12 (such as the first queue).

[0084] Optionally, the register unit 14 may be a register (Memory Register, MR) in the processing-in-memory chip, and the first sub-register unit and the second sub-register unit included in the register unit 14 may be different register areas of the MR respectively.

[0085] Exemplarily, in this embodiment, a DB Register (Doorbell Register) and a CQ Register (Status Register) are newly added to the MR area of the storage device to be used as the above-mentioned first sub-register unit and second sub-register unit respectively, for storing indication information and status information respectively. Among them, DB is the abbreviation of Doorbell, representing a doorbell mechanism for making relevant indications to the storage device (such as indicating the execution of a data processing instruction or indicating data access to the storage device); CQ is the abbreviation of Completion Queue, representing the execution / completion status of data processing instructions in the first queue.

[0086] The control unit 15 may be a memory controller local to the in-memory computing chip.

[0087] In the embodiment of the present application, the control unit 15 is configured to, in response to detecting that the first sub-register unit writes the first indication information for indicating the execution of a data processing instruction, execute the data processing instruction in the first instruction storage unit 12, such as reading the data processing instruction and decoding the read data processing instruction, etc., and then generate a control signal, and based on the control signal, control the processing unit 13 corresponding to the data processing instruction to execute the specific operation corresponding to the data processing instruction, such as reading data, performing a multiplication operation or an accumulation operation on the read data, etc.

[0088] In practical applications, when an external device of the storage device, such as a control chip like an SOC, needs the storage device to execute local data processing internally based on application requirements, in addition to downloading multiple data processing instructions to the storage device through a batch transmission method, it can also send the first indication information for indicating the execution of a data processing instruction to the storage device as needed (the external device can specifically send the first indication information after downloading multiple data processing instructions to the storage device, or it can also send the first indication information simultaneously when downloading the multiple data processing instructions to the storage device). The sent first indication information is specifically stored in the first sub-register unit of the register unit 14 in the storage device. Once the control unit 15 detects the first indication information in the first sub-register unit, it reads and executes the data processing instruction in the first instruction storage unit such as the first queue, and controls the processing unit to perform data processing based on the instruction execution process.

[0089] Taking a memory device as an example of a memory - computing integrated chip, when an external device such as an SOC needs the memory - computing integrated chip to perform local processing on its data based on application requirements (such as AI computing requirements), after downloading multiple data through batch transmission to the memory - computing integrated chip, the first indication information for instructing the execution of data - processing instructions can be further sent to the memory - computing integrated chip as needed. The sent first indication information is stored in the DB Register (the first sub - register unit) of the memory - computing integrated chip. Once the local memory controller of the memory - computing integrated chip detects the first indication information in the DB Register, it reads the data - processing instructions in the first instruction storage unit 12 such as the first queue and executes them, and controls the corresponding PIM processing unit of the memory - computing integrated chip to perform the specific data processing corresponding to the data - processing instructions based on the instruction execution process.

[0090] The processing unit 13 in the memory device, under the control of the control unit 15, specifically executes the operations corresponding to each data - processing instruction based on the execution order of each data - processing instruction in the first instruction storage unit 12. Among them, multiple data - processing instructions received based on the batch transmission method are stored in the first instruction storage unit 12 in sequence according to the execution order between different data - processing instructions. Thus, the control unit 15 directly reads and executes each data - processing instruction stored in the first instruction storage unit 12 in sequence, such as reading and executing each data - processing instruction in the first queue in sequence, and controls the corresponding processing unit 13 such as the PIM processing unit to perform the specific operations corresponding to the data - processing instructions during the execution process, which can ensure that the execution order of each data - processing instruction meets the actual order requirements of its operation logic.

[0091] In addition, optionally, the control unit 15 is further configured to determine the execution status of the data - processing instructions in the first instruction storage unit 12 and write the execution status into the second sub - register unit for providing the execution status to an external device outside the memory device.

[0092] Optionally, the execution status of the data - processing instructions in the first instruction storage unit 12 includes the execution progress of the data - processing instructions in the first instruction storage unit 12 and the instruction type of the currently executed data - processing instruction. For example, for the first queue that contains a total of N data - processing instructions, the execution progress may include, but is not limited to, which data - processing instruction in the first queue is currently being executed, or the proportion of the currently executed data - processing instructions to the total number of instructions in the first queue, etc. The type of the data - processing instruction may, but is not limited to, be a data transfer instruction or a data operation instruction.

[0093] The N is an integer greater than 1.

[0094] Subsequently, an external device other than the storage device can determine whether to transmit a data processing instruction to the storage device based on the execution status stored in the second sub-register unit.

[0095] In summary, on the basis of adding the first instruction storage unit in the storage device, in this embodiment, by further adding a first sub-register unit for storing indication information and a second sub-register unit for storing status information in the storage device, and by designing a matching control function for the control unit of the storage device, the entire process of data processing instruction transmission, reception, execution, and status recording based on the first sub-register unit, the second sub-register unit, and the first instruction storage unit can be organically organized and coordinated, and a sequence mechanism based on Doorbell is implemented. The execution status of the data processing instruction in the storage device is provided to the external device through the second sub-register unit, so that the external device can send relevant instructions or indications such as the second indication information for indicating data access based on the execution status of the data processing instruction in the storage device, effectively avoiding conflicts and improving the instruction execution efficiency of the processing unit in the storage device, such as improving the instruction execution efficiency of LP-PIM. Thus, while improving the transmission efficiency of the data processing instruction and avoiding bandwidth efficiency loss, conflicts are also avoided and the instruction execution efficiency of the processing unit in the storage device is further improved.

[0096] In an alternative embodiment, the control unit 15 in the storage device is further configured to: in response to detecting that the second indication information for indicating data access to the storage device is written in the first sub-register unit, perform a data access operation on the data storage unit in the storage device as indicated by the second indication information.

[0097] Wherein, the second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution status of the data processing instruction stored in the second sub-register unit.

[0098] When an external device of the storage device, such as a control chip like an SOC, has a need to access the data stored in the storage device, specifically, it can determine whether the data storage unit in the storage device is in a window period according to the execution status of the data processing instruction stored in the second sub-register unit of the storage device. If it is in the window period, it indicates that the data in the data storage unit is in a non-access state. Conversely, if it is not in the window period, it indicates that the data in the data storage unit is in an access state. And when the data storage unit is in the window period, that is, the data in the data storage unit is in a non-access state, the second indication information for instructing data access can be sent to the storage device. In the embodiments of the present application, the sent second indication information is stored in the first sub-register unit of the register unit 14. The control unit 15 in the storage device can perform corresponding data access operations on the data storage unit 11 of the storage device by detecting and responding to the second indication information in the first sub-register unit, such as a read operation to read data from the data storage unit 11 or a write operation to write data to the data storage unit 11, etc., to meet the data access needs of the external device for the storage device.

[0099] In some implementation manners, when the in-memory computing chip needs to perform local data processing, it is necessary to first switch the mode of the in-memory computing chip from the conventional data read / write mode to the internal processing mode. For example, switch the in-memory computing chip from normalLP (a conventional mode that can be used to read and write data in the in-memory computing chip) to the PIM operation mode (a mode used for the PIM processing unit in the in-memory computing chip to perform local data processing). After switching to the internal processing mode, such as the PIM operation mode, the external device cannot access the data of the in-memory computing chip to avoid conflicts with the data access of the PIM processing unit to the in-memory computing chip. If the external device needs to access the data of the in-memory computing chip, it needs to switch back to the conventional data read / write mode, such as the normalLP mode. That is, during the internal processing mode of the in-memory computing chip, such as during the PIM operation, the data read / write requirements of the external device need to wait all the time. This will obviously increase the data access latency of the external device to the in-memory computing chip and affect the data access efficiency of the in-memory computing chip. Other storage chips with local processing capabilities also have similar characteristics.

[0100] In view of the above problems, the applicant has found that during the execution of the instruction sequence in the first instruction storage unit 12, due to the execution cycle of the processing unit 13 such as the PIM processing unit, there is a window period for operating the data storage unit in a storage device such as a memory-computation integrated chip. For example, when the PIM processing unit executes a data operation instruction (such as a multiplication operation or an addition operation instruction) in the instruction sequence of the first queue, the data operation is only performed inside the PIM processing unit without accessing the Bank of the memory-computation integrated chip, thus generating a window period for operating the Bank. Correspondingly, the Bank can be in a window period state, that is, the Bank is not accessed by the PIM processing unit at this time. In view of the above problems existing in the known technology, in the embodiment of the present application, taking advantage of the window period feature of the operation of the processing unit 13 on the data storage unit 11 in a storage device such as a memory-computation integrated chip, during the window period of the data storage unit 11, an external device such as an SOC chip is used to perform the data access operation required for the data storage unit 11 in the storage device.

[0101] Specifically, for an external device such as an SOC control chip, when there is a need to access the data stored in the storage device, it can specifically determine whether the data storage unit in the storage device is in a window period according to the execution status of the data processing instruction stored in the second sub-register unit of the storage device, and when the data storage unit is in a window period, that is, when the data in the data storage unit is in a non-access state, send the second indication information for instructing data access to the storage device. The control unit 15 responds to detecting that the second indication information for instructing data access to the storage device is written in the first sub-register unit, and performs the data access operation indicated by the second indication information for the corresponding data processing unit.

[0102] However, not limited to this, in practical applications, when there is a need to access the data stored in the storage device, the external device can also directly send the second indication information for instructing data access to the storage device, write the second indication information into the first sub-register unit, and the control unit 15 responds to detecting that the second indication information for instructing data access to the storage device is written in the first sub-register unit, and determines whether the data storage unit 11 is in an idle period according to the execution status of the data processing instruction stored in the second sub-register unit. Specifically, it can be determined whether the data storage unit 11 is in an idle period according to the type of the currently executed data processing instruction in the execution status. If the type of the currently executed data processing instruction is a data transfer instruction, the data storage unit 11 is not in an idle period. If the type of the currently executed data processing instruction is a data operation instruction, the data storage unit 11 is in an idle period. When the data storage unit 11 is in an idle period, the data access operation indicated by the second indication information can be executed on the data storage unit 11, such as a read operation or a write operation. If the data storage unit 11 is not in an idle period, continuous detection can be performed, and when an idle period is detected, the data access operation indicated by the second indication information is executed to meet the data access requirements of the external device for the data in the storage device.

[0103] For example, the local memory controller of the in-memory computing chip responds to detecting that the second indication information for instructing data access is written in the DB Register, and determines whether the Bank in the in-memory computing chip is in an idle period according to the execution status of the instruction sequence in the CQ Register (such as the type of the currently executed data processing instruction). If so, the data access operation indicated by the second indication information is executed on the Bank. If not, continuous detection is performed, and when an idle period is detected, the data access operation indicated by the second indication information is executed on the Bank to meet the read / write requirements of the external device such as the SOC chip for the data in the in-memory computing chip.

[0104] In this embodiment, by utilizing the idle period characteristic of the operation of the processing unit on the data storage unit in the storage device, during the idle period of the data storage unit, the data access operation required by the external device such as the SOC chip for the data storage unit in the storage device is executed, which can realize meeting the data read / write requirements of the external device such as the SOC chip for the storage device during the local data processing (such as PIM processing) of the storage device, and will not affect the local data processing in the storage device. Therefore, there is no need to perform a mode switch on the storage device such as an in-memory computing chip like LP-DDR, and correspondingly, there is no need to wait all the time before switching back to the normal LP and other conventional read / write modes, thereby improving the data access efficiency of the external device for the storage device in the local data processing (internal data processing) scenario of the storage device and reducing the data access delay of the external device.

[0105] Specifically, based on the execution status information of the data processing instructions stored in the second sub-register unit in the storage device, this embodiment enables an external device to know the execution situation of the data processing instructions in the storage device, and further know the access situation of the data storage unit in the storage device (such as whether it is in a window period / whether it is in an accessed state). When it is known that the data storage unit such as a Bank is in a window period / non-access state, the corresponding data storage unit can be accessed, effectively utilizing the window period feature of the operation of the processing unit on the data storage unit in the storage device, improving the data access efficiency of the external device to the storage device, and reducing the data access delay of the external device.

[0106] See Figure 3 Referring to the composition structure diagram of the control chip shown, the control chip provided in the embodiment of the present application at least includes a second instruction storage unit 21 and a storage controller 22.

[0107] Among them, the second instruction storage unit 21 is used to store multiple data processing instructions to be sent to the storage device at the control chip end.

[0108] Optionally, the second instruction storage unit 21 may include a second queue, which is specifically used to store multiple data processing instructions to be sent to the storage device at the control chip end based on the execution order between the data processing instructions.

[0109] In this embodiment, by adding a second instruction storage unit 21, such as adding a second queue, to the control chip, it is supported to batch store multiple data processing instructions in the control chip, and further support the batch transmission of data processing instructions.

[0110] The storage controller 22 is used to obtain multiple data processing instructions in the second instruction storage unit 21, and based on the batch transmission method, transmit the multiple data processing instructions to the storage device, so that the processing unit in the storage device responds to the first indication information for instructing the execution of the data processing instructions, and executes the operations corresponding to each received data processing instruction to perform data processing on the data stored in the data storage unit of the storage device.

[0111] Optionally, the control chip may be a SOC, and the storage controller 22 may be a DDRC (DDR Controller) in the SOC.

[0112] In addition to the second instruction storage unit 21 and the storage controller 22, optionally, the control chip may further include a processor, such as a Neural Processing Unit (NPU), a Deep Learning Processing Unit (DPU), etc. The number of processors included may be one or more, without limitation.

[0113] In practical applications, when there is a data processing requirement for the processor (such as NPU / DPU) inside the control chip and / or an external processor (such as CPU), and local data processing needs to be performed inside the storage device by means of the storage device (such as performing local PIM processing on a memory-computation integrated chip), each data processing instruction generated can be stored in the second instruction storage unit 21 newly added inside the control chip as needed. For example, when the NPU / DPU inside the SOC generates a series of AI operator instructions that need to be processed by PIM based on AI operation requirements (such as a series of multiplication operation instructions and accumulation operation instructions involved in matrix multiplication), each AI operator instruction can be stored in the second queue newly added on the SOC in the execution order.

[0114] On this basis, the storage controller 22 can obtain multiple data processing instructions in the second instruction storage unit 21, and based on the batch transmission method, transmit the multiple data processing instructions to the storage device. After the subsequent storage device receives the multiple data processing instructions transmitted based on the batch transmission method, it stores them in the first instruction storage unit 12 newly added inside the storage device in the execution order (such as the transmission order), and under the control of the control unit 15 inside the storage device, realizes local processing of the data stored in the data storage unit 11 of the storage device by using the processing unit 13 to execute the operations corresponding to each data processing instruction in the first instruction storage unit 12.

[0115] For example, the DDRC in the SOC obtains each AI operator instruction in the second queue and transmits it in batches to the storage-computing integrated chip. The storage-computing integrated chip stores each received AI operator instruction in the first queue in the order of execution. Subsequently, under the control of the local memory controller of the storage-computing integrated chip, the PIM processing unit of the storage-computing integrated chip executes the operations corresponding to each AI operator instruction in the first queue to implement the required processing of the data in the Bank of the storage-computing integrated chip, such as executing the multiplication and accumulation operations respectively indicated by multiple AI operator instructions. After that, the PIM processing unit can write its operation results to the Bank so that the SOC and other external devices can read and use the operation results. By performing local data processing inside a storage device such as a storage-computing integrated chip, the data processing pressure of an external device such as a SOC can be reduced, and the amount of data transmission between a storage device such as a storage-computing integrated chip and an external device such as a SOC can be reduced, and bandwidth can be saved. For data processing tasks with the characteristics of heavy handling (large amount of data, high transmission time, high bandwidth demand) and light operation (simple operation, such as addition and multiplication), this advantage will be more obvious.

[0116] This embodiment can support batch storage of multiple data processing instructions in the control chip by adding a second instruction storage unit in the control chip, such as adding a second queue, and further supports the control chip to transmit the data processing instructions based on the batch transmission mode. The improvement of the control chip end in this embodiment, combined with the improvement of the storage device end in the above text (such as adding a first instruction storage unit, a first sub-register unit, and a second sub-register unit in the storage device, and matching the functional design of the control unit in the storage device), can realize the transmission of data processing instructions from the control chip to the storage device (such as LP-DDR and other storage and computing integrated chips) through batch transmission, overcome the bandwidth efficiency loss problem existing in the known technology of issuing instructions one by one, improve the transmission efficiency of data processing instructions, avoid bandwidth efficiency loss, and avoid affecting the execution efficiency of data processing instructions in the storage device, thereby improving the execution efficiency of data processing instructions in the storage device.

[0117] In an optional embodiment, the storage controller 22 in the control chip, when transmitting the plurality of data processing instructions to the storage device based on a batch transmission method, is specifically configured to:

[0118] Obtaining the execution status of the data processing instructions in the storage device;

[0119] In response to the execution status satisfying a status condition, the plurality of data processing instructions in the control chip are transmitted to the storage device based on a batch transmission method.

[0120] Optionally, the status condition may be, but is not limited to, set to any one of the following:

[0121] Condition 1: The first instruction storage unit (such as the first queue) is idle.

[0122] If PIM processing is not performed in the in-memory computing chip and the first queue does not contain data processing instructions to be executed.

[0123] Condition 2: The number of data processing instructions that have been executed in the first instruction storage unit reaches a preset number, indicating that it is necessary to further supplement the data processing instructions to be executed to the first instruction storage unit.

[0124] Condition 3: The ratio of the number of data processing instructions that have been executed in the first instruction storage unit to the total number of instructions that the first instruction storage unit can store reaches a preset ratio, indicating that it is necessary to further supplement the data processing instructions to be executed to the first instruction storage unit.

[0125] In this embodiment, when the storage controller 22 (such as DDRC) needs to transmit data processing instructions to the storage device, it can first obtain the execution status of the data processing instructions in the storage device from the second sub-register unit of the storage device, and determine whether the execution status of the data processing instructions meets the status conditions. If the status conditions are met, based on the batch transmission method, multiple data processing instructions in the second instruction storage unit of the control chip are transmitted to the storage device. Otherwise, continuous detection is performed until the execution status of the data processing instructions in the storage device meets the status conditions, and then based on the batch transmission method, multiple data processing instructions in the second instruction storage unit of the control chip are transmitted to the storage device.

[0126] For example, when the DDRC in the SOC needs to transmit data processing instructions to the in-memory computing chip, it can first obtain the execution status of the data processing instructions in the first queue from the CQ Register of the in-memory computing chip, such as which data processing instruction in the first queue is currently being executed or the ratio of the data processing instructions that have been executed to the total number of instructions in the first queue, and determine whether the execution status of the data processing instructions meets the status conditions. If the status conditions are met, based on the batch transmission method, multiple data processing instructions in the second queue of the SOC are transmitted to the in-memory computing chip. Otherwise, continuous detection is performed until the execution status of the data processing instructions in the first queue of the in-memory computing chip meets the status conditions, and then multiple data processing instructions in the second queue of the SOC are transmitted to the in-memory computing chip based on the batch transmission method.

[0127] In this embodiment, by functionally designing the memory controller in the control chip, when it is necessary to transmit data processing instructions to the memory device, the execution status of the data processing instructions in the memory device is obtained, and in response to the execution status satisfying the status condition, multiple data processing instructions are transmitted to the memory device based on the bulk transfer mode. Combined with the improvement on the memory device side in this application, it is possible to control the data transfer between the control chip and the memory device based on the Completion Queue (CQ) sequence mechanism. While being able to improve the transmission efficiency of data processing instructions based on the bulk transfer mode and avoid bandwidth efficiency loss, it can also effectively control the appropriate transmission timing of data processing instructions such as LP-PIM instructions, thereby ensuring the orderly and efficient execution of data processing instructions in the memory device.

[0128] In an alternative embodiment, the memory controller 22 in the control chip is further configured to perform at least one of the following processes 11) and 12):

[0129] 11) Sending first indication information to the memory device to instruct the memory device to execute each received data processing instruction.

[0130] A control chip such as an SOC, in addition to sending multiple data processing instructions to a memory device such as a memory-in-computation chip, can also send first indication information for instructing the execution of each data processing instruction to the memory device such as a memory-in-computation chip as needed.

[0131] Specifically, the sent first indication information can be stored in the first sub-register unit of the memory device, such as stored in the DBRegister, so that the control unit in the memory device can control the processing unit in the memory device to perform operations corresponding to each data processing instruction in the first instruction storage unit such as the first queue based on the first indication information.

[0132] 12) Sending second indication information to the memory device to instruct the memory device to perform a data access operation on the data in the corresponding data storage unit included therein. Wherein, the second indication information is sent to the memory device by the memory controller when it is determined that the data in the data storage unit in the memory device is in a non-access state according to the execution status of the data processing instructions in the memory device.

[0133] When a control chip such as an SOC has a need to access the data stored in a storage device, specifically, the storage controller can be used to determine whether the data storage unit in the storage device is in a window period according to the execution status of the data processing instruction stored in the second sub-register unit in the storage device. If the data storage unit is in a window period, it indicates that the data in the data storage unit is in a non-access state. And when the data storage unit is in a window period, that is, when the data in the data storage unit is in a non-access state, a second indication message for instructing data access can be sent to the storage device. The control unit in the storage device responds to the detection of the second indication message for instructing data access to the storage device and performs the data access operation indicated by the second indication message on the corresponding data processing unit.

[0134] However, it is not limited to this. In other embodiments, when a control chip such as an SOC has a need to access the data stored in a storage device, the storage controller in the control chip can also directly send a second indication message for instructing data access to the storage device. The control unit in the storage device responds to the detection of the second indication message and determines whether the data storage unit in the storage device is in a window period based on the execution status of the data processing instruction in the storage device. And when it is in a window period, that is, when the data in the data storage unit is in a non-access state, the data access operation indicated by the second indication message is performed on the data storage unit.

[0135] The second indication message sent by a control chip such as an SOC to the storage device can be specifically stored in the first sub-register unit of the storage device. For example, it is stored in the DB Register of the memory and computing integrated chip. After the control unit in the storage device detects the second indication message in the first sub-register unit such as the DB Register, specifically during the window period of the data storage unit in the storage device, the data access operation indicated by the second indication message is performed on the data storage unit to meet the data access needs of the control chip such as an SOC for a storage device such as a memory and computing integrated chip.

[0136] In this embodiment, by sending corresponding indication messages to the storage device as needed by the control chip and combining corresponding improvements on the storage device side (such as adding corresponding sub-register units to the storage device and improving the functions of the control unit in the storage device, etc.), the coordination of instruction processing inside the storage device and the interaction between the storage device and the control chip can be ensured, thereby ensuring the efficiency of instruction (data processing instruction) processing inside the storage device and the efficiency of interaction between the storage device and the control chip.

[0137] See Figure 4 , an application example of the solution of this application is provided.

[0138] In this application example, the storage device is LP-DDR and the control chip is SOC. Refer to Figure 5 the schematic diagrams of the composition structures of LP-DDR and SOC provided in the known technology. Compared with the known technology, in this example, a first queue SQ_LP for storing multiple data processing instructions, a first sub-register unit MR(DB) for storing indication information, and a second sub-register unit MR(CQ) for storing status information are added at the LP-DDR end. Optionally, when adding the first queue SQ_LP at the LP-DDR end, specifically, one SQ_LP can be added to each Channel at the LP-DDR end, as Figure 4 shown, and corresponding functional improvements are made to the local memory control unit (control) of LP-DDR. Among them, the memory controller Control can be used as an interface to connect multiple Channels and can provide the required control functions for chips such as LP DDR on each Channel.

[0139] At the same time, a second queue SQ_SOC for storing multiple data processing instructions is added in the SOC, and corresponding functional improvements are made to the DDRC in the SOC. Among them, the XPU in the SOC can include, but is not limited to, NPU and / or DPU, and the DDRphy (Double Data Rate PHY) in the SOC is a physical layer interface for controlling and managing the DDR memory interface.

[0140] Based on the above improvements to LP-DDR and SOC, this example can achieve the transfer of data processing instructions from the SOC to the LP-DDR in a batch transmission manner, without having to transmit data processing instructions one by one, thereby improving the transmission efficiency of data processing instructions, avoiding bandwidth efficiency losses, and at the same time avoiding affecting the execution efficiency of data processing instructions in LP-DDR and improving the execution efficiency of data processing instructions.

[0141] In addition, for the data access requirements of the SOC chip for LP-DDR, the PIM processing unit can utilize the empty window period characteristics of the Bank operation in LP-DDR to execute the data access operations required by the SOC chip during the empty window period of the Bank, thereby improving the data access efficiency of the SOC for LP-DDR in the PIM operation scenario of LP-DDR and reducing the data access latency.

[0142] Regarding the functions of the components in LP-DDR and SOC and the interaction process between LP-DDR and SOC, please refer to the descriptions of the corresponding embodiments of the storage device and the control chip in the previous text, which will not be elaborated here.

[0143] Refer to Figure 6The composition structure diagram of the provided electronic device. The electronic device provided by the embodiments of the present application includes a storage device 10 and a storage controller 20.

[0144] Among them, the storage device 10 includes a data storage unit 11, a first instruction storage unit 12, and a processing unit 13.

[0145] The storage controller 20 is configured to obtain multiple data processing instructions and transmit the multiple data processing instructions to the storage device 10 based on a bulk transfer mode.

[0146] The storage device 10 is configured to receive and store the multiple data processing instructions transmitted by the storage controller 20 based on the first instruction storage unit 12, and in response to the first indication information for instructing the execution of the data processing instruction, perform the operations corresponding to the data processing instruction based on the processing unit 13 to perform data processing on the data stored in the data storage unit 11.

[0147] The first instruction storage unit 12 can be a first queue, and is specifically configured to store multiple data processing instructions transmitted through the bulk transfer mode in the execution order between the data processing instructions at the storage device end.

[0148] In an alternative embodiment, the storage device 10 further includes a register unit and a control unit;

[0149] The register unit includes a first sub-register unit and a second sub-register unit;

[0150] The control unit is configured to, in response to detecting that the first indication information for instructing the execution of the data processing instruction is written in the first sub-register unit, control the processing unit to perform the operations corresponding to the data processing instruction in the first instruction storage unit; and is configured to determine the execution status of the data processing instruction in the first instruction storage unit and write the execution status into the second sub-register unit for providing the execution status to an external device outside the storage device.

[0151] In an alternative embodiment, the control unit is further configured to: in response to detecting that the second indication information for instructing data access to the storage device is written in the first sub-register unit, perform the data access operation indicated by the second indication information on the data storage unit in the storage device;

[0152] Among them, the second indication information is written into the first sub-register unit by the external device when it determines that the data in the data storage unit in the storage device is in a non-access state according to the execution status of the data processing instruction stored in the second sub-register unit.

[0153] In an alternative embodiment, the electronic device further includes a control chip, the storage controller 20 is included in the control chip, and the control chip may further include, but is not limited to, a second instruction storage unit and a processor.

[0154] Optionally, the second instruction storage unit may be a second queue, specifically for storing multiple data processing instructions at the control chip end based on the execution order between the data processing instructions.

[0155] The processor in the control chip may include, but is not limited to, an NPU and / or a DPU, and the number of processors included in the control chip may be one or more.

[0156] For a more detailed description of the components and functions of the storage device in the electronic device and the components and functions of the control chip, please refer to the descriptions of the corresponding embodiments of the storage device and the control chip in the foregoing text, which will not be elaborated here.

[0157] The embodiment of the present application further provides a data processing method for use in a storage device. Refer to Figure 7 the method flowchart shown, and this data processing method includes:

[0158] Step 701, obtain and store multiple data processing instructions transmitted by an external device based on a bulk transfer mode;

[0159] Step 702, in response to first indication information for instructing the execution of the data processing instructions, use the processing unit of the storage device to execute the operations corresponding to the multiple data processing instructions, so as to process the data stored in the data storage unit of the storage device by executing the operations corresponding to each data processing instruction.

[0160] In an alternative embodiment, the using the processing unit in the storage device to execute the multiple data processing instructions includes:

[0161] In response to detecting that the first sub-register unit stores first indication information for instructing the execution of the data processing instructions, control the processing unit to execute the operations corresponding to the multiple data processing instructions;

[0162] wherein, the first sub-register unit is a sub-register unit included in the register unit in the storage device.

[0163] In an alternative embodiment, this data processing method for use in a storage device may further include at least one of the following:

[0164] Determine the execution status of the data processing instructions and write the execution status into a second sub-register unit for providing the execution status to an external device outside the storage device;

[0165] In response to detecting that the second indication information for indicating data access to the storage device is written in the first sub - register unit, perform a data access operation on the data storage unit in the storage device as indicated by the second indication information;

[0166] Wherein, the second indication information is written into the first sub - register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non - access state according to the execution status of the data processing instruction stored in the second sub - register unit; the second sub - register unit is a sub - register unit included in the register unit, and the second sub - register unit is different from the first sub - register unit.

[0167] The data processing method provided in this embodiment corresponds to the storage device disclosed in this application. For related similarities, reference can be made to the description of the corresponding embodiment of the storage device in the foregoing text, and details will not be elaborated here.

[0168] An embodiment of this application also provides a data processing method for use in a control chip. Refer to Figure 8 the method flow chart shown. This data processing method includes:

[0169] Step 801: Obtain multiple data processing instructions to be sent to the storage device;

[0170] Step 802: Based on a batch transfer mode, transfer the multiple data processing instructions to the storage device, so that the processing unit in the storage device, in response to the first indication information for indicating the execution of the data processing instruction, performs operations corresponding to each received data processing instruction to process the data stored in the data storage unit of the storage device.

[0171] In an alternative embodiment, the transferring the multiple data processing instructions to the storage device includes:

[0172] Obtain the execution status of the data processing instruction in the storage device;

[0173] In response to the execution status meeting the status condition, transfer the multiple data processing instructions to the storage device based on a batch transfer mode.

[0174] In an alternative embodiment, this data processing method for use in a control chip may further include at least one of the following:

[0175] Send the first indication information to the storage device to instruct the storage device to control the processing unit to perform operations corresponding to each received data processing instruction;

[0176] Send second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the included data storage unit;

[0177] Among them, the second indication information is sent to the storage device by the storage controller in the control chip when it is determined according to the execution status of the data processing instruction in the storage device that the data in the data storage unit in the storage device is in a non-access state.

[0178] The data processing method provided in this embodiment corresponds to the control chip disclosed in this application. For relevant similarities, reference can be made to the description of the corresponding embodiment of the control chip in the above text, which will not be elaborated here.

[0179] This application embodiment also provides a data processing method for use in an electronic device. Refer to Figure 9 the method flowchart shown. This data processing method includes:

[0180] Step 901, the storage controller obtains multiple data processing instructions and transmits the multiple data processing instructions to the storage device based on a bulk transfer mode;

[0181] Step 902, the storage device receives and stores the multiple data processing instructions transmitted based on the bulk transfer mode based on the included first instruction storage unit, and in response to the first indication information for instructing the execution of the data processing instruction, performs the operation corresponding to the data processing instruction based on the included processing unit to perform data processing on the data in the included data storage unit.

[0182] In an optional implementation manner, the transmitting the multiple data processing instructions to the storage device based on the bulk transfer mode includes:

[0183] The storage controller obtains the execution status of the data processing instruction in the storage device, and in response to the execution status satisfying the status condition, transmits multiple data processing instructions in the control chip to the storage device based on the bulk transfer mode.

[0184] In an optional implementation manner, the data processing method of this embodiment further includes at least one of the following:

[0185] The storage controller sends first indication information to the storage device to instruct the storage device to execute each received data processing instruction;

[0186] The storage controller sends second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding included data storage unit;

[0187] Wherein, the second indication information is sent by the storage controller to the storage device when it determines that the data in the data storage unit in the storage device is in a non-access state according to the execution status of the data processing instruction in the storage device.

[0188] The data processing method provided in this embodiment corresponds to the electronic device disclosed in this application. Further, in essence, it corresponds to the storage device and the control chip included in the electronic device disclosed in this application. For relevant similarities, reference can be made to the descriptions of the corresponding embodiments of the storage device and the control chip in the above text, which will not be elaborated here.

[0189] It should be noted that each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same and similar parts among the embodiments, reference can be made to each other.

[0190] For the convenience of description, when describing the above system or device, various modules or units are described separately according to their functions. Of course, when implementing this application, the functions of each unit can be realized in one or more software and / or hardware.

[0191] From the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution of this application, in essence, or the part that makes a creative contribution, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments of this application.

[0192] Finally, it should also be noted that in this article, relational terms such as first, second, third, and fourth are used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0193] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A storage device, comprising: A first instruction storage unit for storing data processing instructions; A control unit for determining an execution status of a data processing instruction in the first instruction storage unit, so as to provide the execution status to an external device outside the storage device.

2. The storage device according to claim 1, further comprising: A second sub-registration unit; The control unit is specifically configured to write the execution status into the second sub-registration unit, so as to provide the execution status to the external device.

3. The storage device according to claim 2, further comprising: A data storage unit and a first sub-registration unit; The data storage unit is used for storing data; The control unit is further configured to: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-registration unit, perform a data access operation indicated by the second indication information on the data storage unit; Wherein, the second indication information is written into the first sub-registration unit by the external device when it is determined according to the execution status stored in the second sub-registration unit that the data in the data storage unit is in a non-access state.

4. The storage device according to claim 3, further comprising: A processing unit; The control unit is further configured to: in response to detecting that first indication information for indicating execution of a data processing instruction is written in the first sub-registration unit, control the processing unit to perform an operation corresponding to the data processing instruction in the first instruction storage unit, so as to perform data processing on the data in the data storage unit.

5. The storage device according to claim 1, wherein the first instruction storage unit is specifically configured to obtain and store multiple data processing instructions transmitted by the external device through a bulk transfer mode.

6. The storage device according to claim 5, wherein the first instruction storage unit includes a first queue for storing multiple data processing instructions transmitted through a bulk transfer mode based on an execution order between the data processing instructions.

7. A control chip, comprising: A storage controller for obtaining an execution status of a data processing instruction in a storage device; The storage controller is further configured to, when it is determined according to the execution status that the data stored in the storage device is in a non-access state, send second indication information to the storage device to instruct the storage device to perform a data access operation on the data stored in the storage device.

8. The control chip according to claim 7, further comprising: A second instruction storage unit for storing multiple data processing instructions to be sent to the storage device; The storage controller is further configured to obtain multiple data processing instructions in the second instruction storage unit and transmit the multiple data processing instructions to the storage device based on a bulk transfer mode, so that the storage device, in response to first indication information for indicating execution of a data processing instruction, performs operations corresponding to the received data processing instructions to perform data processing on the data stored in the storage device.

9. The storage controller of the control chip according to claim 8, when transmitting the multiple data processing instructions to the storage device based on a bulk transfer mode, is specifically configured to: In response to the execution status satisfying the status condition, based on the batch transfer mode, a plurality of data processing instructions in the control chip are transmitted to the storage device.

10. The control chip according to claim 8, wherein the storage controller is further configured to send first indication information to the storage device to instruct the storage device to execute each received data processing instruction.

11. The control chip according to claim 8, wherein the second instruction storage unit includes a second queue for storing a plurality of data processing instructions to be sent to the storage device based on the execution order between the data processing instructions.

12. An electronic device, comprising a storage controller and a storage device, wherein the storage device includes a first instruction storage unit and a control unit; The storage device is configured to determine the execution status of the data processing instructions in the first instruction storage unit based on the control unit; The storage controller is configured to obtain the execution status, and when it is determined according to the execution status that the data stored in the storage device is in a non-access state, send second indication information to the storage device to instruct the storage device to perform a data access operation on the data stored in the storage device.

13. A data processing method applied to a storage device, the method comprising: Storing data processing instructions; Determining the execution status of the data processing instructions for providing the execution status to an external device other than the storage device.

14. A data processing method applied to a control chip, the method comprising: Obtaining the execution status of the data processing instructions in the storage device; When it is determined according to the execution status that the data stored in the storage device is in a non-access state, sending second indication information to the storage device to instruct the storage device to perform a data access operation on the data stored in the storage device.

15. A data processing method applied to an electronic device, the method comprising: The storage device stores data processing instructions based on the first instruction storage unit and determines the execution status of the data processing instructions in the first instruction storage unit based on the control unit; The storage controller obtains the execution status, and when it is determined according to the execution status that the data stored in the storage device is in a non-access state, sends second indication information to the storage device to instruct the storage device to perform a data access operation on the data stored in the storage device.

16. The data processing method according to claim 15, further comprising: The storage controller obtains a plurality of data processing instructions and transmits the plurality of data processing instructions to the storage device based on the batch transfer mode; The storage device receives and stores the plurality of data processing instructions transmitted based on the batch transfer mode based on the first instruction storage unit, and in response to the first indication information for instructing the execution of the data processing instructions, performs operations corresponding to each received data processing instruction to perform data processing on the data stored in the storage device.

17. The transmitting the plurality of data processing instructions to the storage device based on the batch transfer mode according to claim 16 includes: In response to the execution state satisfying the state condition, based on the batch transfer mode, the multiple data processing instructions are transmitted to the storage device.

18. The data processing method according to claim 16, further comprising: The storage controller sends first indication information to the storage device to instruct the storage device to execute each received data processing instruction.

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