CPLD upgrading method and system based on I2C private communication protocol

Abstract

The invention discloses a CPLD (Complex Programmable Logic Device) upgrading method and system based on an I2C private communication protocol. The method comprises the following steps: writing at least one page of program data into a first on-chip RAM (Random Access Memory) of an FPGA through an SPI (Serial Peripheral Interface); generating a first trigger instruction, controlling a host engine of an I2CMASTER module of the FPGA to start according to the first trigger instruction, extracting at least one page of program data from the first on-chip RAM according to the I2CMASTER, and placing the at least one page of program data on the I2C interface; obtaining an analysis instruction, and writing at least one page of program data into a second on-chip RAM (Random Access Memory) of the CPLD by adopting an I2CSlave module of the CPLD according to the analysis instruction; and generating a second trigger instruction, controlling a host engine of an SPIMASTER module of the CPLD to start according to the second trigger instruction, extracting at least one page of program data from the second on-chip RAM according to the SPIMASTER, burning an internal inherent flash program storage area through an SPI interface until program updating is completed, and transmitting the data to the slave device according to protocol requirements. And the slave device performs data communication with the Flash after caching, and after the Flash is configured, the whole CPLD upgrading process is completed.

Description

Technical Field

[0001] The present invention belongs to the technical field of CPLD upgrading, and particularly relates to a CPLD upgrading method and system based on the I2C private communication protocol. Background Art

[0002] Typical CPLD upgrading is achieved through the SPI or JTAG interface in a point-to-point manner, that is, one SPI host or JTAG host can only upgrade one CPLD. These point-to-point methods will result in a large number of backplane traces and affect the efficiency of CPLD upgrading. Summary of the Invention

[0003] The present invention provides a CPLD upgrading method, system and readable storage medium based on the I2C private communication protocol to solve the technical problem that the point-to-point method will result in a large number of backplane traces.

[0004] In a first aspect, the present invention provides a CPLD upgrading method based on the I2C private communication protocol, including:

[0005] Obtain a CPLD program file in the eMMC, where the CPLD program file contains at least one page of program data;

[0006] Write the at least one page of program data into the first on-chip RAM of the FPGA through the SPI interface;

[0007] Generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, take out the at least one page of program data from the first on-chip RAM according to the I2C_MASTER, and place the at least one page of program data on the I2C interface;

[0008] Obtain a parsing instruction, and write the at least one page of program data into the second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction;

[0009] Generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, take out the at least one page of program data from the second on-chip RAM according to the SPI_MASTER, and burn the internal inherent flash program storage area through the SPI interface until the program update is completed.

[0010] In a second aspect, the present invention provides a CPLD upgrading system based on the I2C private communication protocol, including:

[0011] An acquisition module, configured to acquire a CPLD program file in an eMMC, where the CPLD program file contains at least one page of program data;

[0012] A first writing module, configured to write the at least one page of program data into a first on-chip RAM of an FPGA through an SPI interface;

[0013] A generation module, configured to generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, take out the at least one page of program data from the first on-chip RAM according to the I2C_MASTER, and place the at least one page of program data on the I2C interface;

[0014] A second writing module, configured to obtain a parsing instruction, and write the at least one page of program data into a second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction;

[0015] An update module, configured to generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, take out the at least one page of program data from the second on-chip RAM according to the SPI_MASTER, and burn an internal inherent flash program storage area through an SPI interface until the program update is completed.

[0016] In a third aspect, an electronic device is provided, which includes: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the steps of the CPLD upgrade method based on the I2C private communication protocol according to any embodiment of the present invention.

[0017] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the program instructions are executed by a processor, the processor is enabled to execute the steps of the CPLD upgrade method based on the I2C private communication protocol according to any embodiment of the present invention.

[0018] For the CPLD upgrade method and system based on the I2C private communication protocol of the present application, the online upgrade of the CPLD device is initiated by the master device, data is transmitted to the slave device according to the protocol requirements, the slave device caches the data and then communicates with the Flash, and after the Flash is configured, the entire CPLD upgrade process is completed. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Flowchart of a CPLD upgrade method based on the I2C private communication protocol provided by an embodiment of the present invention;

[0021] Figure 2 Schematic diagram of the circuit composition of CPLD upgrade based on the I2C private communication protocol in a specific embodiment of the present invention;

[0022] Figure 3 Flowchart of an I2C master device writing data to Flash in a specific embodiment of the present invention;

[0023] Figure 4 Flowchart of an I2C master device writing and then reading data to Flash in a specific embodiment of the present invention;

[0024] Figure 5 Flowchart of an I2C master device polling for interrupts in a specific embodiment of the present invention;

[0025] Figure 6 Timing diagram of an I2C master device writing data to Flash in a specific embodiment of the present invention;

[0026] Figure 7 Schematic diagram of the private SPI communication frame structure adopted by the SPI_Slave module of an FPGA in a specific embodiment of the present invention;

[0027] Figure 8 Block diagram of the structure of a CPLD upgrade system based on the I2C private communication protocol provided by an embodiment of the present invention;

[0028] Figure 9 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention fall within the scope of protection of the present invention.

[0030] Please refer to Figure 1 , which shows a flowchart of a CPLD upgrade method based on the I2C private communication protocol of the present application.

[0031] As Figure 1 shown, the CPLD upgrade method based on the I2C private communication protocol specifically includes the following steps:

[0032] Step S101, obtain a CPLD program file in the eMMC, where the CPLD program file contains at least one page of program data;

[0033] Step S102, write the at least one page of program data into the first on-chip RAM of the FPGA through the SPI interface;

[0034] Step S103, generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, take out the at least one page of program data from the first on-chip RAM according to the I2C_MASTER, and place the at least one page of program data on the I2C interface;

[0035] Step S104, obtain a parsing instruction, and write the at least one page of program data into the second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction;

[0036] Step S105, generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, take out the at least one page of program data from the second on-chip RAM according to the SPI_MASTER, and burn the internal inherent flash program storage area through the SPI interface until the program update is completed.

[0037] In this embodiment, the method of the present application initiates the online upgrade of the CPLD device by the master device, transfers data to the slave device according to the protocol requirements, and after the slave device caches and communicates with the Flash, the entire CPLD upgrade process is completed. Using the I2C interface and the point-to-multipoint method, according to the slot number as the I2C slave addr, the program upgrade of the CPLD in 16 slots is realized, reducing the backplane wiring.

[0038] In a specific embodiment, the circuit composition of the present invention is as Figure 2As shown in the figure, the CPLD program of 16 branch boards is upgraded by the main control board. The I2C bus interface of the main control board acts as the master device, and the I2C bus interface of the branch board acts as the slave device. The online upgrade of the CPLD device is initiated by the master device, and the data is transmitted to the slave device according to the protocol requirements. After the slave device caches the data, it communicates with the Flash. After the Flash is configured, the entire CPLD upgrade process is completed.

[0039] The flowchart of the I2C master device writing data to the Flash in the present invention is as Figure 3 shown. First, the module is initialized, and the configuration command 0xA1 is sent. After receiving this command, the SPI interface is configured according to the configured value. After completion, the command 0xA2 is sent. After receiving this command, the I2C data is cached in the RAM, and then the data is written to the Flash. After the Flash writing is completed, an interrupt signal is generated, and finally, the I2C master device ends writing data to the Flash.

[0040] The flowchart of the I2C master device writing data to the Flash first and then reading data in the present invention is as Figure 4 shown. First, the module is initialized, and the configuration command 0xA1 is sent. After receiving this command, the SPI interface is configured according to the configured value. After completion, the command 0xA2 is sent. After receiving this command, the I2C data is cached in the RAM, and then the data is written to the Flash. After the Flash writing is completed, an interrupt signal is generated. At this time, the status sends the command 0xA3 to clear the interrupt. After the interrupt is cleared, the I2C performs a read data operation. After the read operation is completed, finally, it waits for whether the I2C performs read and write data operations again.

[0041] The flowchart of the I2C master device polling interrupt in the present invention is as Figure 5 shown. First, the module is initialized, and the configuration command 0xA1 is sent. After receiving this command, the SPI interface is configured according to the configured value. After completion, the command 0xA2 is sent. After receiving this command, the I2C writes data to the Flash. After writing the data, the command 0xA4 is sent. After receiving the command, the I2C starts to read the interrupt. If no interrupt signal is read, the interrupt signal is continuously read. If an interrupt signal is read, it waits for whether the I2C reads the interrupt again.

[0042] The timing diagram of the I2C master device writing data to the Flash in the present invention is as Figure 7As shown in the figure. Among them, 0x50 + slot_id is the slave addr. I2C_Slave matches according to the slot number of the branch board. When there is no match, the slave device responds with Not Ack. PageAddr is the page address of the Flash; Addr2, Addr1, and Addr0 form the 24-bit storage unit address of the Flash; Data0 represents the first data sent by the I2C master device to the Flash, and Data255 represents the 256th data sent by the I2C master device to the Flash.

[0043] Main control board process:

[0044] The CPLD program file is stored in the eMMC.

[0045] The CPU reads 1 page of data from the eMMC and writes it into the on-chip RAM of the FPGA through the SPI interface.

[0046] The CPU triggers the start of the I2C_MASTER host engine of the FPGA to start transmitting data.

[0047] I2C_MASTER fetches the data from the on-chip RAM and places it on the I2C interface.

[0048] After one page of transmission is completed, the CPU initiates the transmission of the next page of data. This continues until the entire file transmission is completed.

[0049] Branch board process:

[0050] The I2C_SLAVE slave of the CPLD parses the command and stores the data in the on-chip RAM cache of the CPLD.

[0051] The CPLD triggers the start of the SPI_MASTER host engine to start transmitting data.

[0052] SPI_MASTER fetches the data from the on-chip RAM and burns the internal inherent flash program storage area through the SPI interface.

[0053] After one page of transmission is completed, the CPU initiates the transmission of the next page of data. This continues until the program update is completed.

[0054] In the present invention, the SPI_Slave module of the FPGA adopts a private SPI communication frame structure, as Figure 6 shown. The SPI operates in mode 0, with a rate of 10 Mbps, and supports continuous read and write operations. The frame structure consists of 1-bit read / write flag bit + 31-bit starting address + N * 32-bit data.

[0055] In the present invention, the RAM of the FPGA is used to store data. The CPU first writes the program file into the RAM through the SPI interface.

[0056] In the present invention, the ctrl_reg register of the FPGA is used to specify parameters of the I2C_Master such as data length, slave address, starting address, etc. Among them, the slave address is used to distinguish 16 slot branch boards. The CPU configures the ctrl_reg register to trigger the I2C_Master to fetch data from the RAM and transfer it to the branch board through the I2C interface.

[0057] In the present invention, the I2C_Master module of the FPGA is used for I2C framing. The I2C_Master module includes configuring the SPI working mode, writing data mode, clearing interrupts, and reading interrupts.

[0058] In the present invention, the I2C_Slave module of the CPLD is used for I2C deframing, parsing commands, receiving data, and storing it in the internal RAM of the CPLD.

[0059] In the present invention, the SPI_Master module of the CPLD is used to fetch data from the internal RAM of the CPLD and write it into the inherent Flash program storage area of the CPLD.

[0060] The CPU chip model adopted in the present invention is: RK3528.

[0061] The FPGA chip model adopted in the present invention is: XC7A50TFGG484.

[0062] The CPLD chip model adopted in the present invention is: EF2L45BG256B.

[0063] It should be noted that the meanings of the above partial English abbreviations are explained as follows:

[0064] FPGA, Field-Programmable Gate Array, field programmable gate array;

[0065] CPLD, Complex Programmable Logic Device, complex programmable logic device;

[0066] SPI, Serial Peripheral Interface, serial peripheral interface;

[0067] IIC (I2C), Inter-Integrated Circuit, integrated circuit bus;

[0068] eMMC, Embedded Multi Media Card, embedded multimedia card.

[0069] Please refer to Figure 8 , which shows a block diagram of a CPLD upgrade system based on the I2C private communication protocol of the present application.

[0070] As shown in Figure 8 , the CPLD upgrade system 200 includes an acquisition module 210, a first writing module 220, a generation module 230, a second writing module 240, and an update module 250.

[0071] Among them, the acquisition module 210 is configured to acquire a CPLD program file in the eMMC, and the CPLD program file contains at least one page of program data; the first writing module 220 is configured to write the at least one page of program data into the first on-chip RAM of the FPGA through the SPI interface; the generation module 230 is configured to generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, take out the at least one page of program data from the first on-chip RAM according to the I2C_MASTER, and place the at least one page of program data on the I2C interface; the second writing module 240 is configured to acquire a parsing instruction, and write the at least one page of program data into the second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction; the update module 250 is configured to generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, take out the at least one page of program data from the second on-chip RAM according to the SPI_MASTER, and burn the internal inherent flash program storage area through the SPI interface until the program update is completed.

[0072] It should be understood that Figure 8 The modules described in Figure 1 correspond to the respective steps in the method described with reference to Figure 8 . Therefore, the operations, features, and corresponding technical effects described above for the method also apply to the modules in

[0073] and will not be elaborated herein.

[0074] In some other embodiments, the embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored. When the program instructions are executed by a processor, the processor executes the CPLD upgrade method based on the I2C private communication protocol in any of the above method embodiments;

[0075] Obtain the CPLD program file in the eMMC, where the CPLD program file contains at least one page of program data;

[0076] Write the at least one page of program data into the first on-chip RAM of the FPGA through the SPI interface;

[0077] Generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, retrieve the at least one page of program data from the first on-chip RAM according to the I2C_MASTER, and place the at least one page of program data on the I2C interface;

[0078] Obtain a parsing instruction, and write the at least one page of program data into the second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction;

[0079] Generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, retrieve the at least one page of program data from the second on-chip RAM according to the SPI_MASTER, and burn the internal inherent flash program storage area through the SPI interface until the program update is completed.

[0080] A computer-readable storage medium may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the CPLD upgrade system based on the I2C private communication protocol, etc. In addition, the computer-readable storage medium may include high-speed random access memory, and may also include memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the computer-readable storage medium may optionally include a memory remotely provided with respect to the processor, and these remote memories may be connected to the CPLD upgrade system based on the I2C private communication protocol through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0081] Figure 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention, as Figure 9 shown. The device includes: a processor 310 and a memory 320. The electronic device may further include: an input device 330 and an output device 340. The processor 310, the memory 320, the input device 330, and the output device 340 may be connected through a bus or other means, Figure 9Take the bus connection as an example. The memory 320 is the above-mentioned computer-readable storage medium. The processor 310 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 320, that is, implements the CPLD upgrade method based on the I2C private communication protocol in the above method embodiment. The input device 330 can receive input digital or character information, and generate key signal inputs related to user settings and function control of the CPLD upgrade system based on the I2C private communication protocol. The output device 340 can include display devices such as a display screen.

[0082] The above electronic device can execute the method provided by the embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided by the embodiment of the present invention.

[0083] As an implementation manner, the above electronic device is applied to a CPLD upgrade system based on the I2C private communication protocol and is used for a client, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0084] Obtain a CPLD program file in the eMMC, where the CPLD program file contains at least one page of program data;

[0085] Write the at least one page of program data into the first internal RAM of the FPGA through the SPI interface;

[0086] Generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, and according to the I2C_MASTER, take out the at least one page of program data from the first internal RAM and place the at least one page of program data on the I2C interface;

[0087] Obtain a parsing instruction, and according to the parsing instruction, use the I2C_Slave module of the CPLD to write the at least one page of program data into the second internal RAM of the CPLD;

[0088] Generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, and according to the SPI_MASTER, take out the at least one page of program data from the second internal RAM and burn it into the internally inherent flash program storage area through the SPI interface until the program update is completed.

[0089] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiments.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for upgrading a CPLD based on the I2C private communication protocol, characterized in that, including: obtaining a CPLD program file in an eMMC, where the CPLD program file contains at least one page of program data; writing the at least one page of program data into a first internal RAM of an FPGA through an SPI interface; generating a first trigger instruction, controlling a host engine of an I2C_MASTER module of the FPGA to start according to the first trigger instruction, taking out the at least one page of program data from the first internal RAM by the I2C_MASTER, and placing the at least one page of program data on an I2C interface; obtaining a parsing instruction, and writing the at least one page of program data into a second internal RAM of the CPLD by using an I2C_Slave module of the CPLD according to the parsing instruction; generating a second trigger instruction, controlling a host engine of an SPI_MASTER module of the CPLD to start according to the second trigger instruction, taking out the at least one page of program data from the second internal RAM by the SPI_MASTER, and burning an internal inherent flash program storage area through the SPI interface until the program update is completed.

2. The CPLD upgrade method based on the I2C private communication protocol according to claim 1, wherein The burning of the internal inherent flash program storage area through the SPI interface includes: initializing the module, sending a configuration command 0xA1, configuring the SPI interface according to the configured value after receiving the command 0xA1, sending a command 0xA2 after completion, caching I2C data into the RAM after receiving the command 0xA2, then starting to write data to the Flash, generating an interrupt signal after writing the Flash is completed, and finally ending the writing of data from the I2C master device to the Flash.

3. A method for upgrading a CPLD based on the I2C private communication protocol according to claim 2, characterized in that, After the writing of the Flash is completed, generating an interrupt signal includes: initializing the module, sending a configuration command 0xA1, configuring the SPI interface according to the configured value after receiving the command 0xA1, sending a command 0xA2 after completion, writing data from the I2C to the Flash after receiving the command 0xA2, sending a command 0xA4 after writing the data, starting to read the interrupt by the I2C after receiving the command 0xA4, if no interrupt signal is read, continue to read the interrupt signal, if an interrupt signal is read, wait for whether the I2C reads the interrupt again.

4. A CPLD upgrade method based on the I2C private communication protocol according to claim 1, characterized in that The I2C_Master module of the FPGA is used for I2C framing, and the I2C_Master module includes configuring the SPI working mode, writing data mode, clearing interrupts, and reading interrupts.

5. A method for upgrading a CPLD based on the I2C private communication protocol according to claim 1, characterized in that The I2C_Slave module of the CPLD is used for I2C deframing, parsing commands, and receiving data and storing it in a second internal RAM of the CPLD.

6. A method for upgrading a CPLD based on the I2C private communication protocol according to claim 1, wherein The SPI_MASTER module of the CPLD is used for taking out data from a second internal RAM of the CPLD and writing it into an inherent Flash program storage area of the CPLD.

7. A CPLD upgrade system based on the I2C private communication protocol, characterized in that, including: an obtaining module configured to obtain a CPLD program file in an eMMC, where the CPLD program file contains at least one page of program data; a first writing module configured to write the at least one page of program data into a first internal RAM of an FPGA through an SPI interface; A generation module, configured to generate a first trigger instruction, control the host engine of the I2C_MASTER module of the FPGA to start according to the first trigger instruction, retrieve the at least one page of program data from the first on-chip RAM by the I2C_MASTER, and place the at least one page of program data on the I2C interface; A second writing module, configured to obtain a parsing instruction, and write the at least one page of program data into the second on-chip RAM of the CPLD by using the I2C_Slave module of the CPLD according to the parsing instruction; An update module, configured to generate a second trigger instruction, control the host engine of the SPI_MASTER module of the CPLD to start according to the second trigger instruction, retrieve the at least one page of program data from the second on-chip RAM by the SPI_MASTER, and burn the internal inherent flash program storage area through the SPI interface until the program update is completed.

8. An electronic device, characterized in that, Comprising: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the method according to any one of claims 1 to 6 is implemented.

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