Parallel computing processor and electronic device

Abstract

The present invention provides a parallel computing processor and electronic device, comprising a write control unit, a selector, N transmit queues, N state machines, and N pre-decoding units. The input end of the write control unit and the first input end of the selector are connected to a first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th transmit queue, the output end of the i-th transmit queue is connected to the second input end of the selector, the output end of the selector is connected to a second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register. The N state machines and the N pre-decoding units are further connected to a decoding module, which is further connected to the second register. N microcode instructions are executed in parallel, thereby improving the operating efficiency of the processor.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a parallel computing processor and electronic equipment. Background Art

[0002] As an emerging computing architecture, RISC-V is becoming a key driver of AI computing power. With its open and flexible nature, RISC-V provides chip designers with significant freedom to customize AI accelerators to meet specific needs. Its streamlined and highly scalable instruction set allows designers to add custom instruction set extensions to improve AI computing performance and efficiency.

[0003] The RISC-V computing architecture, due to its simplicity, openness, flexibility, low power consumption, modularity, and scalability, allows for proprietary implementations of AI computing through instruction extensions and customization. In this context, how to significantly improve RISC-V processor performance without significantly increasing hardware complexity has become a difficult problem for those skilled in the art. Summary of the Invention

[0004] The object of the present invention is to provide a parallel computing processor and an electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a parallel computing processor, the parallel computing processor comprising a state monitoring module, a first register, a second register, and a decoding module, the state monitoring module comprising: a write control unit, a selector, N transmit queues, N state machines, and N pre-decoding units;

[0007] An input terminal of the write control unit and a first input terminal of the selector are connected to the first register, an i-th control terminal of the write control unit, an i-th control terminal of the selector, and a first input terminal of an i-th pre-decoding unit are connected to a first terminal of an i-th state machine, an i-th output terminal of the write control unit is connected to an input terminal of an i-th transmit queue, an output terminal of the i-th transmit queue is connected to a second input terminal of the selector, an output terminal of the selector is connected to the second register and second input terminals of N pre-decoding units, and output terminals of the N pre-decoding units are connected to the second register, 1≤i≤N;

[0008] The N state machines and the N pre-decoding units are further connected to the decoding module, and the decoding module is further connected to the second register.

[0009] Optionally, the i-th state machine is used to send a status identifier of the i-th microcode instruction in the i-th issue queue to the selector and the write control unit, and send an execution count and a status identifier of the i-th microcode instruction to the i-th pre-decoding unit;

[0010] Wherein, the state flag indicates whether the i-th microcode instruction is in a valid state;

[0011] When all microcode instructions are in an invalid state, the write control unit and the selector are used to read the most recently written and valid target instruction from the first register, where the target instruction includes N microcode instructions;

[0012] The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th issue queue;

[0013] When any microcode instruction is in a valid state, the write control unit and the selector stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th issue queue;

[0014] The selector is used to write the read N microcode instructions into the second register, write the i-th microcode instruction into the i-th pre-decoding unit, and update the N status identification bits in the second register, wherein the i-th status identification bit corresponds to the i-th microcode instruction, and in a safe cycle, the N status identification bits are all in a valid state, and in a non-safe cycle, the i-th status identification bit is the same as the state identification of the i-th microcode instruction issued by the i-th state machine in the current clock cycle;

[0015] The i-th pre-decoding unit is configured to receive a splitting requirement indication sent by the decoding module in the current clock cycle, and obtain i-th pre-decoding information corresponding to the i-th microcode instruction received based on the splitting requirement indication, the number of times the i-th microcode instruction has been executed, and the status flag, wherein the i-th pre-decoding information includes an instruction type, a source register address, and a destination register address;

[0016] The i-th pre-decoding unit is configured to write the obtained i-th pre-decoding information into the second register.

[0017] Optionally, when the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in a valid state, the i-th pre-decoding unit is configured to obtain i-th pre-decoding information corresponding to the i-th microcode instruction it has received, based on the number of times the i-th microcode instruction has been executed;

[0018] When the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction;

[0019] When the splitting requirement indication indicates that splitting is not required, the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives when the i-th microcode instruction sent by the i-th state machine is in a valid state.

[0020] Optionally, the parallel computing processor further includes a third register, and the decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units;

[0021] The first end of the i-th decoding unit is connected to the first end of the i-th state machine, the second ends of the N decoding units are connected to the second register, and the output ends of the N decoding units are all connected to the microcode scoreboard and the third register;

[0022] The register file unit and the hazard check unit are both connected to the second register, the register file unit is further connected to the third register, and the hazard check unit is further connected to the microcode scoreboard and N state machines;

[0023] The i-th state machine is further configured to send the number of times the i-th microcode instruction has been executed to the i-th decoding unit;

[0024] If the i-th state flag in the second register is in a valid state in the current clock cycle, the i-th decoding unit is used to read the i-th microcode instruction written in the second register in the previous clock cycle, and decode it in combination with the number of times the i-th microcode instruction has been executed to obtain i-th decoding information, send the i-th decoding information to the microcode scoreboard and the third register, and send the number of instruction splits corresponding to the i-th microcode instruction to the i-th state machine;

[0025] The i-th decoding information includes the instruction split number, instruction type, destination register address, operation action, execution cycle number and immediate value corresponding to the i-th microcode instruction;

[0026] The microcode scoreboard is used to store risk-related information, wherein the risk-related information includes the instruction type, destination register address and execution cycle number corresponding to the microcode instruction;

[0027] The hazard checking unit is configured to read, in a current clock cycle, the i-th pre-decoded information written in the second register in the previous clock cycle, and query the microcode scoreboard based on the i-th pre-decoded information to determine whether a data hazard and a structure hazard exist, and send a hazard indication signal to the i-th state machine;

[0028] If the i-th pre-decoded information has a data hazard or a structural hazard, the hazard indication signal is a hazard signal; if the i-th pre-decoded information does not have a data hazard or a structural hazard, the hazard indication signal is a non-hazard signal;

[0029] The register file unit is configured to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0030] Optionally, the i-th state machine is used to update the number of times the i-th microcode instruction stored therein has been executed according to the hazard indication signal received in the previous clock cycle, and update the state threshold according to the number of instruction splits received in the previous clock cycle;

[0031] The i-th state machine is used to determine the state identifier of the i-th microcode instruction according to the updated number of executions and the state threshold.

[0032] Optionally, the i-th decoding unit is used to send a splitting requirement indication indicating that splitting is required to the i-th pre-decoding unit when it is determined that the number of instruction splits of the i-th microcode instruction is greater than 1; when the i-th microcode instruction changes from a valid state to an invalid state, or when the number of times the i-th microcode instruction has been executed is equal to its corresponding state threshold, send a splitting requirement indication indicating that splitting is not required to the i-th pre-decoding unit.

[0033] Optionally, the microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard, and a vector scoreboard, and the register file unit includes a fixed-point register file, a floating-point register file, and a vector register file;

[0034] The output terminals of the N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are further connected to the third register; the hazard check unit is further connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard;

[0035] When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store risk-related information in the i-th decoding information;

[0036] When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store risk-related information in the i-th decoding information;

[0037] When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store hazard related information in the i-th decoding information;

[0038] When the relevant register in the i-th pre-decoding information is a fixed-point register, the hazard checking unit is configured to query the fixed-point scoreboard to determine whether a data hazard and a structure hazard exist, and generate a hazard indication signal, wherein the relevant register is any one of the destination register and one or more source registers in the i-th pre-decoding information;

[0039] When the relevant register in the i-th pre-decoding information is a floating-point register, the hazard checking unit is used to query the floating-point scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal;

[0040] When the relevant register in the i-th pre-decoding information is a vector register, the hazard checking unit is used to query the vector scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal;

[0041] When the source register in the i-th pre-decoding information includes a fixed-point register, the fixed-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information;

[0042] When the source register in the i-th pre-decoding information includes a floating-point register, the floating-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information;

[0043] When the source register in the i-th pre-decoding information includes a vector register, the vector register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0044] Optionally, the parallel operation processor further includes an operation module and a fourth register, and the operation module is connected to the third register and the fourth register respectively;

[0045] The operation module is used to read the decoding information and source data written by the third register in the previous clock cycle, and perform corresponding operations based on them, and send the obtained operation results and the corresponding destination register address to the fourth register for call by the back-end module.

[0046] Optionally, the operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units, and N vector arithmetic logic units;

[0047] When the instruction type in the i-th decoding information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is used to perform operation processing on the source data corresponding to the i-th decoding information to obtain an i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register;

[0048] When the instruction type in the i-th decoding information is a floating-point instruction, the i-th floating-point arithmetic logic unit is used to perform operation processing on the source data corresponding to the i-th decoding information to obtain an i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register;

[0049] When the instruction type in the i-th decoding information is a vector instruction, the i-th vector arithmetic logic unit is used to perform calculations on the source data corresponding to the i-th decoding information to obtain the i-th calculation result, and send the i-th calculation result and the corresponding destination register address to the fourth register.

[0050] In a second aspect, an embodiment of the present invention provides an electronic device comprising the above-mentioned parallel computing processor.

[0051] Compared to the prior art, embodiments of the present invention provide a parallel computing processor and electronic device. The parallel computing processor includes a state monitoring module, a first register, a second register, and a decoding module. The state monitoring module includes: a write control unit, a selector, N transmit queues, N state machines, and N pre-decoding units. The input end of the write control unit and the first input end of the selector are connected to the first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th transmit queue. The output end of the i-th transmit queue is connected to the second input end of the selector. The output end of the selector is connected to the second register and the second input ends of the N pre-decoding units. The output ends of the N pre-decoding units are connected to the second register, where 1≤i≤N. The N state machines and the N pre-decoding units are further connected to the decoding module, which is further connected to the second register. N microcode instructions can be executed in parallel, thereby improving the operating efficiency of the processor.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 This is a schematic diagram of the structure of a status monitoring module provided by an embodiment of the present invention.

[0055] Figure 2This is one of the structural diagrams of the decoding module provided in an embodiment of the present invention.

[0056] Figure 3 This is a second structural diagram of the decoding module provided in an embodiment of the present invention.

[0057] Figure 4 A schematic diagram of the structure of a computing module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0060] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0061] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0062] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0063] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0064] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0065] The embodiment of the present invention provides a parallel operation processor, which includes a state monitoring module, a first register, a second register and a decoding module. Figure 1 , Figure 1 This is a schematic diagram of the structure of a status monitoring module provided by an embodiment of the present invention.

[0066] The status monitoring module includes: a write control unit, a selector, N transmit queues, N state machines and N pre-decoding units. In the drawings of the embodiments of the present invention, N is 4 as an example, but this is not a limitation, and N≥2.

[0067] The input end of the write control unit and the first input end of the selector are connected to the first register, the i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine, the i-th output end of the write control unit is connected to the input end of the i-th transmission queue, the output end of the i-th transmission queue is connected to the second input end of the selector, the output end of the selector is connected to the second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register, 1≤i≤N.

[0068] It should be noted that the first register may be used to store instructions sent by a higher-level module (eg, an instruction fetching module).

[0069] The N state machines and the N pre-decoding units are further connected to the decoding module, and the decoding module is further connected to the second register.

[0070] exist Figure 1 On the basis of the working logic of the parallel operation processor, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0071] The i-th state machine is used to send the status identifier of the i-th microcode instruction in the i-th issue queue to the selector and the write control unit, and send the number of times the i-th microcode instruction has been executed and the status identifier to the i-th pre-decoding unit.

[0072] Among them, the status identifier indicates whether the i-th microcode instruction is in a valid state. If it is in a valid state, it means that the i-th microcode instruction in the i-th transmit queue needs to continue to be executed. If it is in an invalid state, it means that the i-th microcode instruction in the i-th transmit queue has been executed.

[0073] In some scenarios, the i-th microcode instruction corresponds to multiple destination registers. The i-th microcode instruction needs to be executed once for each destination register. The total number of executions of the i-th microcode instruction is the same as the number of destination registers to which it corresponds. The number of executions of the i-th microcode instruction can be counted using a counter. It should be noted that the execution result of the microcode instruction needs to be written to its corresponding destination register. When the i-th microcode instruction is in an invalid state, the corresponding execution count is reset to zero.

[0074] When all microcode instructions are in an invalid state, the write control unit and the selector recognize that the current clock cycle is a safe cycle, and the write control unit and the selector are used to read the most recently written and valid target instruction from the first register, where the target instruction includes N microcode instructions.

[0075] The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th issue queue.

[0076] When any microcode instruction is in a valid state, the write control unit and the selector recognize that the current clock cycle is a non-safe cycle, stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th transmit queue.

[0077] The selector is used to write the N microcode instructions read into the second register, write the i-th microcode instruction into the i-th pre-decoding unit, and update the N status flags in the second register, where the i-th status flag corresponds to the i-th microcode instruction. During a safe cycle (and there is a valid instruction in the first register), the N status flags are all in a valid state. During a non-safe cycle, the i-th status flag is the same as the status flag of the i-th microcode instruction issued by the i-th state machine in the current clock cycle.

[0078] Among them, the safe cycle is the clock cycle in which all microcode instructions are in an invalid state, and the unsafe cycle is the clock cycle in which any microcode instruction is in a valid state.

[0079] The i-th pre-decoding unit is used to receive a splitting requirement indication sent by the decoding module (specifically, the i-th decoding unit) in the current clock cycle, where the splitting requirement indication is used to indicate whether the i-th microcode instruction in the current clock cycle needs to be split when pre-decoding is performed, and obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives based on the splitting requirement indication, the number of times the i-th microcode instruction has been executed, and the status identifier, where the i-th pre-decoding information includes the instruction type, the source register address, and the destination register address.

[0080] The i-th pre-decoding unit is configured to write the obtained i-th pre-decoding information into the second register.

[0081] The decoding module can read the data in the second register to complete the decoding work.

[0082] In the parallel computing processor provided by the embodiment of the present invention, N microcode instructions can be executed in parallel, thereby improving the operating efficiency of the processor.

[0083] On the basis of the foregoing, regarding how the i-th pre-decoding unit obtains the i-th pre-decoding information, the embodiment of the present invention further provides an optional implementation manner, which is referred to below.

[0084] When the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in a valid state, the i-th pre-decoding unit is used to obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it has received in combination with the number of times the i-th microcode instruction has been executed.

[0085] It should be noted that the i-th pre-decoding unit may determine the source register address and the destination register address in the i-th microcode instruction based on the execution count of the i-th microcode instruction + 1, and update the value according to the count after +1 to generate the i-th pre-decoding information.

[0086] It should be understood that after entering the current clock cycle, the i-th pre-decoding unit must first receive the splitting requirement indication fed back by the decoding module, receive the number of times the i-th microcode instruction has been executed and the status identifier sent by the i-th state machine, and then perform pre-decoding.

[0087] When the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction.

[0088] When the splitting requirement indication indicates that splitting is not required, the number of times the i-th microcode instruction sent by the i-th state machine has been executed is ignored, and the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives when the i-th microcode instruction sent by the i-th state machine is in a valid state.

[0089] By performing pre-decoding and obtaining corresponding pre-decoding information, the operating efficiency of the processor can be improved and clock cycles can be saved.

[0090] Regarding the structure of the decoding module, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 This is one of the structural diagrams of the decoding module provided in an embodiment of the present invention.

[0091] The parallel operation processor further includes a third register, and the decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units.

[0092] The first end of the i-th decoding unit is connected to the first end of the i-th state machine, the second ends of the N decoding units are connected to the second register, and the output ends of the N decoding units are all connected to the microcode scoreboard and the third register.

[0093] The register file unit and the hazard check unit are both connected to the second register. The register file unit is further connected to the third register. The hazard check unit is further connected to the microcode scoreboard and the N state machines.

[0094] The i-th state machine is further configured to send the number of times the i-th microcode instruction has been executed to the i-th decoding unit.

[0095] If the i-th state flag in the second register is in a valid state in the current clock cycle, the i-th decoding unit is used to read the i-th microcode instruction written in the second register in the previous clock cycle, and decode it in combination with the number of times the i-th microcode instruction has been executed (sent in the current clock cycle) to obtain the i-th decoding information, send the i-th decoding information to the microcode scoreboard and the third register, and send the number of instruction splits corresponding to the i-th microcode instruction to the i-th state machine.

[0096] The i-th decode information includes the instruction split number, instruction type, destination register address, operation (addition, subtraction, multiplication, division, etc.), execution cycle count (the number of clock cycles required to complete execution of the microcode instruction), and immediate value corresponding to the i-th microcode instruction. The i-th decode unit is configured to determine the destination register address of the i-th microcode instruction based on the number of times the i-th microcode instruction has been executed. It is understood that the only part of the i-th decode information that changes with the number of times the i-th microcode instruction has been executed is the destination register address of the i-th microcode instruction.

[0097] The microcode scoreboard is used to store hazard-related information, wherein the hazard-related information includes the instruction type, destination register address, and execution cycle number corresponding to the microcode instruction.

[0098] The instruction type and the number of execution cycles are used to determine the number of cycles that the destination register address is occupied. After the corresponding number of cycles, the microcode scoreboard releases the occupied state of the destination register address.

[0099] The hazard checking unit is used to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and query in the microcode scoreboard based on the i-th pre-decoding information to determine whether there is a data hazard and a structure hazard, and send a hazard indication signal to the i-th state machine.

[0100] If the source register address and / or destination register address in the i-th predecoded information is the same as any occupied destination register address in the microcode scoreboard, the i-th predecoded information is deemed to contain a data hazard or a structural hazard. Otherwise, the i-th predecoded information is deemed to contain neither a data hazard nor a structural hazard. If the i-th predecoded information contains a data hazard or a structural hazard, the hazard indication signal is a hazard signal; if the i-th predecoded information contains neither a data hazard nor a structural hazard, the hazard indication signal is a non-hazard signal. If the i-th predecoded information was not written to the second register in the previous clock cycle, the i-th predecoded information is deemed to contain neither a data hazard nor a structural hazard, and a corresponding non-hazard signal is sent to the i-th state machine, but the i-th state machine ignores the non-hazard signal.

[0101] The register file unit is used to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0102] exist Figure 2 On the basis of this, regarding how the i-th state machine updates the number of times the i-th microcode instruction has been executed and the state flag stored therein, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0103] The i-th state machine is used to update the number of times the i-th microcode instruction stored in it has been executed according to the hazard indication signal received in the previous clock cycle. If the hazard indication signal received in the previous clock cycle is a non-hazardous signal, the number of times the i-th microcode instruction has been executed is increased by 1. If the hazard indication signal received in the previous clock cycle is a hazard signal, the number of times the i-th microcode instruction has been executed remains unchanged, and the state threshold is updated according to the number of instruction splits received in the previous clock cycle.

[0104] It should be noted that, assuming that the hazard indication signal received by the i-th state machine in the k-th clock cycle is a non-hazardous signal, the i-th state machine needs to update the number of executions of the i-th microcode instruction stored in it in the k+1-th clock cycle (set it to +1); if the hazard indication signal received by the i-th state machine in the k-th clock cycle is a hazard signal, the i-th state machine needs to keep the number of executions of the i-th microcode instruction unchanged in the k+1-th clock cycle.

[0105] Assuming that the i-th state machine receives the number of instruction splits in the k-th clock cycle, the i-th state machine needs to use the number of instruction splits received in the k-th clock cycle as the updated state threshold in the k+1-th clock cycle. It can be understood that after entering the non-safe cycle, the number of instruction splits corresponding to the i-th microcode instruction remains unchanged until entering the safe cycle, and the number of instruction splits is cleared to zero.

[0106] The i-th state machine is used to determine the state identifier of the i-th microcode instruction based on the updated number of executions and the state threshold. If the number of executions is less than the state threshold, the i-th microcode instruction is in a valid state. If the number of executions is equal to the state threshold, the i-th microcode instruction is in an invalid state.

[0107] It should be noted that the i-th state machine updates the number of executions and the status flag in the current clock cycle, and sends the updated number of executions and the status flag of the i-th microcode instruction to the write logic control unit, the selector, the i-th pre-decoding unit, the i-th decoding unit, etc.

[0108] In an optional embodiment, the i-th decoding unit is used to send a splitting requirement indication indicating that splitting is required to the i-th pre-decoding unit when it is determined that the number of instruction splits of the i-th microcode instruction is greater than 1; when the i-th microcode instruction changes from a valid state to an invalid state, or when the number of times the i-th microcode instruction has been executed is equal to its corresponding state threshold, send a splitting requirement indication indicating that splitting is not required to the i-th pre-decoding unit.

[0109] exist Figure 2 On the basis of the structure of the microcode scoreboard and the register file unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 This is a second structural diagram of the decoding module provided in an embodiment of the present invention.

[0110] The microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard, and a vector scoreboard; the register file unit includes a fixed-point register file, a floating-point register file, and a vector register file.

[0111] The output ends of the N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are also connected to the third register; the hazard check unit is also connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard.

[0112] When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store the hazard-related information in the i-th decoding information.

[0113] When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store the hazard-related information in the i-th decoding information.

[0114] When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store the hazard-related information in the i-th decoding information.

[0115] When the relevant register in the i-th pre-decoding information is a fixed-point register, the hazard checking unit is configured to query the fixed-point scoreboard to determine whether a data hazard and a structure hazard exist, and generate a hazard indication signal, wherein the relevant register is the destination register and any one of the one or more source registers in the i-th pre-decoding information.

[0116] When the relevant register in the i-th pre-decoding information is a floating-point register, the hazard checking unit is used to query in the floating-point scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal.

[0117] When the relevant register in the i-th pre-decoding information is a vector register, the hazard checking unit is used to query in the vector scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal.

[0118] When the source register in the i-th pre-decoding information includes a fixed-point register, the fixed-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0119] When the source register in the i-th pre-decoding information includes a floating-point register, the floating-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0120] When the source register in the i-th pre-decoding information includes a vector register, the vector register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

[0121] In an optional embodiment, the parallel operation processor also includes an operation module and a fourth register, and the operation module is connected to the third register and the fourth register respectively; the operation module is used to read the decoding information and source data written by the third register in the previous clock cycle, and perform corresponding operations based on them, and send the obtained operation results and the corresponding destination register address to the fourth register for call by the back-end module.

[0122] Please refer to Figure 4 , Figure 4 A schematic diagram of the structure of a computing module provided in an embodiment of the present invention.

[0123] The operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units, and N vector arithmetic logic units.

[0124] When the instruction type in the i-th decoding information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is used to perform operation processing in combination with the source data corresponding to the i-th decoding information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0125] When the instruction type in the i-th decoding information is a floating-point instruction, the i-th floating-point arithmetic logic unit is used to perform operation processing in combination with the source data corresponding to the i-th decoding information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0126] When the instruction type in the i-th decoding information is a vector instruction, the i-th vector arithmetic logic unit is used to perform calculations on the source data corresponding to the i-th decoding information to obtain the i-th calculation result, and send the i-th calculation result and the corresponding destination register address to the fourth register.

[0127] In the parallel operation processor provided by the embodiment of the present invention, an improved VLIW (very long instruction word) architecture is used to implement the RISC-V processor vector extension. Vector instructions can perform the same operation on multiple data at the same time, more effectively utilize processor resources, reduce the necessary number of instructions and processor cycles, and thus improve energy efficiency when executing large-scale parallel data processing tasks. By improving the microcode slot launch queue, adding a launch queue state machine and a launch queue write control logic, the microcode splitting of the vector operator can be achieved. Because each microcode in the VLIW structure can only write back to one register after completing the operation, and the vector operator needs to support the write back of a register, it is necessary to improve the VLIW structure and support the write back of multiple registers of a single instruction through the microcode splitting method. According to the RISC-V Vector1.0 vector extension requirements, vector operators and source registers may come from fixed-point registers, floating-point registers or vector registers, so it is necessary to add corresponding floating-point and vector parts to the register file unit, microcode scoreboard, hazard check unit and operation unit to support the RISC-V vector extension.

[0128] An embodiment of the present invention provides an electronic device including the above-mentioned parallel computing processor.

[0129] In summary, embodiments of the present invention provide a parallel computing processor and electronic device. The parallel computing processor includes a state monitoring module, a first register, a second register, and a decoding module. The state monitoring module includes: a write control unit, a selector, N transmit queues, N state machines, and N pre-decoding units. The input end of the write control unit and the first input end of the selector are connected to the first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th transmit queue. The output end of the i-th transmit queue is connected to the second input end of the selector. The output end of the selector is connected to the second register and the second input ends of the N pre-decoding units. The output ends of the N pre-decoding units are connected to the second register, where 1≤i≤N. The N state machines and the N pre-decoding units are further connected to the decoding module, which is further connected to the second register. N microcode instructions can be executed in parallel, thereby improving the operating efficiency of the processor.

[0130] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0131] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A processor, characterized in that: The processor includes a state monitoring module, a first register, a second register and a decoding module, wherein the state monitoring module includes: a write control unit, a selector, N transmission queues, N state machines and N pre-decoding units, where N is greater than or equal to 2; An input terminal of the write control unit and a first input terminal of the selector are connected to the first register, an i-th control terminal of the write control unit, an i-th control terminal of the selector, and a first input terminal of an i-th pre-decoding unit are connected to a first terminal of an i-th state machine, an i-th output terminal of the write control unit is connected to an input terminal of an i-th transmit queue, an output terminal of the i-th transmit queue is connected to a second input terminal of the selector, an output terminal of the selector is connected to the second register and second input terminals of N pre-decoding units, and output terminals of the N pre-decoding units are connected to the second register, 1≤i≤N; The N state machines and the N pre-decoding units are further connected to the decoding module, and the decoding module is further connected to the second register; The i-th state machine is used to send a status identifier of the i-th microcode instruction in the i-th issue queue to the selector and the write control unit, and to send the number of times the i-th microcode instruction has been executed and a status identifier to the i-th pre-decoding unit, wherein the status identifier indicates whether the i-th microcode instruction is in a valid state.

2. The processor according to claim 1, wherein When all microcode instructions are in an invalid state, the write control unit and the selector are used to read the most recently written and valid target instruction from the first register, where the target instruction includes N microcode instructions; The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th issue queue; When any microcode instruction is in a valid state, the write control unit and the selector stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th issue queue; The selector is used to write the read N microcode instructions into the second register, write the i-th microcode instruction into the i-th pre-decoding unit, and update the N status identification bits in the second register, wherein the i-th status identification bit corresponds to the i-th microcode instruction, and in a safe cycle, the N status identification bits are all in a valid state, and in a non-safe cycle, the i-th status identification bit is the same as the state identification of the i-th microcode instruction issued by the i-th state machine in the current clock cycle; The i-th pre-decoding unit is configured to receive a splitting requirement indication sent by the decoding module in the current clock cycle, and obtain i-th pre-decoding information corresponding to the i-th microcode instruction received based on the splitting requirement indication, the number of times the i-th microcode instruction has been executed, and the status flag, wherein the i-th pre-decoding information includes an instruction type, a source register address, and a destination register address; The i-th pre-decoding unit is configured to write the obtained i-th pre-decoding information into the second register.

3. The processor according to claim 2, wherein: When the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in a valid state, the i-th pre-decoding unit is configured to obtain i-th pre-decoding information corresponding to the i-th microcode instruction received by the unit in combination with the number of times the i-th microcode instruction has been executed; When the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction; When the splitting requirement indication indicates that splitting is not required, the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives when the i-th microcode instruction sent by the i-th state machine is in a valid state.

4. The processor according to claim 2, wherein: The processor further includes a third register, and the decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units; The first end of the i-th decoding unit is connected to the first end of the i-th state machine, the second ends of the N decoding units are connected to the second register, and the output ends of the N decoding units are all connected to the microcode scoreboard and the third register; The register file unit and the hazard check unit are both connected to the second register, the register file unit is further connected to the third register, and the hazard check unit is further connected to the microcode scoreboard and N state machines; The i-th state machine is further configured to send the number of times the i-th microcode instruction has been executed to the i-th decoding unit; If the i-th state flag in the second register is in a valid state in the current clock cycle, the i-th decoding unit is used to read the i-th microcode instruction written in the second register in the previous clock cycle, and decode it in combination with the number of times the i-th microcode instruction has been executed to obtain i-th decoding information, send the i-th decoding information to the microcode scoreboard and the third register, and send the number of instruction splits corresponding to the i-th microcode instruction to the i-th state machine; The i-th decoding information includes the instruction split number, instruction type, destination register address, operation action, execution cycle number and immediate value corresponding to the i-th microcode instruction; The microcode scoreboard is used to store risk-related information, wherein the risk-related information includes the instruction type, destination register address and execution cycle number corresponding to the microcode instruction; The hazard checking unit is configured to read, in a current clock cycle, the i-th pre-decoded information written in the second register in the previous clock cycle, and query the microcode scoreboard based on the i-th pre-decoded information to determine whether a data hazard and a structure hazard exist, and send a hazard indication signal to the i-th state machine; If the i-th pre-decoded information has a data hazard or a structural hazard, the hazard indication signal is a hazard signal; if the i-th pre-decoded information does not have a data hazard or a structural hazard, the hazard indication signal is a non-hazard signal; The register file unit is configured to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

5. The processor according to claim 4, wherein: The i-th state machine is used to update the number of times the i-th microcode instruction has been executed according to the hazard indication signal received in the previous clock cycle, and update the state threshold according to the number of instruction splits received in the previous clock cycle; The i-th state machine is used to determine the state identifier of the i-th microcode instruction according to the updated number of executions and the state threshold.

6. The processor according to claim 4, wherein: The i-th decoding unit is configured to send a splitting requirement indication indicating that splitting is required to the i-th pre-decoding unit when determining that the number of instruction splits of the i-th microcode instruction is greater than 1; When the i-th microcode instruction changes from a valid state to an invalid state, or when the number of times the i-th microcode instruction has been executed is equal to its corresponding state threshold, a splitting requirement indication indicating that no splitting is required is sent to the i-th pre-decoding unit.

7. The processor according to claim 4, wherein: The microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard and a vector scoreboard, and the register file unit includes a fixed-point register file, a floating-point register file and a vector register file; The output terminals of the N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are further connected to the third register; the hazard check unit is further connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store risk-related information in the i-th decoding information; When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store risk-related information in the i-th decoding information; When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store hazard related information in the i-th decoding information; When the relevant register in the i-th pre-decoding information is a fixed-point register, the hazard checking unit is configured to query the fixed-point scoreboard to determine whether a data hazard and a structure hazard exist, and generate a hazard indication signal, wherein the relevant register is any one of the destination register and one or more source registers in the i-th pre-decoding information; When the relevant register in the i-th pre-decoding information is a floating-point register, the hazard checking unit is used to query the floating-point scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal; When the relevant register in the i-th pre-decoding information is a vector register, the hazard checking unit is used to query the vector scoreboard to determine whether there is a data hazard and a structure hazard, and generate a hazard indication signal; When the source register in the i-th pre-decoding information includes a fixed-point register, the fixed-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information; When the source register in the i-th pre-decoding information includes a floating-point register, the floating-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information; When the source register in the i-th pre-decoding information includes a vector register, the vector register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

8. The processor according to claim 7, wherein: The processor further includes a calculation module and a fourth register, wherein the calculation module is connected to the third register and the fourth register respectively; The operation module is used to read the decoding information and source data written by the third register in the previous clock cycle, and perform corresponding operations based on them, and send the obtained operation results and the corresponding destination register address to the fourth register for call by the back-end module.

9. The processor according to claim 8, wherein The operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units and N vector arithmetic logic units; When the instruction type in the i-th decoding information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is used to perform operation processing on the source data corresponding to the i-th decoding information to obtain an i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoding information is a floating-point instruction, the i-th floating-point arithmetic logic unit is used to perform operation processing on the source data corresponding to the i-th decoding information to obtain an i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoding information is a vector instruction, the i-th vector arithmetic logic unit is used to perform calculations on the source data corresponding to the i-th decoding information to obtain the i-th calculation result, and send the i-th calculation result and the corresponding destination register address to the fourth register.

10. An electronic device, characterized in that: The method comprises the processor according to any one of claims 1 to 9.

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