Processor architecture verification method

Abstract

The invention relates to the technical field of processor function verification, in particular to a processor architecture verification method, which comprises the following steps of: based on architecture description document information, analyzing an instruction name, an operand attribute and a register state, screening instruction set structure information according to an operand definition rule through an architecture document, judging the availability of register calling, and verifying the processor architecture. And screening the register combination meeting the architecture description rule to obtain instruction set architecture data. According to the method, the framework description document information is analyzed, effective application of framework description rules is ensured, test codes are more targeted, verification effectiveness is improved, instruction combinations which cannot be logically executed are eliminated, coverage rate calculation precision is optimized, and invalid test data interference is reduced; through improvement of instruction analysis, accessibility analysis, coverage rate optimization, execution adjustment and the like, it is ensured that the execution condition of an instruction set is comprehensively evaluated, the test efficiency is improved, and the completeness and reliability of processor verification are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of processor functional verification, and in particular, to a method for verifying a processor architecture. Background Art

[0002] The technical field of processor functional verification includes technical means for testing and verifying the instruction set, architecture features, and functionality of a processor. The core content of this technical field is to evaluate the correctness and stability of a processor under different operating conditions through various testing methods, including functional coverage analysis, performance analysis, error detection, and fault tolerance mechanisms. Functional coverage analysis mainly counts the execution of the instruction set to ensure that all defined instructions and operation paths are effectively verified. Processor functional verification also involves the construction of an automated test framework, the generation of test stimuli, and the analysis of test results to reduce the complexity of manual testing and improve verification efficiency. With the continuous upgrade of processor architectures, the combination of instruction sets and architecture features is huge, resulting in extremely complex verification scenarios, and relying on accurate functional coverage calculation methods to measure the completeness of verification.

[0003] Among them, the method for verifying a processor architecture refers to a technical means of describing the behavior of instructions through a structured document during the processor architecture definition stage and automatically generating functional coverage code using this document. This method is for verifying the processor instruction set, covering the combined analysis of instructions and operands, the automatic identification of architecture feature constraints, and the elimination of dead warehouses in coverage statistics. The method includes parsing the structured document to obtain complete information about the instructions, identifying architecture constraints to automatically remove unexecutable instruction combinations, and generating corresponding coverage code according to the definition to ensure that test stimuli can accurately evaluate the effective instruction space.

[0004] In the prior art, during the processor functional verification process, it mainly relies on the method of parsing structured documents and automatically generating functional coverage code for verification. Although it can achieve the combined analysis of instructions and operands, there are limitations in the automatic identification of architecture feature constraints, and it cannot effectively exclude logically unexecutable instruction combinations, resulting in a relatively high proportion of invalid test data, affecting test efficiency and verification accuracy. In the process of coverage statistics, the prior method lacks optimization of the register call method, resulting in test coverage deviation for some register combinations, making the test results have a problem of local imbalance. During the execution of automated tests, the execution order of test vectors is not dynamically adjusted according to the register state, restricting the ability to capture abnormal behaviors and making it difficult to form an efficient processor verification closed-loop. Due to the huge combination of instruction sets and architecture features, the prior verification means are difficult to accurately measure the effectiveness of coverage data in the face of complex scenarios, affecting the overall verification completeness and the optimization process of the processor architecture. Summary of the Invention

[0005] The object of the present invention is to solve the disadvantages existing in the prior art, and a method for verifying a processor architecture is proposed.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A method for verifying a processor architecture includes:

[0007] S1: Based on the architecture description document information, parse the instruction name, operand attributes, and register status. Through the architecture document, screen the instruction set structure information according to the operand definition rules, judge the availability of register calls, and screen the register combinations that meet the architecture description rules to obtain the instruction set architecture data;

[0008] S2: Based on the instruction set architecture data, extract the instruction coverage rate, structure coverage rate, interaction coverage rate, and register coverage rate, screen the coverage rate target data, obtain the functional coverage rate test code set, classify and process the instruction set parameter information and then pass it to the mako template to generate the coverage rate code;

[0009] S3: Call the functional coverage rate test code set, analyze the reachability of register combinations, analyze the value range limits of operands, and eliminate the instruction combinations that are logically non-executable to obtain the invalid coverage bin data set;

[0010] S4: Based on the invalid coverage bin data set, identify the coverage rate data distribution, analyze the register allocation situation, and adjust the register call method to obtain the optimized coverage rate;

[0011] S5: Call the optimized coverage rate, adjust the execution order of test vectors, analyze the register status distribution, and record the abnormal execution behavior to obtain the processor verification result.

[0012] As a further solution of the present invention, the instruction set architecture data includes an instruction name set, an operand attribute classification, a register status list, and an immediate number range limit. The functional coverage rate test code set includes an instruction coverage rate index, a structure coverage rate index, an interaction coverage rate index, and a register coverage rate index. The invalid coverage bin data set includes unreachable register combinations, invalid operand ranges, and logically invalid instruction sets. The optimized coverage rate includes a register allocation scheme, a coverage rate data adjustment scheme, and a register call optimization scheme. The processor verification result includes abnormal execution records, test vector order adjustment, and register status analysis data.

[0013] As a further solution of the present invention, the specific steps for obtaining the instruction set architecture data are:

[0014] S111: Extract the instruction name, operand attributes, register status, and immediate value range based on the architecture description document information, filter the operand information that meets the architecture description requirements, and obtain the operand classification features;

[0015] S112: Invoke the operand classification features, classify the register status according to the operand definition rules, and determine the availability of registers in different instruction modes to obtain the register call matrix;

[0016] S113: Invoke the register call matrix, filter the instruction set structure information that meets the architecture description rules, establish the matching relationship between operands and registers, analyze the corresponding mapping relationship of the instruction structure, and use the formula:

[0017]

[0018] Obtain the instruction set architecture data;

[0019] where M represents the instruction set architecture data, R i represents the register set of the i-th instruction, O i represents the operand set of the i-th instruction, |R i ∩O i | represents the intersection number of register and operand matching, and n represents the total number of instructions.

[0020] As a further solution of the present invention, the specific steps for obtaining the functional coverage test code set are as follows:

[0021] S211: Based on the instruction set architecture data, parse the instruction execution path, count the trigger times of each instruction, and obtain the instruction coverage value;

[0022] S212: Based on the instruction coverage value, invoke the activation data of registers, caches, and branch predictions in the architecture, identify the trigger frequency of the structure, analyze the interaction effects between structures, and use the formula:

[0023]

[0024] Obtain the interaction coverage ratio;

[0025] where C int represents the interaction coverage ratio, A j represents the execution influence degree of the j-th instruction, B j represents the influence intensity of the j-th instruction on the storage structure in the architecture, and m represents the total number of instructions;

[0026] S213: Invoke the interaction coverage ratio, filter the coverage target data, and obtain the functional coverage test code set according to the register usage rate and the distribution of critical instructions.

[0027] As a further solution of the present invention, the steps for obtaining the invalid coverage bin data set are specifically as follows:

[0028] S311: Invoke the function coverage test code set, detect the access paths of register combinations, analyze the register state transition constraints, filter reachable paths, and use the formula:

[0029]

[0030] Calculate the register combination reachability coefficient and obtain the register reachable path set;

[0031] Among them, C r represents the register combination reachability coefficient, V k represents the current state value of register k, T k represents the target state value of register k, S k represents the number of steps of register k state transition, and K represents the number of register combinations;

[0032] S312: Invoke the register reachable path set, analyze the operand value ranges, filter the operands that meet the register state constraints, and obtain the valid operand set;

[0033] S313: Based on the valid operand set, analyze the execution logic of instruction combinations, filter the non-executable instruction combinations, eliminate invalid instructions, and obtain the invalid coverage bin data set.

[0034] As a further solution of the present invention, the steps for obtaining the optimized coverage rate are specifically as follows:

[0035] S411: Based on the invalid coverage bin data set, analyze the frequency distribution of coverage rate data, filter the data points lower than the benchmark value, and obtain the coverage rate anomaly point distribution coefficient;

[0036] S412: Invoke the coverage rate anomaly point distribution coefficient, evaluate the optimal register allocation according to the register occupancy rate, access frequency, and storage capacity, adjust the register call method, reduce the occupancy of invalid coverage bin registers, optimize the register utilization rate, and obtain the optimized register allocation ratio;

[0037] S413: Based on the optimized register allocation ratio, analyze the coverage rate distribution, and use the formula:

[0038]

[0039] Calculate the coverage rate adjustment value to obtain the optimized coverage rate;

[0040] Among them, C' represents the coverage rate adjustment value, D xCoverage data representing the x-th register, D avg Mean value of register coverage data, F x Access frequency of the x-th register, P represents the total number of registers, U x Occupancy rate of the x-th register, W x Storage capacity of the x-th register.

[0041] As a further solution of the present invention, the step of obtaining the processor verification result is specifically as follows:

[0042] S511: Based on the optimized coverage rate, analyze the register status distribution within the coverage area, screen the coverage rate influencing factors, and use the formula:

[0043]

[0044] Operate and adjust the coverage parameters to obtain an optimized coverage rate distribution map;

[0045] Among them, C opt Represents the adjusted coverage parameter, C base Represents the basic coverage rate, F reg Represents the access frequency of critical registers, F avg Represents the average access frequency of registers, W inst Represents the instruction distribution weight, D cov Represents the state dispersion degree of the coverage area;

[0046] S512: Based on the optimized coverage rate distribution map, identify the priority of the test vector execution order, and adjust the test vector order according to the register status change to obtain an adjusted test vector sequence;

[0047] S513: Call the adjusted test vector sequence, monitor the register status change, screen the abnormal status jump data, and record the abnormal execution behavior data to obtain the processor verification result.

[0048] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0049] In the present invention, by parsing the architecture description document information, in-depth matching of the instruction set structure is achieved, ensuring the precise application of the architecture description rules. Target data is screened based on coverage analysis at different levels, making the test code more targeted and enhancing the effectiveness of verification. Regarding the reachability of instructions and registers, by analyzing the register combinations and operand value constraints, instruction combinations that are logically non-executable are automatically eliminated, optimizing the accuracy of coverage calculation, reducing the interference of invalid test data on the verification process, further adjusting the register call method, making the coverage data distribution more balanced, avoiding register resource allocation deviations, and improving the representativeness of instruction execution. By optimizing the execution order of test vectors and combining the analysis of register state distribution, precise capture of abnormal behaviors is achieved, making the processor verification result more perfect. Through multi-level improvements such as instruction parsing, reachability analysis, coverage construction, elimination of invalid data, and execution optimization, the test data is made more targeted, reducing the interference of invalid data, improving the test efficiency, ensuring that the execution situation of the instruction set can be comprehensively evaluated, and enhancing the completeness and reliability of processor verification. Brief Description of the Drawings

[0050] Figure 1 is the flowchart of the method of the present invention;

[0051] Figure 2 is the flowchart for obtaining the instruction set architecture data in the present invention;

[0052] Figure 3 is the flowchart for obtaining the functional coverage test code set in the present invention;

[0053] Figure 4 is the flowchart for obtaining the invalid coverage bin data set in the present invention;

[0054] Figure 5 is the flowchart for obtaining the optimized coverage rate in the present invention;

[0055] Figure 6 is the flowchart for obtaining the processor verification result in the present invention. Detailed Description of the Preferred Embodiment

[0056] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0057] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, in the description of the present invention, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.

[0058] Please refer to Figure 1 , a method for verifying a processor architecture includes:

[0059] S1: Based on the architecture description document information, parse the instruction name, operand attributes, and register status. Through the architecture document, ensure the easier automated acquisition of information. Filter the instruction set structure information according to the operand definition rules, judge the availability of register calls, filter the register combinations that conform to the architecture description rules, establish the instruction set structure matching relationship, obtain the instruction set architecture data, and extract the characteristics and constraint information in the architecture description to ensure the integrity and consistency of the information;

[0060] S2: Based on the instruction set architecture data, extract the instruction coverage rate, structure coverage rate, interaction coverage rate, and register coverage rate. Filter the coverage rate target data to obtain the functional coverage rate test code set. After classifying and processing the instruction set parameter information, pass it to the mako template to generate the coverage rate code;

[0061] S3: Call the functional coverage rate test code set, analyze the reachability of register combinations, analyze the value limits of operands, eliminate the instruction combinations that are logically unexecutable, obtain the invalid coverage bin data set, verify the executability of instructions according to the instruction architecture rules, and eliminate the combinations that do not meet the execution conditions;

[0062] S4: Based on the invalid coverage bin data set, identify the coverage rate data distribution, analyze the register allocation situation, adjust the register call method, obtain the optimized coverage rate, and adjust the execution strategy of test cases according to the register status distribution;

[0063] S5: Call the optimized coverage rate, adjust the execution order of test vectors, analyze the register status distribution, and record the abnormal execution behavior to obtain the processor verification result.

[0064] The instruction set architecture data includes a set of instruction names, operand attribute classifications, register status lists, and immediate value range limitations. The functional coverage test code set includes instruction coverage metrics, structural coverage metrics, interaction coverage metrics, and register coverage metrics. The invalid coverage bin data set includes unreachable register combinations, invalid operand ranges, and logically invalid instruction sets. The optimized coverage includes a register allocation scheme, a coverage data adjustment scheme, and a register call optimization scheme. The processor verification results include exception execution records, test vector order adjustments, and register status analysis data.

[0065] Please refer to Figure 2 , and the specific steps for obtaining the instruction set architecture data are as follows:

[0066] S111: Based on the architecture description document information, extract the instruction names, operand attributes, register statuses, and immediate value ranges, and filter the operand information that meets the architecture description requirements to obtain the operand classification characteristics;

[0067] First, obtain the instruction set information in the architecture description document, including instruction names, operand attributes, register statuses, and immediate value ranges, etc. For each instruction, parse its operand attributes to determine the type (such as register, memory address, immediate value, etc.) and quantity of the operands, analyze the register status, identify the available register set, determine the value range of the immediate value, and combine the operand definition rules to filter out the operand information that meets the architecture description requirements. For example, an instruction requires two register operands and one immediate value operand, and the immediate value range is from 0 to 255, then extract the operand classification characteristics of this instruction.

[0068] S112: Invoke the operand classification characteristics, classify the register status according to the operand definition rules, and judge the availability of registers in different instruction modes to obtain the register call matrix;

[0069] First, classify the register status according to the operand definition rules. For example, classify registers into general-purpose registers, floating-point registers, special-purpose registers, etc. For each instruction, analyze its operand requirements, judge the required register type and quantity, check the current register status, and determine the available register combination that meets the instruction requirements. For example, an instruction requires two general-purpose register operands, the method will check the current list of available general-purpose registers and select two unoccupied registers to obtain the register call matrix.

[0070] S113: Invoke the register call matrix, filter the instruction set structure information that meets the architecture description rules, establish the matching relationship between operands and registers, analyze the corresponding mapping relationship of the instruction structure, and use the formula:

[0071]

[0072] Obtain instruction set architecture data;

[0073] where M represents the instruction set architecture data, R i represents the register set of the i-th instruction, and O i represents the operand set of the i-th instruction, |R i ∩O i | represents the number of intersections of register and operand matching, and n represents the total number of instructions;

[0074] First, filter the instruction set structure information that conforms to the architecture description rules. For example, when designing a microprocessor, it is necessary to determine the types and quantities of registers required for the supported instructions such as the addition instruction. Based on the requirements of each instruction, establish the matching relationship between operands and registers. For example, the addition instruction requires two general-purpose registers and one register for storing the result, and calculate the corresponding mapping relationship of the instruction structure;

[0075] Suppose there are the following parameter settings: For a simple instruction set, there are three instructions, and the register sets R i and operand sets O i for each instruction are as follows:

[0076] Instruction 1 (addition instruction): R1 = {R1, R2, R3}, O1 = {R1, R2};

[0077] Instruction 2 (subtraction instruction): R2 = {R4, R5, R6}, O2 = {R4, R5};

[0078] Instruction 3 (multiplication instruction): R3 = {R7, R8, R9}, O3 = {R7, R8};

[0079] Calculate each value: |R1∩O1| = 2 (R1 and R2 are common), |R2∩O2| = 2 (R4 and R5 are common), |R3∩O3| = 2 (R7 and R8 are common);

[0080] Substitute the values into the formula:

[0081] The calculation result M≈2.683 represents the matching efficiency of registers and operands of the entire instruction set. Through such matching analysis, developers can optimize the instruction design to ensure the efficient cooperation between instructions and hardware and obtain the instruction set architecture data.

[0082] Please refer to Figure 3 , and the specific steps for obtaining the functional coverage test code set are as follows:

[0083] S211: Based on the instruction set architecture data, parse the instruction execution path, count the trigger times of each instruction, and obtain the instruction coverage value;

[0084] Analyze the execution of each instruction in different processor states through dedicated software. For example, simulate the ARM architecture in a virtual environment, track how instructions are scheduled and executed at each stage of the processor, and also monitor how instructions affect each register of the processor. The specific process includes collecting the data of the number of times each instruction triggers a register, and then using simple calculations such as calculating the average number of registers affected by the ADD instruction. This process is repeated to cover all instruction types, so as to count the trigger times of each instruction, and through comprehensive analysis of the data, calculate the overall instruction coverage value. This method can ensure the accurate calculation of test coverage, and then provide data support for the performance optimization of the processor, which will directly affect subsequent performance adjustment and optimization.

[0085] S212: Based on the instruction coverage value, call the activation data of registers, caches, and branch predictions within the architecture, identify the trigger frequency of the structure, analyze the interaction effects between structures, and use the formula:

[0086]

[0087] Obtain the interaction coverage ratio;

[0088] Among them, C int represents the interaction coverage ratio, A j represents the execution influence degree of the j-th instruction, B j represents the influence strength of the j-th instruction on the storage structure within the architecture, and m represents the total number of instructions;

[0089] Collect the activation times of each storage structure. For example, in the processor environment of the ARM architecture, execute 2000 instructions, and count its access to the L1 cache. Among them, the cache access times of instruction A are 150 times, the access times of instruction B are 180 times, and the access times of instruction C are 90 times. Further analyze the distribution of instructions in the storage structure within the processor architecture, and calculate its impact on the overall cache behavior. For the three instructions A, B, and C, obtain their respective execution frequencies. For example, A is executed 500 times, B is executed 400 times, and C is executed 300 times. Then, the cache influence degree of each instruction can be calculated, that is:

[0090] A1 = 150 / 500 = 0.3 (cache influence degree of instruction A);

[0091] A2 = 180 / 400 = 0.45 (cache influence degree of instruction B);

[0092] A3 = 90 / 300 = 0.3 (cache influence degree of instruction C);

[0093] Similarly, analyze the influence intensity of the instruction on the storage structure. Assume that the influence intensity calculation method is based on the storage access hit rate multiplied by the number of instruction executions. For example:

[0094] B1 = 0.9 × 500 = 450 (storage influence intensity of instruction A);

[0095] B2 = 0.8 × 400 = 320 (storage influence intensity of instruction B);

[0096] B3 = 0.85 × 300 = 255 (storage influence intensity of instruction C);

[0097] Substitute specific values for calculation:

[0098]

[0099] Finally, the calculated interaction coverage ratio is 0.584. The value indicates that under the current architecture, the interaction degree between the instruction and the storage structure is relatively high, and the storage structure has a greater impact on the instruction execution. This data can be further used to optimize the instruction scheduling method. For example, the execution order of the instructions can be adjusted to reduce the storage access conflict, thereby improving the overall operation efficiency of the processor.

[0100] S213: Call the interaction coverage ratio, filter the coverage target data, and obtain the functional coverage test code set according to the register usage rate and the distribution of key instructions;

[0101] Analyze which registers and key instructions are frequently used in actual operations. For example, when performing high-performance computing, the utilization rate of registers and the execution distribution of instructions are key factors. By collecting and analyzing a large amount of actual operation data, such as when running big data processing tasks on a high-performance server, record the most frequently used registers and instructions. It is also necessary to perform detailed calculations and comparisons on the data to ensure that the truly high-impact areas are screened out. Finally, obtain the functional coverage test code set according to the data calculation. The result is directly related to the final performance of the processor and the optimization and adjustment of the software, ensuring the effectiveness and practicality of the target data.

[0102] Please refer to Figure 4 , and the specific steps for obtaining the invalid coverage bin data set are as follows:

[0103] S311: Call the functional coverage test code set, detect the access paths of register combinations, analyze the register state transition constraints, filter the reachable paths, and use the formula:

[0104]

[0105] Calculate the register combination reachability coefficient to obtain the register reachable path set;

[0106] Among them, C r represents the register combination reachability coefficient, V k represents the current state value of register k, T k represents the target state value of register k, S k represents the number of state transition steps of register k; K represents the number of register combinations;

[0107] Detect and identify register paths that conform to specific logical instructions. For example, in a high-performance computing (HPC) environment, the processor core needs to execute multiple parallel tasks. When data is transferred between registers, its reachability needs to be ensured to avoid data blocking or loss. Monitor the currently active registers and record their states, mainly focusing on the data transfer path, the current stored value, the target stored value, and the number of their state transition steps. For each register combination, calculate its reachability;

[0108] For specific calculations, assume that the four registers 1, 2, 3, and 4 in the method have the following data:

[0109] Register 1: The current value V1 = 80, the target value T1 = 200, and the number of state transition steps S1 = 3;

[0110] Register 2: The current value V2 = 150, the target value T2 = 300, and the number of state transition steps S2 = 4;

[0111] Register 3: The current value V3 = 90, the target value T3 = 180, and the number of state transition steps S3 = 2;

[0112] Register 4: The current value V4 = 50, the target value T4 = 220, and the number of state transition steps S4 = 5;

[0113] Substitute these data into the formula to calculate the reachability coefficient:

[0114]

[0115]

[0116] C r = 60 + 67.09 + 51.96 + 69.42 = 248.47;

[0117] The calculated register reachability coefficient is 248.47. The value can be used to further determine whether the data transfer path between registers is feasible. Assume that the reachability reference value of the method is set to 250. Since C r= 248.47 is slightly lower than this benchmark value, indicating that this register combination is still feasible under the current architecture, but it will cause some instruction executions to be blocked under high load conditions. Therefore, it is necessary to further optimize the data scheduling strategy. Finally, the set of register reachable paths is obtained, and this set is used to optimize the instruction execution process of the method, ensure smooth data transmission, and improve computing efficiency.

[0118] S312: Call the set of register reachable paths, analyze the value range of operands, filter the operands that meet the register status constraints, and obtain the set of valid operands;

[0119] In a specific algorithm or data processing task, select the most suitable operands according to the performance metrics of the registers. For example, when performing complex graphics processing or big data analysis, select the operands that can maximize the utilization of register performance. According to the register reachability data set, perform the availability detection of operands, which includes checking whether each operand can be used without violating the register constraints. Screen out the optimal choice by comparing the performance of each operand, accurately quantify the effectiveness of each operand, and sort accordingly to ensure the efficiency of data processing. The application scenario of operands in processing high-frequency trading data can be considered, where the selection of each operand directly affects the reaction speed and accuracy of the trading algorithm. Obtain the set of valid operands, which helps method designers make more informed decisions when choosing the appropriate algorithm and data path.

[0120] S313: Based on the set of valid operands, analyze the execution logic of instruction combinations, filter out the non-executable instruction combinations, eliminate the invalid instructions, and obtain the invalid coverage bin data set;

[0121] When designing a microprocessor or highly integrated hardware, ensure that all instruction sets can operate effectively in the given hardware architecture. For example, when developing a new processor architecture, it is necessary to ensure the compatibility of all software and hardware to avoid execution errors. Use simulation software to test the execution results of various instruction combinations, which includes simulating the operation of different types of operation methods and applications on the new processor. According to the test results, eliminate the instruction combinations that cannot be executed due to hardware limitations, significantly improve the reliability of the hardware and the compatibility of the software. For practical demonstration, consider that when designing a GPU for high-performance computing, eliminate the instruction combinations that cannot effectively support parallel processing. Obtaining the invalid coverage bin data set helps the design team optimize the product design and reduce the testing time and cost in the market.

[0122] Please refer to Figure 5 , and the specific steps for obtaining the optimized coverage rate are as follows:

[0123] S411: Analyze the frequency distribution of the coverage rate data based on the invalid coverage bin dataset, filter out the data points below the benchmark value, and obtain the distribution coefficient of the coverage rate anomaly points;

[0124] Calculate the frequency distribution of the coverage rate data, filter out the data points below the benchmark value, identify the anomaly points. The points are the register data where the coverage rate is significantly lower than expected. For example, assume there are 100 registers, and those with a coverage rate lower than 20% are regarded as anomalies. At this time, the benchmark value is set to 20%. Collect the usage frequency and coverage rate of each register, find the set of registers below this benchmark value, further analyze the distribution characteristics of the registers, calculate the mean and standard deviation of the coverage rate, and obtain the distribution coefficient of the coverage rate anomaly points. This coefficient can help locate the problematic registers. If it is found that a certain type of register frequently appears in the anomaly points, it is necessary to adjust the management strategy of this type of register or increase its monitoring intensity.

[0125] S412: Invoke the distribution coefficient of the coverage rate anomaly points, evaluate the optimal allocation of the registers based on the register occupancy rate, access frequency, and storage capacity, adjust the register call method, reduce the occupancy of the invalid coverage bin registers, optimize the register utilization rate, and obtain the optimized register allocation ratio;

[0126] First, it is necessary to calculate the usage efficiency of each register. Through actual data calculation, for example, assume that the average occupancy rate of a certain register is 75%, the access frequency is 10 times per minute, and the storage capacity is 32 bit. Based on this data, use the formula to calculate the efficiency index of each register. Based on this index, further adjust the allocation strategy. For example, for registers with low efficiency but high access frequency, increase their priority to ensure efficient operation, and obtain the optimized register allocation ratio. By comparing the efficiency improvement before and after the adjustment, in the embodiment, if the efficiency improvement after the adjustment exceeds 10%, it is considered that the adjustment is effective, and the result will directly affect the performance of the entire method.

[0127] S413: Based on the optimized register allocation ratio, analyze the coverage rate distribution, and use the formula:

[0128]

[0129] Calculate the adjusted value of the coverage rate to obtain the optimized coverage rate;

[0130] Among them, C′ represents the adjusted value of the coverage rate, D x represents the coverage rate data of the xth register, D avg represents the mean of the register coverage rate data, F x represents the access frequency of the xth register, P represents the total number of registers, U x represents the occupancy rate of the xth register, W x represents the storage capacity of the xth register;

[0131] To calculate the optimized coverage rate, assume there are 5 registers in the method, and the coverage rate data is as follows:

[0132] D1 = 30%, D2 = 25%, D3 = 20%, D4 = 35%, D5 = 40%;

[0133] Calculate the average coverage rate:

[0134] Set the access frequencies: F1 = 10, F2 = 15, F3 = 5, F4 = 12, F5 = 8;

[0135] Calculate the numerator part:

[0136]

[0137] Set the register occupancy rate and storage capacity:

[0138] U1 = 0.75, U2 = 0.80, U3 = 0.60, U4 = 0.85, U5 = 0.90;

[0139] W1 = 256, W2 = 512, W3 = 128, W4 = 1024, W5 = 768;

[0140] Calculate the denominator part:

[0141]

[0142]

[0143] Calculate the final optimized coverage rate:

[0144] After the optimized register allocation strategy, the optimized value of the coverage rate reaches 5.11. This value has a certain improvement compared with the calculated value before optimization, which means that the calling method of the register has been adjusted, the distribution of coverage rate abnormal points has been effectively controlled, thereby reducing the impact of invalid coverage bins and improving the overall coverage rate management efficiency of the method.

[0145] Please refer to Figure 6 , and the specific steps for obtaining the processor verification result are as follows:

[0146] S511: Based on the optimized coverage rate, analyze the register status distribution in the coverage area, screen the coverage rate influencing factors, and use the formula:

[0147]

[0148] Operate and adjust the coverage parameters to obtain the optimized coverage rate distribution map;

[0149] Among them, C opt represents the adjusted coverage parameter, C base represents the basic coverage rate, F reg represents the access frequency of critical registers, F avg represents the average access frequency of registers, W inst represents the instruction distribution weight, D cov represents the state dispersion degree of the coverage area;

[0150] First, obtain the state distribution of each register in the coverage area. Assume that in a certain test environment, the access frequencies of five registers are sampled. Among them, a certain register is accessed 1500 times within 10 seconds, while the average access frequency of other registers is 1000 times. This indicates that the access volume of this register is relatively high. In order to optimize the test coverage rate, it is necessary to calculate the coverage rate impact factor and adjust the coverage area parameters. Calculate the absolute difference between the access frequency of this register and the average access frequency: |F reg ―F avg | = |1500 - 1000| = 500;

[0151] It is necessary to consider the instruction distribution weight W inst , which reflects the distribution of instructions on different registers. In the experimental environment, the execution weight of the instructions related to this register is calculated to be 0.6. At the same time, it is necessary to consider the state dispersion degree D cov of the coverage area. This parameter measures the variability of the register state in the test cases. By calculating the coefficient of variation (i.e., the ratio of the standard deviation to the mean of the register state), D cov = 25;

[0152] Assume the basic coverage rate C base = 70, then:

[0153]

[0154] The adjusted coverage parameter 128.82 is obtained. This result can be used as an important basis for adjusting the test vector execution strategy, and helps to optimize the coverage rate distribution, thereby improving the effectiveness and balance of test coverage, and finally generating an optimized coverage rate distribution map.

[0155] S512: Based on the optimized coverage rate distribution map, identify the priority of the test vector execution order, and adjust the test vector order according to the register state change to obtain an adjusted test vector sequence;

[0156] By observing the changing trend of the register status, the test vectors are adjusted to simulate the most actual running conditions. For example, if a certain register shows frequent access in the optimized coverage data, the test vectors of the register will be adjusted preferentially to ensure that it is tested first in the test sequence. This adjustment is carried out by comparing the calculations of the influence of each test vector on the register status to ensure that each adjustment is based on precise calculations of actual data. Finally, the adjusted test vector sequence is obtained, and this sequence is verified through actual tests to ensure the effectiveness of the test and the maximization of the coverage rate.

[0157] S513: Call the adjusted test vector sequence, monitor the changes in the register status, screen the data of abnormal status jumps, record the data of abnormal execution behaviors, and obtain the processor verification result;

[0158] Using the adjusted test vector sequence, focus on monitoring and recording the changes in the register status that deviate from the normal expectations. By regularly monitoring the register status, abnormal behaviors can be quickly identified. For example, if the status of a certain register suddenly changes without an obvious triggering condition, this indicates potential hardware or software problems. Recording abnormal behaviors not only helps to detect problems early but also helps engineers quickly troubleshoot. The finally obtained data of abnormal execution behaviors is obtained through a series of precise calculations and experimental settings, and the processor verification result is obtained to ensure the stability and reliability of the method.

[0159] The above are only the preferred embodiments of the present invention and do not limit the present invention in other forms. Any person skilled in the art may use the disclosed technical content to make changes or modifications into equivalent embodiments with equivalent changes and apply them to other fields. However, as long as it does not depart from the technical solution content of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for verifying a processor architecture, characterized in that The method includes: S1: Based on the architecture description document information, parse the instruction names, operand attributes, and register statuses. Through the architecture document, screen the instruction set structure information according to the operand definition rules, judge the availability of register calls, and screen the register combinations that conform to the architecture description rules to obtain the instruction set architecture data. S2: Based on the instruction set architecture data, extract the instruction coverage rate, structure coverage rate, interaction coverage rate, and register coverage rate, screen the coverage rate target data to obtain the functional coverage rate test code set, classify and process the instruction set parameter information and then pass it to the mako template to generate the coverage rate code. S3: Call the functional coverage rate test code set, analyze the reachability of register combinations, analyze the value limits of operands, and eliminate the instruction combinations that are logically unexecutable to obtain the invalid coverage bin data set. S4: Based on the invalid coverage bin data set, identify the distribution of coverage rate data, analyze the register allocation situation, and adjust the register call method to obtain the optimized coverage rate. S5: Call the optimized coverage rate, adjust the execution order of test vectors, analyze the register status distribution, and record the abnormal execution behavior to obtain the processor verification result.

2. The method for verifying a processor architecture according to claim 1, wherein The instruction set architecture data includes an instruction name set, an operand attribute classification, a register status list, and an immediate number range limit. The functional coverage rate test code set includes an instruction coverage rate index, a structure coverage rate index, an interaction coverage rate index, and a register coverage rate index. The invalid coverage bin data set includes unreachable register combinations, invalid operand ranges, and logically invalid instruction sets. The optimized coverage rate includes a register allocation scheme, a coverage rate data adjustment scheme, and a register call optimization scheme. The processor verification result includes an abnormal execution record, a test vector order adjustment, and register status analysis data.

3. The method for verifying a processor architecture according to claim 1, wherein The specific steps for obtaining the instruction set architecture data are as follows: S111: Based on the architecture description document information, extract the instruction names, operand attributes, register statuses, and immediate number ranges, and screen the operand information that conforms to the architecture description requirements to obtain the operand classification features. S112: Call the operand classification features, classify the register statuses according to the operand definition rules, and judge the availability of registers in different instruction modes to obtain the register callable matrix. S113: Call the register callable matrix, screen the instruction set structure information that conforms to the architecture description rules, establish the matching relationship between operands and registers, analyze the corresponding mapping relationship of the instruction structure, and use the formula: To obtain the instruction set architecture data. Among them, M represents the instruction set architecture data, R i represents the register set of the i-th instruction, O i represents the operand set of the i-th instruction, |R i ∩O i | represents the number of intersections of register and operand matching, and n represents the total number of instructions.

4. The method for verifying a processor architecture according to claim 3, wherein The specific steps for obtaining the functional coverage rate test code set are as follows: S211: Based on the instruction set architecture data, parse the instruction execution path, count the trigger times of each instruction to obtain the instruction coverage rate value. S212: Based on the instruction coverage rate value, call the activation data of registers, caches, and branch predictions in the architecture, identify the trigger frequency of the structure, analyze the interaction effects between structures, and use the formula: To obtain the interaction coverage rate ratio. Among them, C int represents the interaction coverage ratio, A j represents the execution impact of the j-th instruction, B j represents the influence intensity of the j-th instruction on the storage structure within the architecture, and m represents the total number of instructions; S213: Invoke the interaction coverage ratio, screen the coverage target data, and obtain the functional coverage test code set based on the register usage rate and the critical instruction distribution.

5. The method for verifying a processor architecture according to claim 4, wherein The specific steps for obtaining the invalid coverage bin data set are as follows: S311: Invoke the functional coverage test code set, detect the access paths of register combinations, analyze the register state transition constraints, screen the reachable paths, and use the formula: Calculate the register combination reachability coefficient and obtain the register reachable path set; Among them, C r represents the register combination reachability coefficient, V k represents the current state value of register k, T k represents the target state value of register k, S k represents the number of steps of state transition of register k, and K represents the number of register combinations; S312: Invoke the register reachable path set, analyze the operand value ranges, screen the operands that meet the register state constraints, and obtain the valid operand set; S313: Based on the valid operand set, analyze the instruction combination execution logic, screen the non-executable instruction combinations, eliminate the invalid instructions, and obtain the invalid coverage bin data set.

6. The method for verifying a processor architecture according to claim 5, wherein The specific steps for obtaining the optimized coverage are as follows: S411: Based on the invalid coverage bin data set, analyze the frequency distribution of the coverage data, screen the data points below the benchmark value, and obtain the coverage anomaly point distribution coefficient; S412: Invoke the coverage anomaly point distribution coefficient, evaluate the optimal register allocation according to the register occupancy rate, access frequency, and storage capacity, adjust the register call method, reduce the register occupancy of the invalid coverage bins, optimize the register utilization rate, and obtain the optimized register allocation ratio; S413: Based on the optimized register allocation ratio, analyze the coverage distribution, and use the formula: Calculate the coverage adjustment value to obtain the optimized coverage; Among them, C′ represents the coverage adjustment value, D x represents the coverage data of the x-th register, D avg represents the mean value of the register coverage data, F x represents the access frequency of the x-th register, P represents the total number of registers, U x represents the occupancy rate of the x-th register, W x represents the storage capacity of the x-th register.

7. The method for verifying a processor architecture according to claim 6, wherein The specific steps for obtaining the processor verification result are as follows: S511: Based on the optimized coverage, analyze the register state distribution within the coverage area, screen the coverage impact factors, and use the formula: Calculate the adjusted coverage parameter to obtain the optimized coverage distribution map; Among them, C opt represents the adjusted coverage parameter, C base represents the basic coverage rate, F reg represents the access frequency of key registers, F avg represents the average access frequency of registers, W inst represents the instruction distribution weight, D cov represents the state dispersion degree of the coverage area; S512: Based on the optimized coverage distribution map, identify the priority of the test vector execution order, and adjust the test vector order according to the register state changes to obtain the adjusted test vector sequence; S513: Invoke the adjusted test vector sequence, monitor the register state changes, screen the abnormal state transition data, and record the abnormal execution behavior data to obtain the processor verification result.

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