Signal interface generation method and system based on HIL test

Abstract

The invention relates to the technical field of automobile testing, and particularly discloses a signal interface generation method and system based on HIL testing, and the method comprises the steps: A, configuring and reading a Veriand project, obtaining an initial signal interface, configuring the Veriand project according to the initial signal interface, automatically reading the initial signal interface in the Veriand project and the attribute of the initial signal interface, and generating a signal interface according to the initial signal interface; generating first associated information in one-to-one correspondence; b, dividing the first associated information, and performing first hierarchical region division on different first associated information according to the attribute characteristics of the first associated information; c, customizing first screening information, screening the first associated information and generating customized first screening information; d, editing a Simulink project, and automatically generating a corresponding second signal interface in the Simulink project according to the first screening information; and E, generating a target mapping file, and generating one-to-one corresponding mapping interfaces according to the initial signal interface and the second signal interface. The test efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive testing, and particularly to a signal interface generation method and system based on HIL testing. Background Art

[0002] HIL (Hardware-in-the-Loop) testing is a system-level testing method widely used in fields such as automotive and industrial automation. It connects the actual controller hardware to the simulation environment to test the control system in a virtual simulation test environment. This method allows engineers to verify the functions and performance of the control system in a laboratory environment, greatly improving development efficiency and reducing costs.

[0003] Especially in the automotive field, current HIL bench solutions include various types of test platform integration solutions, such as HIL testing based on platforms like NI / Dspace / IPG. Based on the NI hardware platform, it involves the interaction between multiple models, including the integration of Veristand and Simulink software. In HIL testing, users need to manually configure multiple types of interfaces, such as AIO (Analog Input / Output), CAN (Controller Area Network), etc. This not only increases the workload of users but also easily leads to configuration errors due to human errors, affecting the setup efficiency of the test environment. Veristand and Simulink are two independent test tools without an automated interface adaptation function. Users need to manually build a Simulink project for various signals in the Veristand project and perform interface mapping, which is cumbersome and inefficient.

[0004] In the prior art, such as the method for automatic signal mapping in HIL testing with the patent application number CN202210329687.8, it only has the function of generating mapping files, and a Simulink project needs to be built in advance before implementing this function. However, building a Simulink project requires the configuration of Simulink interfaces and related attributes, and the connection mapping file of the generated interface can only be carried out based on the existing Simulink interfaces and Veristand interfaces. Therefore, the prior art requires manual configuration in advance for signal interface generation based on HIL testing. In HIL testing, multiple types often need to be configured, such as hardwired signals, CAN signals, and custom signals. With the adaptation of a large number of signal interfaces, the workload is extremely large and the testing time is long. Summary of the Invention

[0005] The present invention aims to provide a signal interface generation method and system based on HIL testing, which can improve the testing efficiency.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] First solution, a method for generating a signal interface based on HIL testing, includes: A: Configure and read a Veristand project, obtain an initial signal interface, configure the Veristand project according to the initial signal interface, automatically read the initial signal interface and its properties in the Veristand project, and generate corresponding first association information for each initial signal interface and its properties; the first association information includes the initial signal interface properties and the property information of each level attached to it; B: Divide the first association information, and make a first-level area division for different first association information according to the property characteristics of the first association information; C: Customize the first screening information, screen the first association information, and generate customized first screening information from the screened first association information; D: Edit the Simulink project, automatically generate corresponding second signal interfaces in the Simulink project according to the first screening information, and make a second-level area division for different second signal interfaces according to the second signal interfaces and their interface properties; E: Generate a target mapping file, generate corresponding mapping interfaces one by one according to the initial signal interface and the second signal interface, and automatically generate corresponding mapping files one by one according to different mapping interfaces.

[0008] Beneficial effects: First, obtain the initial signal interface by automatically reading the initial signal interface and its properties in the Veristand project; and, automatically generate the signal interfaces and their properties in the Simulink project according to the generated customized first screening information, significantly reducing the workload of user configuration. In existing HIL testing, users need to manually build and configure a large number of signal interfaces, which is not only time-consuming but also error-prone. However, this solution automatically reads the initial signal interface and its properties in the Veristand project, screens them, and generates corresponding second signal interfaces in the Simulink project, greatly improving the configuration efficiency.

[0009] Secondly, by automatically making a first-level area division for the first association information, automatically screening the first association information and generating customized first screening information, and automatically generating mapping files, the workload of manual mapping is reduced, and at the same time, the workload of users in the process of signal interface configuration and mapping is reduced. At the same time, errors caused by manual configuration are avoided, thereby improving the construction efficiency of the test environment, such as the Veristand project and the Simulink project, and the reliability of the test.

[0010] Moreover, it supports users to customize filtering conditions and select the generation path. Users can set filtering conditions, select the required first associated information, and generate customized first filtering information and mapping files. This flexibility enables users to quickly configure the required signal interfaces according to different test scenarios and requirements.

[0011] Then, the first filtering information is screened out before the test, avoiding the processing of a large number of irrelevant signals, and automatically generating the second signal interface, reducing the configuration time of the corresponding signal interface in the Simulink project during the test process. In existing HIL tests, users need to screen and analyze all signal interfaces and messages after the test is completed, which not only increases the test time but also may lead to low test efficiency. However, this solution reduces unnecessary signal processing by screening and generating the required signal interfaces before the test, thus shortening the test time.

[0012] Finally, the generated mapping interface and mapping file can be directly used for the construction of the test environment, and it avoids the failure of the test environment construction caused by manual configuration errors. By automatically generating the mapping interface and mapping file, the workload of users during the test environment construction process is reduced. At the same time, it avoids the failure of the test environment construction caused by manual configuration errors and improves the construction efficiency of the test environment.

[0013] Preferably, both the initial signal interface attributes and the second signal interface attributes include interface name, interface type, and interface hierarchical path.

[0014] Beneficial effects: First, by clearly defining the attributes of the initial signal interface and the second signal interface as interface name, interface type, and interface hierarchical path, the identification of signal interfaces becomes clearer and more accurate. This clear attribute definition helps to quickly locate and manage signal interfaces in a complex HIL test environment, reducing confusion or errors caused by unclear interface attributes.

[0015] Secondly, by clarifying the attributes of the initial signal interface, it provides a more accurate basis for subsequent screening steps. Users can more accurately screen out the required signal interfaces according to attributes such as interface name, interface type, and interface hierarchical path. This not only improves the screening efficiency but also reduces the problems of misselection or missed selection caused by unclear screening conditions.

[0016] At the same time, the clear interface attribute definition can better adapt to different types of signal interfaces and complex hierarchical structures. For example, for signal interfaces with multi-level paths, users can more flexibly perform hierarchical division and management. This flexibility is particularly important for dealing with complex automotive control systems (such as CAN networks with multiple ECUs) and can meet the diverse needs of different test scenarios.

[0017] Moreover, when generating the mapping file, explicit interface attributes can ensure the accuracy and reliability of the mapping relationship. Through precise interface names, types, and hierarchical paths, the generated mapping file can more accurately reflect the mapping relationship between signal interfaces, reducing mapping errors caused by unclear attributes. This helps improve the efficiency of setting up the test environment and the reliability of test results.

[0018] Finally, explicit interface attribute definitions contribute to optimizing overall performance and efficiency. By reducing errors and repetitive work caused by unclear interface attributes, tasks such as generating, filtering, and mapping signal interfaces can be completed more efficiently, thereby shortening the test preparation time and improving test efficiency.

[0019] Preferably, in step B, a first-level area division is preset. According to the preset first-level area division, the first associated information is automatically divided into hierarchical areas; each piece of first associated information will be assigned to the corresponding hierarchical area according to its attribute characteristics.

[0020] Beneficial effects: By presetting the first-level area division rules, the first associated information can be efficiently and accurately hierarchically divided automatically without manual operation, thus greatly reducing the workload and error probability of users. This automated hierarchical division method makes the organization of signal interfaces clearer and more orderly, facilitating subsequent filtering and management operations. Especially when facing a complex multi-level signal interface structure, it can significantly improve the processing efficiency of signal interfaces and the speed of setting up the test environment, providing strong support for the smooth progress of HIL testing.

[0021] Preferably, in step C, according to the filtering conditions set by the user, the first associated information is automatically filtered; during the filtering process, all the first associated information is traversed first, and each piece of first associated information is judged one by one according to the filtering conditions to determine whether it meets the filtering conditions; after the filtering is completed, a filtering result list is generated, and the filtering result list contains all the first filtered information that meets the filtering conditions.

[0022] Beneficial effects: Through this automated filtering mechanism, signal interfaces that meet the user's requirements can be quickly and accurately filtered out from a large number of initial signal interfaces, greatly improving the filtering efficiency and reducing the time and effort required for manual filtering. At the same time, the generation of the filtering result list provides a clear basis for subsequent generation of customized first filtered information, ensuring the accuracy and reliability of signal interface filtering, and further enhancing the automation degree and test efficiency of the entire HIL test signal interface generation process.

[0023] Preferably, in step D, according to the first screening information, the corresponding second signal interfaces and signal interface attributes are automatically generated in the Simulink project; corresponding Simulink model components are generated according to each second signal interface attribute, and the second signal interfaces are arranged in the Simulink model according to the second-level area.

[0024] Beneficial effects: By automatically generating the second signal interfaces from the first screening information and automatically generating the corresponding second signal interfaces and signal interface attributes in the Simulink project, the workload of manually configuring interfaces in the Simulink project is significantly reduced, the interface configuration errors caused by human errors are avoided, and the accuracy and efficiency of interface configuration are improved. At the same time, organizing the second signal interfaces in the Simulink model according to the hierarchical area structure makes the management of signal interfaces clearer and more orderly, facilitating subsequent testing and debugging work, and further improving the overall efficiency and reliability of HIL testing.

[0025] Preferably, in step E, the mapping file includes detailed information of the mapping interfaces, and the detailed information includes signal name, signal type, signal range, and mapping relationship.

[0026] Beneficial effects: By recording these key information in detail in the mapping file, users can clearly understand the specific attributes of each signal interface and its mapping relationship between different projects, so as to quickly and accurately complete the connection and configuration of signal interfaces in the HIL test environment. Such a detailed mapping file not only improves the transparency and traceability of signal interface mapping, but also facilitates subsequent test verification and problem troubleshooting, further improving the test efficiency and system reliability.

[0027] The second solution is a signal interface generation system based on HIL testing, including:

[0028] A file configuration module for providing a human-computer interaction interface through which users can configure the Simulink project, the Veristand project, and the automatic generation path of the mapping file;

[0029] A file processing module for automatically reading all signal interface hierarchical paths in the current Veristand project, where the signal interfaces include hardwired signal interfaces, communication signal interfaces, and custom signal interfaces;

[0030] A signal configuration module for providing a human-computer interaction interface to present the attributes such as signal names and hierarchies of all current signals in a type-based interface. The interface provides multiple modes for users to select signals and an option to generate other signal attribute interfaces, and automatically stores the user's selection as a sequence;

[0031] An interface generation module, which is used to automatically generate signal interfaces according to the user's selection. It has the functions of signal name, signal interface module, and automatic standard arrangement of interfaces. It can automatically generate corresponding hierarchical modules, automatically arrange them and their hierarchical names. For CAN signals, it can automatically generate corresponding hierarchies according to the CAN signal name rules and complete the Simulink project configuration;

[0032] A mapping file generation module, which is used to automatically generate corresponding different mapping files one by one according to different mapping interfaces according to the user's selection. The mapping interfaces include hardwired signal interfaces, custom signal interfaces, and CAN signal interfaces; among them, the hardwired signal interfaces include AIO signals and DIO signals.

[0033] Beneficial effects: By integrating a file configuration module, a file processing module, a signal configuration module, an interface generation module, and a mapping file generation module, a full-process automated operation from signal interface reading, screening, generation to mapping file generation is achieved. This systematic solution significantly reduces manual intervention, reduces configuration errors caused by human errors, and improves the efficiency and accuracy of signal interface generation. At the same time, the system provides a flexible human-computer interaction interface, supporting user-defined configuration and selection, meeting the diverse needs under different test scenarios, and greatly enhancing the overall efficiency and user experience of HIL testing.

[0034] Preferably, the human-computer interaction interface provided by the file configuration module includes options for configuring Simulink projects, Veristand projects, and the automatic generation path of mapping files.

[0035] Beneficial effects: By providing options for configuring Simulink projects, Veristand projects, and the automatic generation path of mapping files, users can configure the system more conveniently. This intuitive interface design enables users to quickly set the required project parameters and generation paths, reduces the complexity of manual input and configuration, and further improves the usability and configuration efficiency of the system. At the same time, this flexible configuration method can meet the personalized needs of different users in different test scenarios, ensuring the versatility and adaptability of the system.

[0036] Preferably, the file processing module can automatically read the signal interface resources and their interface attributes in the Veristand project and transfer the read information to the signal configuration module.

[0037] Beneficial effects: By automatically reading the signal interface resources and their attributes in the Veristand project and passing this information to the signal configuration module, the system can efficiently obtain and process the initial signal interface data without manual extraction and input. This not only reduces the workload and error probability of manual operations but also ensures the accuracy and integrity of the signal interface information, providing a reliable data basis for subsequent signal interface screening, generation, and mapping file generation, thereby improving the automation level and operation efficiency of the entire HIL test signal interface generation system.

[0038] Preferably, the interface generation module can automatically generate corresponding levels and signal interfaces in Simulink according to the selection and automatically arrange the generated interfaces in a standardized manner.

[0039] Beneficial effects: By automatically generating corresponding levels and signal interfaces in Simulink according to the user's selection and automatically arranging the generated interfaces in a standardized manner, the system can efficiently complete the generation and organization of signal interfaces. This automatic generation and arrangement method not only reduces the workload of manually configuring interfaces but also ensures that the generated signal interface structure is clear and hierarchical, facilitating subsequent testing and debugging. At the same time, this standardized interface generation method further improves the overall efficiency and reliability of the system, providing strong support for the smooth progress of HIL testing. Description of the Drawings

[0040] Figure 1 It is a schematic diagram of a signal interface generation method based on HIL testing for Embodiment 1;

[0041] Figure 2 It is a schematic diagram of a signal interface generation system based on HIL testing for Embodiment 3;

[0042] Figure 3 It is a schematic structural diagram of a signal interface generation system based on HIL testing for at least one embodiment;

[0043] Figure 4 It is a schematic diagram of the electronic device structure of a signal interface generation system based on HIL testing for at least one embodiment. Detailed Implementation Manner

[0044] The following is further detailed through specific implementation manners:

[0045] In the prior art, the user manually creates and constructs a Simulink project, and constructs a target signal interface in the Simulink project. Each target signal interface corresponds to a signal. A test project of a vehicle-mounted system can have hundreds or thousands of signals. The target interface is a test signal included in the environment construction for HIL testing. Manually construct the Simulink project in advance, and use it to establish a Simulink model in the Simulink project, and match through the Simulink interface and the target interface built in the Simulink model. At the same time, it is also necessary to create a Veristand project, implant the target interface into the Veristand project, import the Simulink model into the Veristand project, and map the Simulink interface to the corresponding interface of the Veristand project. Since Simulink and Veristand are two different tools, when generating the target signal interface in HIL testing, it is necessary to map the signal interface in the Simulink project and the signal interface in the Veristand project. According to the mapping method of the prior art, it is necessary to manually construct and match hundreds or thousands of signals in different projects, which not only has low test efficiency, but also does not actually need to observe such a large number of signals when doing different HIL tests, resulting in low utilization rate.

[0046] Hereinafter, embodiments of the technical solution of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and therefore are only examples and cannot be used to limit the protection scope of the present invention.

[0047] It should be noted that unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meaning understood by those skilled in the art to which the present invention belongs.

[0048] The reference numerals in the accompanying drawings of the specification include:

[0049] A signal interface generation system 100, a processor 101, an input device 102, an output device 103, a memory 104, a bus 105, and a computer program 1041 based on HIL testing.

[0050] Embodiment 1

[0051] As Figure 1 shown, this embodiment provides a signal interface generation method based on HIL testing, which specifically includes:

[0052] A: Configure and read the Veristand project, obtain the initial signal interface, configure the Veristand project according to the initial signal interface, automatically read the initial signal interface and the initial signal interface attributes in the Veristand project, and generate the corresponding first association information for each initial signal interface and the initial signal interface attributes; the first association information includes the initial signal interface attributes and the attribute information of each level attached to it.

[0053] Specifically, obtain the initial signal interface, then open the Veristand software and create a new project file. During the creation process, the user needs to input the basic information about the Veristand project, and the basic information includes the project name and the project description. According to the test requirements, select the corresponding initial signal interface configuration. In one implementation, if the test involves the chassis control system of a vehicle, the corresponding chassis control hardware module can be selected. In the Veristand project, complete the configuration required for testing the chassis control system of the vehicle, including the CAN interface and the hardwired interface. These configurations include the signal interface definitions and the test logic required for the test. When the Veristand project is established, start the signal interface scanning program. This program traverses all the signal interface resources in the Veristand project through a preset conventional interface scanning algorithm. The signal interface resources include analog input / output (AIO), digital input / output (DIO), and controller area network (CAN) interface types. For each type of interface, by reading its detailed attribute information, the attribute information includes the interface name, the interface type, the interface hierarchy path, the signal name, the signal type, and the signal range. In one implementation, for a CAN interface, its CAN channel number, message ID, and signal name and other attribute information will be read. These attribute information will be stored in the database for subsequent processing.

[0054] After obtaining the corresponding initial signal interface and its interface attributes through the database, in the user interface of the Veristand project, display all the read initial signal interfaces and the first association information corresponding to their attributes in the form of a table or a tree diagram. The user can intuitively view the detailed information of these first association information through the interface. At the same time, the interface provides search and filtering functions, and the user can quickly locate the required first association information according to the filtering conditions such as the signal name, the interface type, and the hierarchy path.

[0055] The first association information includes the initial signal interface attributes and the attribute information of each level attached to it. Each level of the CAN signal interface includes CAN channel, CAN TX or CAN RX, ECU, message, and signal.

[0056] B: Divide the first associated information and perform first-level regional division on different first associated information according to the attribute characteristics of the first associated information.

[0057] Specifically, according to the first associated information, corresponding first-level regional division is performed on its attribute information. The division of the first-level regions is based on the type, hierarchical path, and signal name of the first associated information. In one implementation, for the CAN signal interface, it is divided into different hierarchical regions according to the CAN channel number and message ID. Each CAN channel number corresponds to a top-level region, and each message ID corresponds to a sub-region. Within the sub-region, the signal levels are further divided according to the signal name. For the AIO signal interface, it is divided into different hierarchical regions according to the board information and port number. Each board corresponds to a top-level region, and each port number corresponds to a sub-region. For the DIO signal interface, it can be divided into different hierarchical regions according to the board information and port type (input or output) of the initial signal interface. Each board corresponds to a top-level region, and each port type corresponds to a sub-region.

[0058] There is a preset first-level regional division. According to the preset first-level regional division, the first associated information is automatically divided into hierarchical regions; each first associated information will be assigned to the corresponding hierarchical region according to its attribute characteristics. In the interface, the structure of the divided first-level regions will be displayed in the form of a tree diagram. The user can view the types, hierarchical paths, and signal names of the first associated information in different hierarchical regions by expanding or collapsing the nodes of the tree diagram.

[0059] At the same time, the user can customize the function of the first-level regional division. The user can adjust the division rules of the first-level regions according to actual test requirements. In one implementation, the user can move the specified first associated information from one hierarchical region to another, or create a new hierarchical region. The user can perform custom operations on the hierarchical regions through the operation buttons or menu options provided in the interface. By updating the hierarchical region structure in real time, the latest division results of the hierarchical regions are displayed in the user interface.

[0060] In one implementation, the CAN signal is in dbc structure, and the CAN parent-child hierarchy includes CAN channels, ECUs, messages, and signal names. Since the number of signal quantities in the dbc structure is large, there can be hundreds of sub-signals in its lower layer. Without a hierarchy, the objectivity for users is poor, and corresponding division is performed by reading the different naming rules of the lower-layer sub-signals of the CAN signal. In this embodiment, the difference between the first associated information and the initial signal interface is that the first associated information is the information reflected by the initial signal interface in software. That is, the interface attributes of the initial signal interface are the attribute characteristics of the first associated information, and at the same time, the first associated information also includes each parent-child hierarchy to which all signals belong.

[0061] C: Customize the first screening information, screen the first associated information, and generate customized first screening information from the screened first associated information.

[0062] Specifically, by providing multiple screening conditions, users can screen according to the attribute information of the first associated information, such as different hierarchical regions, signal names, signal types, signal ranges, etc. to which the first associated information belongs. In one implementation, the user can choose to screen out all signal interfaces under the target CAN channel number, or screen out signal interfaces whose signal names contain the keyword name of the initial signal interface. The screened first associated information will be used as the first screening information, and the first screening information will be used for the next step of configuring the Simulink project. In this embodiment, combined screening conditions are also supported, and the user can set multiple screening conditions at the same time to accurately screen out the required signal interfaces.

[0063] Automatically screen the first associated information according to the screening conditions set by the user; during the screening process, first traverse all the first associated information, and judge whether each first associated information meets the screening conditions one by one according to the screening conditions; after the screening is completed, generate a screening result list, and the screening result list contains all the first screening information that meets the screening conditions. The screening result list will be displayed in the interface in the form of a table or a tree diagram.

[0064] Automatically generate customized first screening information according to the screening results. The first screening information is a set of the screened first associated information and is used for subsequent signal interface generation and mapping operations in configuring the Simulink project.

[0065] Specifically, the first screening information is the screened signal. When generating the first associated information, the attribute information of each first associated information regarding the corresponding initial signal interface will be retained and organized according to the first-level region structure. In this way, users can intuitively view and manage the first screening information through the interface. By selecting the corresponding first screening information, generally screening out the required signals, other signal and interface attribute information is not required, reducing the complexity of the Simulink model. In the subsequent configuration of the Simulink project, only this signal interface needs to be generated. The interface attributes of this signal interface only include the attribute characteristics corresponding to the screened signal, and this signal interface is the second signal interface.

[0066] D: Edit the Simulink project, automatically generate the corresponding second signal interface in the Simulink project according to the first screening information, and make a second-level region division for different second signal interfaces according to the second signal interface and its interface attributes.

[0067] Specifically, open the Simulink software and create a new Simulink project file. During the creation process, the user needs to input the basic information of the Simulink project, and the basic information includes the project name and project description. In another implementation manner, it can also be an existing Simulink project, and the first screening information is used to automatically generate corresponding second signal interfaces in the specific Simulink project.

[0068] According to the attribute characteristics of the first screening information, corresponding second signal interfaces and the interface attributes of the second signal interfaces are automatically generated in the Simulink project. For each second signal interface, corresponding Simulink model components are generated according to its attribute information. In one implementation manner, for a CAN signal interface, a CAN receiving module and a CAN sending module are generated, and the parameters of its receiving module and sending module are set according to the signal name and signal attributes. At the same time, the second signal interfaces automatically generated by the CAN signal interface are organized in the Simulink model according to the second-level area structure. In this way, the user can intuitively view and manage the second signal interfaces through the hierarchical area structure.

[0069] In the user interface of the Simulink project, the generated second signal interfaces and their attributes are displayed in a graphical manner, and the second signal interfaces are divided into second-level areas. Specifically, corresponding second signal interfaces and signal interface attributes are automatically generated in the Simulink project according to the first screening information. Corresponding Simulink model components are generated according to the attributes of each second signal interface, and the second signal interfaces are arranged in the Simulink model according to the second-level area. The user can intuitively view and edit the attribute information of these interfaces through the interface. Moreover, the user can customize the functions of the interface attributes. The user can adjust the attribute information of the second signal interface according to the actual test requirements. In one implementation manner, the user can modify the signal name and signal range, and according to the modified attribute information, the second signal interface information in the Simulink model is updated in real time, and the latest interface status is displayed in the user interface. The attribute information of the second signal interface is based on the first screening information. In one implementation manner, for the sorting of CAN signals in the Simulink model, the second-level area division includes CAN TX or CAN RX, CAN channel, ECU, message, and signal name.

[0070] E: Generate a target mapping file, generate corresponding mapping interfaces according to the initial signal interfaces and the second signal interfaces, and automatically generate corresponding mapping files according to different mapping interfaces.

[0071] For each initial signal interface and the corresponding second signal interface, a corresponding mapping interface is generated according to its attribute information, that is, the first associated interface and the second signal interface are mapped accordingly. In one implementation, for a CAN signal interface, a CAN signal mapping interface is generated, and the parameters of the mapping interface are set according to the signal name and signal attributes.

[0072] Specifically, according to the signal interface information in the first associated interface and the second signal interface, a corresponding mapping interface is generated. The mapping interface is the mapping relationship between the first associated interface and the second signal interface, and is used to implement signal transmission and conversion. According to the generated mapping interface information, a corresponding mapping file is automatically generated. The mapping file contains the detailed information of the mapping interface, and the detailed information includes signal name, signal type, signal range and mapping relationship. At the same time, the generated mapping file will be saved in the specified path. Users can find and use these mapping files through a file browser.

[0073] In the user interface for generating the mapping file, the generated mapping interface and its detailed information are displayed in tabular form. The information in the table includes signal name, signal type, signal range and mapping relationship, and users can view the detailed content of all mapping interfaces through the scroll bar. At the same time, an editing function for the mapping interface is provided, and users can directly modify the parameters of the mapping interface by double-clicking the file content containing the corresponding information of the mapping interface. In one implementation, users can adjust the mapping relationship of the signal, or modify the range and type of the signal, and then save the user's modification to the mapping interface in real time and update the content of the modified mapping file. Users can view the generation status of the mapping file in the interface, including the generation progress and the file size.

[0074] The format of the mapping file adopts the TXT format. In one implementation, for the mapping file generated in the full selection mode, the name can be AllSignals_Mapping.txt; for the mapping file selected manually, the name can be ManualSelection_Mapping.txt. Moreover, users are supported to customize the storage path of the mapping file. Users can select a directory in the interface and save the generated mapping file to that directory. Users can quickly find and use these mapping files through a file browser. At the same time, the storage path and file name of the mapping file will be displayed in the user interface for the convenience of users to confirm and record.

[0075] In the HIL test environment, users can import the generated mapping files through different interfaces in Veristand and Simulink projects. In the Veristand project, users load the mapping files into the project. The Veristand project automatically generates the mapping files based on the information in the mapping files and imports them into the Veristand project. Users can quickly complete the connection and configuration of the signal interface, greatly reducing the workload and error rate of manual configuration.

[0076] Specifically, users can intuitively view the currently required signals. CAN signals and hard-wired signals are different types, so they are currently generated separately. Different mapping files will also be generated accordingly. If the user actually needs the Simulink project to be automatically generated, it is necessary to clarify which signal interface to generate. At the same time, it also supports automatic full selection and manual selection. Automatic full selection and manual signals are definitely partially repeated. Automatic full selection will include manual ones. All generated mapping files are also distinguished by different names. In this way, when users actually use it, if they need the full set of mapping file information, they can import the full selection. If they only need the mapping information file of a subset, they can import the manual selection. If they are repeated and meaningless, the mapping file will be automatically generated after the user selects it. The file name is automatically generated. The user finds the generation path location configured when the file is imported, and finds the specific mapping file according to the name. In this way, the generation of multiple repeated signal interfaces can be avoided, which not only occupies memory resources, but also occupies the corresponding computing memory during the test process, reducing the test efficiency.

[0077] In one embodiment, in order to improve the operating efficiency, multi-threaded processing technology is adopted. In the process of reading, screening, generating and mapping files of signal interfaces, multiple threads are started for parallel processing, which greatly shortens the operation time. At the same time, data storage and reading are optimized. By adopting an efficient database management mode, this mode can quickly store and read a large amount of signal interface information and mapping file contents, thereby improving the response speed. Secondly, the user interface is optimized and a responsive design is adopted. The user interface can automatically adjust the layout according to different screen sizes and resolutions to ensure that users can get a good operating experience on different devices.

[0078] Specifically, in terms of function expansion, it supports user-defined signal interface types and attributes. Users can define new signal interface types and attributes according to actual test requirements and add them. It will automatically read, filter and generate operations based on the user-defined signal interface types and attributes.

[0079] In one implementation, different mapping files are generated. For example, the CAN signal interface and the hardwired signal interface are different, and different types of combinations are generated, resulting in different mapping files with different contents. When only one mapping file is generated, content duplication is likely to occur, and it will overwrite previously potentially useful content. Therefore, different mapping files are generated according to different selection modes (automatic selection, manual selection, hardwired signal, CAN signal).

[0080] In steps A, B, C, D, and E, although there is no specific step sequence, in this embodiment, the arrangement order of ABCDE can be followed to implement a signal interface generation method based on HIL testing.

[0081] Specifically, the user configures the Veristand project and the Simulink project file, and at the same time, the user selects the generation path of the mapping file. By automatically reading all the initial signal interfaces and interface attributes of the Veristand project, in the interactive interface, the user can automatically divide the areas for displaying signal interfaces such as CAN or hardwired signals according to the signal type, and present the first associated information corresponding to the initial signal interfaces according to the interface. The interactive interface provides signal automatic full selection or manual selection modes, and options such as whether to generate associated modules, such as the Switch module, for the user to select, and the user can customize the generation of the first screening information. According to the first screening information screened by the user, the second signal interfaces are automatically generated on the Simulink project file, and each second signal interface corresponds to a second-level area, and the interface attributes of the second signal interfaces are automatically generated. The interface attributes of the second signal interfaces include signal names and automatic arrangement of signal interfaces. At the same time, signal level modules are automatically generated and automatically arranged, the CAN signal interface automatically generates the corresponding level, and associated modules are automatically generated to complete the configuration of the Simulink project. Different mapping files are generated according to the initial signal interfaces and the second signal interfaces screened by the user, and the fixed path selected by the user in the interface is automatically generated.

[0082] Advantages of this embodiment

[0083] This embodiment realizes the reading and processing of the Veristand project, the configuration of the Simulink tool, and the human-computer interaction with the user. Thereby, it fully reduces the workload of manual project configuration, greatly improves the efficiency and accuracy of project configuration, and improves the convenience of project configuration. For example, automatic reading and processing of the interface and files, automatic generation of interfaces, automatic generation of mapping files, etc., so that the user can conveniently and quickly complete the project configuration in HIL testing. By combining the interactive interface and automatic generation, it not only ensures the user's need for custom configuration, but also is flexible and convenient by improving efficiency. It provides a project selection interface and multiple options for interface configuration, which not only meets the user's customization needs but also ensures that the user can quickly generate all with one key, taking into account both efficiency and user experience.

[0084] Specifically, in the prior art, especially in the current automotive field where there is a large demand for signal interface processing, users need to build an initial signal interface for the required signals in various signals in the Veristand project, and correspondingly build a Simulink project in advance and build a corresponding second signal interface. The second signal interface includes a hierarchical configuration, a signal interface name configuration, and a signal interface type configuration. At the same time, the second signal interface in the Simulink project and the initial interface signal in the Veristand project need to be manually mapped synchronously, which is not very convenient for users to operate because these are two independent test tools and do not have the function of automatic interface adaptation.

[0085] At present, the automatic signal mapping method in HIL testing with patent application number CN202210329687.8 only automatically maps two signals in different engineering files, which can only realize the automation of signal interface mapping to a certain extent, and does not reduce the time of setting up the test environment too much.

[0086] The current vehicle systems are becoming more and more complex, and the related interactive systems are complex and numerous. The systems under test involve a large number of signals and levels, and different tests require different signals, messages, ECUs, and channels. In the prior art, it is necessary to manually build the second signal interface and related attributes in the Simulink project, which requires a large amount of manpower to synchronously build different second signal interfaces or a single person to spend a lot of time to build all the second signal interfaces, resulting in very low efficiency, a large number of orders of magnitude, and manual construction and screening, which is prone to errors and increases debugging costs. In addition, due to the large number of signals, there are about thousands of them. When users cannot obtain the screening information in a timely manner, such as when the car company does not provide the signals required for the test, or when new users do not understand the specific signals corresponding to the test. Most of the time, all signal interfaces corresponding to each other are built in the Simulink project and the Veristand project simultaneously, and all signal interfaces are mapped. First, a large number of Simulink signal constructions lead to redundant models. Complex models may lead to poor test performance. Secondly, the construction of a large number of model signals and levels requires a lot of manual screening. After executing the HIL test, a test report is obtained. This test report is attached with the corresponding information of the signal interface and its attached messages. The user needs to judge the corresponding test situation through specific test information. In this way, the message is screened accordingly after obtaining the test report results. Not only in the execution of HIL test, due to too many signal interfaces in the model, the test efficiency and test performance are affected, resulting in slow completion of HIL test and distortion. At the same time, after completing the HIL test and obtaining the test report, a large number of messages need to be screened, which further reduces the efficiency of HIL test report analysis.

[0087] At this time, in order to first screen the signal interfaces and then conduct HIL tests, those skilled in the art need to manually create and build a Simulink project, and build the required target signal interfaces in the Simulink project. Each target signal interface can contain hundreds or thousands of signals. Manually building the target signal interfaces in the Simulink project and making corresponding hierarchical divisions of the target signal interfaces in the Simulink project are required. Depending on the complexity of the model, such as a complex model that may take weeks or months to complete the corresponding construction. In this embodiment, the corresponding hierarchy is automatically generated according to the signal name rule, and a clear second-level division is made in the Simulink project. This clear hierarchical structure facilitates users to view, screen, and manage the second signal interfaces. By screening and generating the required first screening information before testing, the processing of a large number of irrelevant signals is avoided, thus reducing the test time and the consumption of computing resources. This optimization makes the HIL test more efficient, especially effective when dealing with complex automotive control systems. Under normal circumstances, it only takes seconds to complete the construction of the Simulink project and the mapping of signals.

[0088] Secondly, first configure the Veristand project. Then, after making the first-level area division according to the initial signal interfaces and their attributes read by the Veristand project, the user can screen the required first associated information. The screened first associated information is used as the first screening information. The second signal interfaces are correspondingly generated in the Simulink project according to the first screening information, and a target Simulink model is generated. This target Simulink model can be directly used for HIL testing, and the Simulink model already contains specific levels, which is convenient for quickly locating specific signals in Simulink, and the Simulink interface has good observability, accelerating the configuration efficiency, reducing the back-and-forth configuration time or configuration manpower of the project, reducing the construction time and construction difficulty of the Simulink model. It only takes one person seconds to complete the construction of the Simulink project. At the same time, the test report generated according to steps ABCDE can also comprehensively and accurately reflect the test results required by the user.

[0089] Subsequently, the beneficial effect of adopting the ABCED step sequence in the first embodiment is that this embodiment does not require creating an additional tool or step to obtain the initial signal interface as the database source for maintenance or update. In this way, when conducting different test projects, the database needs to be frequently updated and maintained to accurately complete different tests. By executing step A first, the initial signal interface is directly read from the Veristand project, which can be achieved without a large database, reducing the memory occupancy, the maintenance and update of the database, and lowering the cost. Moreover, the finally generated Simulink model and mapping file will be applied in the Veristand project, so the link and workload of automatically generating the Simulink signal interface and mapping file are simplified to the greatest extent, and the configuration efficiency before HIL testing is accelerated.

[0090] In addition, the first embodiment provides the function of user-defined screening conditions and generation paths. Users can flexibly select signal interfaces according to actual test requirements and generate customized mapping files. This flexibility enables the system to adapt to different test scenarios and requirements and meet the personalized requirements of users.

[0091] Then, by using the ABCDE steps instead of the existing test steps, the configuration errors caused by human errors are reduced, and the efficiency of setting up the test environment and the reliability of test results are improved.

[0092] Finally, for complex signal interfaces such as CAN signal interfaces, the first embodiment can automatically generate corresponding levels according to the signal name rules and perform clear level division in the Simulink project. This clear level structure is convenient for users to view and manage signal interfaces, improving the maintainability and readability of the system.

[0093] Second Embodiment

[0094] Different from the first embodiment, in step B, the corresponding initial signal interfaces are automatically screened according to the project name of the current Veristand project. Users can judge whether the automatically screened signal interfaces are complete or the required initial signal interfaces. If the signal interfaces do not meet the requirements of the target test, they can manually screen again and generate customized first screening information for the screened initial signal interfaces.

[0095] Specifically, according to the current Veristand project name, such as when the Veristand project name is steering test, actively retrieve or select EPS-related messages. If the Veristand project name is an ADAS project, actively retrieve and select radar / camera EPS / ESC-related module messages. After selection, the messages will be displayed on the interface, and the user confirms by clicking the generate button.

[0096] Beneficial effects of this embodiment

[0097] Divide the initial signal interfaces, and make hierarchical area division for different initial signal interfaces according to the initial signal interface attributes. Considering that there are multiple levels of initial signal interfaces, although this can enable corresponding hierarchical division of signals, reduce the time for users to screen, and thus reduce the test time. Moreover, compared with the prior art where the message screening is carried out after completing the full test, or each initial signal interface is matched in the early stage and cannot be selected autonomously during the process, the matching rate is greatly reduced and the test time is increased. However, through Embodiment 1 and this embodiment, the corresponding initial signal interfaces are automatically screened according to the project name of the created Veristand project, which not only speeds up the screening time, but also can accurately determine the initial signal interfaces required by the user according to the project name of the current Veristand project.

[0098] Embodiment 3

[0099] Different from the foregoing, this embodiment provides a signal interface generation system based on HIL testing, which is used to execute a signal interface generation method based on HIL testing in the foregoing embodiment. This system is used to execute a signal interface generation method described in Embodiment 1. As Figure 2 shown, a signal interface generation system based on HIL testing includes a file configuration module, a file processing module, a signal configuration module, an interface generation module, and a mapping file generation module. In the project construction stage, the file reading and processing module automatically extracts the AIO / DIO interfaces and their attributes from the Veristand project file configured by the user for automatically generating AIO model interfaces and mapping files. The interface presentation module automatically presents the current AIO / DIO interface resource information for the user to view and operate, and automatically reads the AIO interfaces and attributes selected by the user. The interface generation module automatically generates corresponding hierarchical and signal interfaces in Simulink according to the currently selected signal sequence. Users can use the generated interfaces for efficient operations. At the same time, the mapping generation module will synchronously create a mapping file between the Simulink interface and the project interface.

[0100] Automatically generate CAN model interfaces and mapping files. During project construction, the file reading and processing module automatically reads the CAN resource signal interfaces in the current project file. The interface presentation module automatically presents the current CAN signal interface resource information for the user to view and operate, and automatically reads the CAN interfaces and attributes selected by the user. The interface generation module automatically generates corresponding hierarchical and signal interfaces in Simulink according to the currently selected signal sequence. Subsequently, users can use the generated interfaces quickly. At the same time, the mapping generation module generates a mapping file between the Simulink interface and the project interface.

[0101] The CAN interface of Simulink is automatically encapsulated in layers. When Simulink automatically generates the CAN interface, it will automatically generate layers according to the signal naming rules, enhancing the readability of the Simulink project.

[0102] The user-defined interface signal generation tool will automatically read the signal layers of the Veristand project and generate a configuration interface accordingly. Users can choose to select all or manually select to customize the generation of interface signals. This embodiment can not only meet the needs of a large number of users to automatically generate signal interfaces (including the automatic setting of attributes such as layers and signal names, as well as the automatic arrangement of interfaces and layer modules), but also be applicable to scenarios where users create a small number or make subsequent iterative modifications.

[0103] Users can customize the selection of projects and generate the mapping file path. Users can create a blank Simulink module in the early stage and customize the selection of a blank custom Simulink project, Veristand project, and the automatic generation of the mapping file path through the tool interface. For manual, automatic, hardwired, and CAN types, the tool can automatically distinguish, name, and generate the mapping file.

[0104] When importing an interface using a Veristand project, each CAN channel needs to be configured with a DBC file to parse and verify all CAN messages and signals of that channel. When generating signals for multiple CAN channels, the Veristand project file can include multiple CAN channels, which involves a lot of CAN messages and information. According to conventional tests, it is usually not necessary to process too many signals on the HIL test platform. HIL is mainly used to test the functions of a single ECU. For this function, it may only be necessary to obtain some messages and specific signals contained in several nodes in a certain CAN channel of the whole vehicle.

[0105] Specifically, taking one CAN channel as an example, it may contain 10 ECUs, each ECU has 10 messages, and each message contains 20 signals. In this way, the total number of signals in all CAN channels may reach several hundred or even thousands. If all these signals are to be mapped, it means that the corresponding number of interfaces need to be added in the Simulink project. However, the existing technology (such as the method for automatically mapping signals in the HIL test with the patent application number CN202210329687.8) can only automatically generate the mapping file and does not yet have the function of generating interfaces. In contrast, this embodiment not only realizes the automatic generation from automatic mapping to interfaces, but also provides a complete function for automatically generating HIL test interface signals. At the same time, it also has a hierarchical structure, dividing several hundred or even thousands of signals into layers, which is convenient for users to operate and view.

[0106] Meanwhile, a manually selectable method is also provided to allow users to select the signals that are truly useful and needed. This reduces the test workload and time, and is more flexible. Finally, for example, for hardwired signals, when establishing a Veristand project, there may be multiple hardwired signals. Hardwired signals include AI, AO, DI, and DO signals, and each hardwired signal contains many ports. Users only need a few ports and can make corresponding selections, so there is no need to generate all interfaces.

[0107] Immediately afterwards, during the HIL project debugging process, for example, when the user updates the original Veristand project, such as adding signals or debugging the original Veristand project, the signals that may be changed are not all. For example, if a message is added to the dbc file, then a corresponding set of signals is added to the Veristand file. There is no need to generate all interfaces. After making some logical changes to the Simulink interface generated by the customer before, regenerating may overwrite it. In this case, only generate interfaces for the added signals separately.

[0108] If the user does not need to obtain all signals and automatically generate all Simulink interfaces, the corresponding modules in the Simulink file may be relatively large, and the additional interfaces are actually redundant. For example, subsequent Simulink debugging and compilation may take a relatively long time, which instead lengthens the project setup time.

[0109] Configure the target Simulink project and the target Veristand project, and generate the interface of the target Simulink project and the target mapping file that maps to the interface of the target Veristand project. The target mapping file includes the generation path that maps the interface of the target Veristand project and the interface of the target Simulink project.

[0110] Read the signal interface resources of the target Veristand project. The signal interface resources include AIO, DIO, CAN, and the corresponding hierarchical paths.

[0111] Monitor all the read signals in the display interface according to the signal name and hierarchy. The display interface is used to filter the target signals. Specifically, the display interface provides a full selection and manual selection mode for users to choose. CAN signals generally have a dbc file structure. The hierarchical structure of the interaction interface includes CAN TX or CAN RX, CAN channel, ECU, message, and signal name. Generally, the number of signals in the dbc file is very large, and the number of ECUs and messages is also very large. By using hierarchical classification, it can perform a reading of the current information level from the file. The ECU is extracted according to the signal name naming rule.

[0112] Beneficial effects of this embodiment

[0113] 1) The file processing module automatically reads the signal interface resources in the Veristand project, and the signal configuration module presents the attribute information of the signal interfaces to the user by type. The user can select through the interface, and the system automatically generates the signal interfaces and mapping files according to the user's selection, reducing the workload of manual configuration, with a high degree of automation and improving work efficiency.

[0114] 2) The system can quickly generate the required signal interfaces and mapping files, reducing the workload of the user in the process of signal interface configuration and mapping, avoiding test failures caused by manual configuration errors, and thus improving test efficiency.

[0115] 3) The system provides an automatic full-selection / manual selection mode for the user to choose from, and supports the user to customize the generation of interface signals, which can meet the diverse needs in different test scenarios. The user can flexibly select signal interfaces according to the actual test requirements.

[0116] 4) For the CAN signal interface, the system can automatically generate the corresponding hierarchy according to the signal name rule and complete the Simulink project configuration, making the generated signal interfaces have a clear hierarchical structure, which is convenient for the user to view and manage.

[0117] 5) The system can process multiple signal interface types, such as AIO, DIO, CAN, etc., and supports multiple mapping interfaces, including CAN, AIO, manual, and full selection, etc., with wide applicability.

[0118] 6) By automatically generating signal interfaces and mapping files, the preparatory work before testing is reduced, enabling the user to focus more on the testing itself, thus optimizing the entire testing process.

[0119] 7) In the HIL test, the user can select the generated signal interfaces according to the actual needs, avoiding the processing of a large number of irrelevant signals, thereby reducing the occupation of testing time and computing resources.

[0120] 8) The system provides an intuitive interaction interface, through which the user can intuitively view and operate the process of generating and configuring signal interfaces, enhancing the user experience.

[0121] 9) By automatically generating signal interfaces and mapping files, configuration errors caused by human errors are reduced, improving the efficiency of setting up the test environment and the reliability of test results.

[0122] Example 4

[0123] Different from Example 3, this example provides a signal interface generation system based on HIL testing, as Figure 3As shown in the figure, a signal interface generation system based on HIL testing includes a data analysis module. The data analysis module includes an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the electronic device implements a signal interface generation method according to any one of the above embodiments.

[0124] Specifically, as Figure 4 shown in the figure, the electronic device may include: one or more processors 101, one or more input devices 102, one or more output devices 103, one or more memories 104, and a computer program stored in the memory 104 and executable on the processor. The above-mentioned processor 101, input device 102, output device 103, and memory 104 are interconnected through a bus 105. The memory 104 is used to store the computer program, and the computer program includes program instructions. The processor 101 is configured to call the program instructions to execute the method steps described in the above method embodiments.

[0125] It should be understood that in this embodiment, the so-called processor 101 may be a central processing unit (CPU), and this processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0126] The input device 102 may include a keyboard, etc., and the output device 103 may include a display (such as an LCD), a speaker, etc.

[0127] The memory 104 may include a read-only memory and a random access memory, and provide instructions and data to the processor 101. A part of the memory 104 may also include a non-volatile random access memory. For example, the memory 104 may also store information about the device type.

[0128] In specific implementation, the processor 101, input device 102, and output device 103 described in the embodiments of the present invention may execute the implementation manners described in the relevant embodiments of a signal interface generation method and system based on HIL testing provided by the embodiments of the present invention, which will not be elaborated herein.

[0129] It should be noted that for a more specific description of the working process of the electronic device and the implementation of a signal interface generation method based on HIL testing, please refer to the foregoing method embodiment section and will not be elaborated here.

[0130] Embodiment Five

[0131] Different from the foregoing embodiments, the memory described in this embodiment should be understood in a broad sense. It can not only be a hardware component in a computer system for temporarily storing data, but also a physical medium that can store digital information and be read by a computer. These media can be permanent or temporary, including but not limited to hard disks and solid-state drives.

[0132] Specifically, the memory can be an internal storage unit of the electronic device described in any of the embodiments, such as the hard disk or memory of the system. The memory can also be an external storage device of the system, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a FlashCard, etc. equipped on the system. Further, the memory can also include both the internal storage unit and the external storage device of the system. The memory is used to store the computer program and other programs and data required by the system. The memory can also be used to temporarily store the data that has been output or will be output.

[0133] The memory includes various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0134] In this specification, a large number of specific details are described. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, systems, and technologies are not shown in detail so as not to obscure the understanding of this specification. In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, methods, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this specification.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention, and they should all be covered within the scope of the claims and the specification of the present invention.

Claims

1. A signal interface generation method based on HIL testing, characterized in that, Including: A: Configure and read the Veristand project, obtain the initial signal interface, configure the Veristand project according to the initial signal interface, automatically read the initial signal interface and the initial signal interface attributes in the Veristand project, and generate corresponding first association information for each of the initial signal interface and the initial signal interface attributes; The first association information includes the initial signal interface attributes and the attribute information of each level attached thereto; B: Divide the first association information, and perform a first-level area division on different first association information according to the attribute characteristics of the first association information; C: Customize the first screening information, screen the first association information, and generate customized first screening information from the screened first association information; D: Edit the Simulink project, automatically generate corresponding second signal interfaces in the Simulink project according to the first screening information, and perform a second-level area division on different second signal interfaces according to the second signal interfaces and their interface attributes; E: Generate a target mapping file, generate corresponding mapping interfaces one by one according to the initial signal interface and the second signal interface, and automatically generate corresponding mapping files one by one according to different mapping interfaces.

2. The method for generating a signal interface based on HIL testing according to claim 1, wherein Both the initial signal interface attributes and the second signal interface attributes include an interface name, an interface type, and an interface hierarchical path.

3. The method for generating a signal interface based on HIL testing according to claim 1, wherein In step B, there is a preset first-level area division. According to the preset first-level area division, the first association information is automatically divided into hierarchical areas; each first association information will be assigned to the corresponding hierarchical area according to its attribute characteristics.

4. A signal interface generation method based on HIL testing according to claim 1, characterized in that, In step C, according to the screening conditions set by the user, the first association information is automatically screened; during the screening process, all the first association information is traversed first, and each first association information is judged one by one according to the screening conditions whether it meets the screening conditions; After the screening is completed, a screening result list is generated, and the screening result list contains all the first screening information that meets the screening conditions.

5. A signal interface generation method based on HIL testing according to claim 1, characterized in that, In step D, according to the first screening information, corresponding second signal interfaces and signal interface attributes are automatically generated in the Simulink project; corresponding Simulink model components are generated according to each second signal interface attribute, and the second signal interfaces are arranged in the Simulink model according to the second-level area.

6. The signal interface generation method based on HIL testing according to claim 1, wherein In step E, the mapping file includes the detailed information of the mapping interface, and the detailed information includes a signal name, a signal type, a signal range, and a mapping relationship.

7. A signal interface generation system based on HIL testing, characterized in that, Including: A file configuration module, used to provide a human-computer interaction interface through which users can configure the Simulink project, the Veristand project, and the automatic generation path of the mapping file; A file processing module, used to automatically read all the signal interface hierarchical paths in the current Veristand project. The signal interfaces include hardwired signal interfaces, communication signal interfaces, and custom signal interfaces; A signal configuration module, which is used to provide a human-machine interaction interface, present the attributes such as signal names and hierarchies of all current signals in a type-based interface. The interface provides multiple modes for users to select signals, and provides an option to generate an interface for other signal attributes. The user's selection will be automatically stored as a sequence; An interface generation module, which is used to automatically generate signal interfaces according to the user's selection. It has the functions of signal name, signal interface module, and automatic standard arrangement of interfaces. It automatically generates corresponding hierarchical modules, automatically arranges them and their hierarchical names. For CAN signals, it can automatically generate corresponding hierarchies according to the CAN signal name rules and complete the Simulink project configuration; A mapping file generation module, which is used to automatically generate corresponding different mapping files one by one according to different mapping interfaces according to the user's selection. The mapping interfaces include hardwired signal interfaces, custom signal interfaces, and CAN signal interfaces; among them, the hardwired signal interfaces include AIO signals and DIO signals.

8. The signal interface generation system based on HIL testing according to claim 7, characterized in that, The human-machine interaction interface provided by the file configuration module includes options for configuring Simulink projects, Veristand projects, and the automatic generation path of mapping files.

9. The signal interface generation system based on HIL testing according to claim 7, characterized in that The file processing module can automatically read the signal interface resources and their interface attributes in the Veristand project, and transfer the read information to the signal configuration module.

10. A signal interface generation system based on HIL testing according to claim 7, wherein, The interface generation module can automatically generate corresponding hierarchies and signal interfaces in Simulink according to the selection, and automatically standardize and arrange the generated interfaces.

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