Data filling dynamic control method and system based on pointers

Abstract

The invention discloses a pointer-based data filling dynamic control method and system, the number of times of calling a preset interface by a flash memory controller is reduced through a flash memory cache built-in mapping table, in addition, the setting of writing a small data volume into a first flash memory storage area cache and then writing a large data volume into a second flash memory storage area is adopted, and the data filling dynamic control efficiency is improved. Therefore, the quantity of the filling data required to be filled in the data filling operation link of the single write operation is greatly reduced, so that the data volume of the data written into the storage interval of the flash memory by the host cache is reduced, the utilization rate of the bandwidth resource of the preset interface is improved, and the problem of write amplification is effectively controlled.

Description

Technical Field

[0001] This application belongs to the field of flash memory technology, and particularly relates to a method and system for dynamically controlling data filling based on pointers. Background Art

[0002] Currently, some flash memory products adopt the Host Memory Buffer (HMB) technology to balance cost and performance requirements. The HMB technology means that the host allocates target memory for use by the flash memory device.

[0003] In practical applications, the inventor found that in the scenario of high-frequency requests for front-end data services in such flash memory products, due to the overly frequent invocation of the flash memory controller interface, there are problems of data service delay and instability, which urgently need to be improved and optimized. Summary of the Invention

[0004] This application provides a method and system for dynamically controlling data filling based on pointers, aiming to improve the problems of data service delay and instability caused by overly frequent invocation of the flash memory controller interface in existing flash memory products using the HMB technology in the scenario of high-frequency requests for front-end data services. By reducing the number of times the flash memory controller invokes a preset interface through an internal mapping table in the flash memory cache, and in addition, by first writing a small amount of data into the cache of the first flash memory storage area and then writing a large amount of data into the second flash memory storage area, the number of fill data to be filled in the data filling operation link of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash memory storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem.

[0005] In a first aspect, an embodiment of this application provides a method for dynamically controlling data filling based on pointers, which is applied to a flash memory device. The flash memory controller is communicatively connected to the host controller of the host. The flash memory device includes the flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes the host controller and the host memory module;

[0006] Among them, a first host memory range in the host memory module is configured as the cache range of the flash memory device. The flash memory storage module is configured with a first flash memory storage area and a second flash memory storage area, and the capacity of the first minimum write block of the first flash memory storage area is smaller than the capacity of the second minimum write block of the second flash memory storage area. The flash memory controller accesses the first host memory range through a preset interface;

[0007] Wherein, the flash cache module is used to cache the host memory mapping table and the address mapping table of the flash device. The host memory mapping table includes the address information of the first host memory range and a first pointer, and the first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory range. The address mapping table includes the mapping relationship between the physical address of the data stored in the flash cache module and the logical address of the data, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash storage area, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash storage area;

[0008] The method includes:

[0009] Receiving a first data writing instruction from the host;

[0010] Parsing the first data writing instruction to obtain the first data to be written;

[0011] Querying the host memory mapping table in the flash cache module to obtain the first pointer, and calling the preset interface to cache the first data in the first host memory range according to the first pointer;

[0012] Querying the address mapping table in the flash cache module to obtain the second pointer and the third pointer;

[0013] Calling the preset interface to perform a first data filling operation to obtain a second data that can fill the first minimum writing block; and updating the first pointer of the host memory mapping table;

[0014] Calling the preset interface to write the second data into the first flash storage area according to the second pointer; and updating the second pointer in the address mapping table; and creating a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0015] When it is determined that the size of the third data already written in the first flash storage area is equal to the capacity of the second minimum writing block, writing the third data into the second flash storage area according to the third pointer; and updating the third pointer in the address mapping table; and updating the mapping relationship between the physical address and the logical address of the third data.

[0016] Second aspect, an embodiment of the present application provides a data filling dynamic control system based on pointers, including a host and a flash memory device. The flash memory device is communicatively connected to the host. The flash memory device includes a flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes a host controller and the host memory module;

[0017] Among them, a first host memory range in the host memory module is configured as a cache range of the flash memory device. The flash memory storage module is configured with a first flash memory storage area and a second flash memory storage area. The capacity of the first minimum write block in the first flash memory storage area is smaller than the capacity of the second minimum write block in the second flash memory storage area. The flash memory controller accesses the first host memory range through a preset interface;

[0018] Among them, the flash memory cache module is used to cache the host memory mapping table and the address mapping table of the flash memory device. The host memory mapping table includes the address information of the first host memory range and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory range. The address mapping table includes the mapping relationship between the logical address and the physical address, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory storage area. The third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory storage area;

[0019] The flash memory controller is used to perform the following operations:

[0020] Receive a first data write instruction from the host;

[0021] Parse the first data write instruction to obtain the first data to be written;

[0022] Query the host memory mapping table in the flash memory cache module to obtain the first pointer, and call the preset interface to cache the first data in the first host memory range according to the first pointer;

[0023] Query the address mapping table in the flash memory cache module to obtain the second pointer and the third pointer;

[0024] Call the preset interface to perform a first data filling operation to obtain a second data that can fill the first minimum write block; and update the first pointer of the host memory mapping table;

[0025] Invoke the preset interface to write the second data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0026] When it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, write the third data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the third data.

[0027] It can be seen that in the embodiments of the present application, for the problem of data service delay and instability caused by too frequent calls to the flash memory controller interface in the high-frequency request scenario of the front-end data service of the existing flash memory products using the HMB technology, the number of times the flash memory controller calls the preset interface is reduced by the built-in mapping table in the flash memory cache. In addition, by first writing a small amount of data into the first flash memory storage area for caching and then writing a large amount of data into the second flash memory storage area, the number of padding data to be filled in the data filling operation link of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash memory storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a pointer-based data filling dynamic control system 100 provided by an embodiment of the present application.

[0029] Figure 2 It is a schematic diagram of the processing flow of a pointer-based data filling dynamic control method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0031] In the description, claims, and above-mentioned drawings of this application, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0032] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0033] The "and / or" in the embodiments of this application describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone; both A and B exist simultaneously; B exists alone. Among them, A and B can be singular or plural.

[0034] In the embodiments of this application, the symbol " / " can represent an "or" relationship between the associated objects before and after. Additionally, the symbol " / " can also represent a division sign, that is, perform a division operation. For example, A / B can represent A divided by B.

[0035] The "at least one (item)" or its similar expression in the embodiments of this application refers to any combination of these items, including any combination of single item (s) or plural items (s), and refers to one or more, where multiple refers to two or more. For example, at least one (item) of a, b, or c can represent the following seven situations: a, b, c, a and b, a and c, b and c, a, b, and c. Among them, each of a, b, and c can be an element or a set containing one or more elements.

[0036] The "equal to" in the embodiments of this application can be used in combination with "greater than" and is applicable to the technical solutions adopted when it is greater than, or can also be used in combination with "less than" and is applicable to the technical solutions adopted when it is less than. When "equal to" is used in combination with "greater than", it is not used in combination with "less than"; when "equal to" is used in combination with "less than", it is not used in combination with "greater than".

[0037] First, a basic explanation of the key concepts involved in this application is given.

[0038] (1) Peripheral Component Interconnect Express (PCIe)

[0039] The PCIe interface is a high-speed serial computer expansion bus standard used to connect various components inside a computer, such as graphics cards, solid-state drives, network cards, etc., to achieve high-speed data transmission and communication.

[0040] (2) Solid State Drive (SSD)

[0041] An SSD is a non-volatile storage device based on storage media such as flash chips or DRAM, used to store and retrieve data in computers and other electronic devices, featuring high-speed read and write, low power consumption, strong earthquake resistance, etc.

[0042] (3) Host Memory Buffer (HMB) technology

[0043] In HMB technology, a portion of the address space managed by the host is allocated to the flash controller. The host controller calls the NVMe driver to synchronize the base address and length data of the target memory to the flash controller. The flash controller updates its address mapping table (such as the FTL mapping table) based on this data list for looking up the physical addresses of its own storage blocks. The host controller can store the address mapping table in the target memory area of the host. When the flash controller processes data operation commands, it can access the target memory of the host through the PCIe bus to extract the target physical address corresponding to the target logical address in the command.

[0044] (4) Non-Volatile Memory Express (NVMe) driver

[0045] The NVMe driver is a software program that enables the host system to communicate and interact with storage devices supporting the NVMe protocol. It acts as a bridge between the operating system and the NVMe storage device, responsible for converting the instructions and requests of the operating system into a format that the storage device can understand, and passing the responses and data of the storage device back to the operating system to achieve efficient transmission and processing of data between the host and the storage device.

[0046] (5) Dynamic Random Access Memory (DRAM)

[0047] DRAM is a type of random access memory, which means it allows a computer processor to directly access data in any storage cell, featuring relatively fast data read and write speeds. The "dynamic" aspect emphasizes its storage characteristic, i.e., the stored data needs to be continuously refreshed to maintain its validity. Compared with static random access memory (SRAM), DRAM has a higher integration density and lower cost, but is relatively slower in speed.

[0048] Currently, some flash memory products adopt the host memory buffer (HMB) technology to balance cost and performance requirements.

[0049] In practical applications, the inventors found that in scenarios of high-frequency requests for front-end data services in such flash memory products, due to overly frequent calls to the flash memory controller interface, there are problems of data service latency and instability, which urgently need to be improved and optimized.

[0050] To solve the above problems, this application provides a pointer-based data filling dynamic control method and system. By means of a built-in mapping table in the flash memory cache, the number of calls to the preset interface by the flash memory controller is reduced. In addition, the setting of first writing a small amount of data into the cache of the first flash memory storage area and then writing a large amount of data into the second flash memory storage area greatly reduces the number of filling data to be filled in the data filling operation link of a single write operation. Furthermore, it reduces the amount of data written from the host cache to the flash memory storage area, improves the utilization rate of the bandwidth resources of the preset interface, and effectively controls the write amplification problem, which is beneficial to improving the stability and response ability of flash memory devices adopting the HMB technology in data service processing.

[0051] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a pointer-based data filling dynamic control system 100 provided by an embodiment of this application. As Figure 1 shown, the pointer-based data filling dynamic control system 100 includes a flash memory device 1 and a host 2. The flash memory controller 2 is communicatively connected to the host controller 20 of the host 2. The flash memory device 1 includes the flash memory controller 10, a flash memory cache module 30, and a flash memory storage module 50. The host 2 includes the host controller 20 and the host memory module 40;

[0052] Among them, the first host memory range 41 in the host memory module 40 is configured as the cache range of the flash memory device 1. The flash memory storage module 50 is configured with a first flash memory storage area 51 and a second flash memory storage area 52, and the capacity of the first minimum write block of the first flash memory storage area 51 is smaller than the capacity of the second minimum write block of the second flash memory storage area 52. The flash memory controller 10 accesses the first host memory range 41 through a preset interface (such as a PCIe interface);

[0053] Among them, the capacity of the second smallest write block is an integer multiple of the capacity of the first smallest write block. For example, the capacity of the first smallest write block can be 16 KB, and the capacity of the second smallest write block can be 96 KB.

[0054] Among them, the host memory module 40 can adopt the first DRAM, and the flash cache module 30 can adopt the second DRAM. The cost and performance of the first DRAM are both higher than those of the second DRAM.

[0055] In a possible example, the configuration process of the first host memory range includes the following steps:

[0056] After detecting that the flash device 1 is powered on, perform a self-check operation and obtain the remaining capacity of the storage space in the flash storage module 50 where no data is stored;

[0057] Send a memory configuration request message carrying the remaining capacity to the host controller 20. The memory configuration request message is used to instruct the host controller 20 to perform the following operations: determine a target capacity according to the remaining capacity and the current usage status of the host memory module; and, mark the usage status of multiple host idle cache units whose total marked capacity is the target capacity as flash cache usage status in the host idle cache unit of the host memory module 40; and, create the host memory mapping table according to the memory addresses of the multiple host idle cache units; and, call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash controller;

[0058] Receive the memory configuration response message from the host controller 20;

[0059] Cache the host memory mapping table in the flash cache module 30, and store the host memory mapping table in the flash storage module 50.

[0060] Among them, the current usage status of the host memory module 40 can be the ratio of the used space capacity of the host memory module 40 to the total space capacity and the value of the total space capacity. Moreover, the more the remaining capacity, the smaller the ratio, and the larger the value of the total space capacity, the larger the configurable target capacity. The larger the configured target capacity, the better the stability and performance of data processing of the flash device.

[0061] In one implementation, a parameter table can be pre-configured and stored in the storage module of the host 2. The host controller 20 queries the parameter table to obtain the parameter group entry to which the current parameter value belongs. In addition to the numerical range of the remaining capacity, the numerical range of the ratio, and the numerical range of the total space capacity described above, the parameter entry also includes the value or numerical range of the recommended allocated capacity. The host controller 20 determines the target capacity according to the value or numerical range of the recommended allocated capacity in the parameter group entry.

[0062] In another implementation, a calculation formula can be set in advance according to the correlation relationship between parameters. Subsequently, the host controller 20 substitutes the values of the currently obtained parameters into the calculation formula for calculation, and the obtained calculation result can be used as the target capacity.

[0063] The present application does not uniquely limit the specific implementation manner of the target capacity.

[0064] It can be seen that in this example, since the host controller determines the target capacity of the host memory interval allocated to the flash device based on the remaining storage space of the flash device itself and the usage status of the host memory, it is possible to avoid affecting the stability and performance requirements of the host or the flash device due to an overly large or small allocation of the host memory interval, which is beneficial to improving the running stability of the flash device.

[0065] Among them, the flash cache module 30 is used to cache the host memory mapping table 71 and the address mapping table 72 of the flash device 1. The host memory mapping table 71 includes the address information of the first host memory interval 41 and a first pointer, and the first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory interval 41. The address mapping table 72 includes the mapping relationship between the logical address and the physical address, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash storage area 51, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash storage area 52.

[0066] In a specific implementation, the flash device can use an unsigned integer type to store pointers. For example, use uint32_t (32-bit unsigned integer) or uint64_t (64-bit unsigned integer) to represent pointers, so as to cover different ranges of address spaces. When more information needs to be included in the pointer, a structure type may be used. For example, in addition to the address information, it is also necessary to record the status of the cache unit or storage unit pointed to by the address (such as whether it is valid, whether it has been deleted, etc.), and a structure can be defined:

[0067] typedef struct{

[0068] uint64_t address; / / Storage address

[0069] uint8_t status; / / Storage status information

[0070] }FlashPointer;

[0071] As Figure 2 shown, the schematic diagram of the processing flow of a data filling dynamic control method based on pointers provided by an embodiment of the present application can be applied to the flash memory controller 10 of the flash memory device 1 as Figure 1 shown. The method includes the following steps:

[0072] Step 201, receive a first data write instruction from the host;

[0073] Among them, the first data write instruction may be associated with data paste tasks, data transfer tasks, text editing tasks, etc. in the front-end data task, and is not uniquely limited here.

[0074] Step 202, parse the first data write instruction to obtain the first data to be written;

[0075] Step 203, query the host memory mapping table in the flash cache module to obtain the first pointer, and call the preset interface to cache the first data in the first host memory range according to the first pointer;

[0076] Step 204, query the address mapping table in the flash cache module to obtain the second pointer and the third pointer;

[0077] Among them, the first flash memory area of the flash memory module can be used to store the host memory mapping table, and the second flash memory area of the flash memory module can be used to store the address mapping table.

[0078] Step 205, call the preset interface to perform a first data filling operation to obtain a second data that can fill the first minimum write block; and update the first pointer of the host memory mapping table;

[0079] Among them, the purpose of the data filling operation is to reduce the probability of instability of the flash memory minimum write block caused by flushing flash memory cells with unfilled data, that is, to improve stability.

[0080] In a specific implementation, the data filled in the first data filling operation can be preset dummy data, such as all 0s, all 1s, or a specific byte sequence, and is not uniquely limited here.

[0081] Step 206: Call the preset interface to write the second data into the first flash memory storage area according to the second pointer; update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0082] Step 207: When it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, write the third data into the second flash memory storage area according to the third pointer; update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the third data.

[0083] In a specific implementation, when the flash memory controller writes the third data into the second flash memory storage area according to the third pointer, it includes: detecting whether the third data remains in the data cached in the first host memory area.

[0084] If it is detected that there is no remaining, first read the third data from the first flash memory storage area into the first host memory area, and then flush and write the third data in the order of the storage units in the second flash memory storage area indicated by the third pointer; and perform a garbage collection operation on the first flash memory storage area to recycle the first flash memory storage area.

[0085] If it is detected that there is remaining, directly flush and write the third data in the order of the storage units in the second flash memory storage area indicated by the third pointer; and perform a garbage collection operation on the first flash memory storage area to recycle the first flash memory storage area.

[0086] It can be seen that in this example, the performance and spatial redundancy of the host memory are fully considered, the host memory is fully utilized, the detailed situations of whether the third data remains or not in the first host memory area are accurately detected and identified, and exclusive write operations are performed to adapt to the detailed situations to improve flexibility and applicability.

[0087] In a possible example, the method further includes:

[0088] When it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second minimum write block, receive a second data write instruction from the host.

[0089] Parse the second data write instruction to obtain the fifth data to be written.

[0090] Query the host memory mapping table in the flash cache module to obtain the first pointer, and call the preset interface to cache the fifth data in the first host memory area according to the first pointer.

[0091] Query the address mapping table in the flash cache module to obtain the second pointer and the third pointer;

[0092] Call the preset interface to perform a second data filling operation to obtain a sixth data that can fill the first minimum write block; and update the first pointer in the host memory mapping table;

[0093] Call the preset interface to write the sixth data into the first flash storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0094] When it is determined that the size of the seventh data written in the first flash storage area is equal to the capacity of the second minimum write block, write the seventh data into the second flash storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the seventh data.

[0095] It can be seen that in this example, the flash device can aggregate multiple data of multiple write instructions in the first flash storage area until the sum of the aggregated data is equal to the capacity of the second minimum write unit of the second flash storage area, and then write them into the second flash storage area as a whole. Through the design concept of using the first flash storage area as a temporary storage area and the second flash storage area as a main storage area, it can effectively reduce the amount of data that needs to be filled during the data filling operation in a single data write operation, thereby reducing the amount of data transferred by the flash device and the host when calling the preset interface once, and avoiding the problems of bandwidth resource waste and storage space resource waste caused by transferring a large amount of redundant data.

[0096] It can be seen that in the embodiment of the present application, the flash device adopting the HMB technology reduces the number of times the flash controller calls the preset interface through the built-in mapping table in the flash cache. In addition, by first writing a small amount of data into the first flash storage area for caching and then writing a large amount of data into the second flash storage area, the amount of filling data required in the data filling operation link of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash storage area, improving the utilization rate of the bandwidth resources of the preset interface, effectively controlling the write amplification problem, and being beneficial to improving the stability and response ability of the flash device adopting the HMB technology in data service processing.

[0097] In a possible example, before invoking the preset interface to perform a first data filling operation to obtain second data that can fill the first minimum write block, the method further includes: performing a modulo operation on the size of the first data with respect to the capacity of the first minimum write block to obtain a calculation result; and detecting that the calculation result is not zero;

[0098] The method further includes:

[0099] detecting that the calculation result is zero;

[0100] invoking the preset interface to write the first data into the first flash memory storage area according to the second pointer; and updating the second pointer in the address mapping table; and creating a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0101] In the case where it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, writing the fourth data into the second flash memory storage area according to the third pointer; and updating the third pointer in the address mapping table; and updating the mapping relationship between the physical address and the logical address of the fourth data.

[0102] It can be seen that in this example, the flash memory device dynamically calculates whether to perform a data filling operation, and the data processing process is more accurate and stable.

[0103] As Figure 1 shown, in the pointer-based data filling dynamic control system 100 disclosed in the embodiments of the present application, the flash memory controller 10 is configured to perform the following operations:

[0104] Receive a first data write instruction from the host;

[0105] Parse the first data write instruction to obtain the first data to be written;

[0106] Query the host memory mapping table in the flash memory cache module to obtain the first pointer, and invoke the preset interface to cache the first data in the first host memory interval according to the first pointer;

[0107] Query the address mapping table in the flash memory cache module to obtain the second pointer and the third pointer;

[0108] Invoke the preset interface to perform a first data filling operation to obtain second data that can fill the first minimum write block; and update the first pointer in the host memory mapping table;

[0109] Invoke the preset interface to write the second data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0110] When it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second smallest write block, write the third data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the third data.

[0111] In a possible example, the capacity of the second smallest write block is an integer multiple of the capacity of the first smallest write block.

[0112] In a possible example, the configuration process of the first host memory range includes the following steps:

[0113] After the flash memory controller 10 detects that the flash memory device is powered on, perform a self-check operation and obtain the remaining capacity of the storage space in the flash memory storage module where no data is stored;

[0114] The flash memory controller 10 sends a memory configuration request message carrying the remaining capacity to the host controller, and the memory configuration request message is used to instruct the host controller to perform the following operations: determine the target capacity according to the remaining capacity and the current usage status of the host memory module; and mark the usage status of multiple host idle cache units with the sum of capacities being the target capacity in the host idle cache unit of the host memory module as the flash cache usage status; and create the host memory mapping table according to the memory addresses of the multiple host idle cache units; and call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash memory controller 10;

[0115] The flash memory controller 10 receives the memory configuration response message from the host controller;

[0116] The flash memory controller 10 caches the host memory mapping table in the flash cache module and stores the host memory mapping table in the flash memory storage module.

[0117] In a possible example, before the flash memory controller 10 invokes the preset interface to perform the first data filling operation to obtain the second data that can fill the first smallest write block, it is also used to: perform a modulo calculation on the size of the first data with respect to the capacity of the first smallest write block to obtain a calculation result; and detect that the calculation result is not zero;

[0118] The flash memory controller 10 is further configured to:

[0119] Detect that the calculation result is zero;

[0120] Call the preset interface to write the first data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0121] In the case where it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second smallest write block, write the fourth data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the fourth data.

[0122] In a possible example, the flash memory controller 10 is further configured to:

[0123] In the case where it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second smallest write block, receive a second data write instruction from the host;

[0124] Parse the second data write instruction to obtain the fifth data to be written;

[0125] Query the host memory mapping table in the flash cache module to obtain the first pointer, and call the preset interface to cache the fifth data in the first host memory range according to the first pointer;

[0126] Query the address mapping table in the flash cache module to obtain the second pointer and the third pointer;

[0127] Call the preset interface to perform a second data filling operation to obtain a sixth data that can fill the first smallest write block; and update the first pointer of the host memory mapping table;

[0128] Call the preset interface to write the sixth data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table;

[0129] When it is determined that the size of the seventh data written in the first flash memory storage area is equal to the capacity of the second smallest write block, write the seventh data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the seventh data.

[0130] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0131] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0132] In several embodiments provided by this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the above division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical or other form.

[0133] The units described as separate components above may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, in each embodiment of this application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0135] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the above methods in various embodiments of this application. The aforementioned memory includes: USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks, or optical discs, etc., which are various media that can store program codes.

[0136] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program. This program can be stored in a computer-readable memory, and the memory can include: flash drives, read-only memories (English: Read-Only Memory, abbreviated: ROM), random access memories (English: Random Access Memory, abbreviated: RAM), magnetic disks, or optical discs, etc.

[0137] The above has introduced the embodiments of this application in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on this application.

Claims

1. A dynamic control method for data filling based on pointers, characterized in that, Applied to a flash memory device, the flash memory controller is used for communication connection with a host. The flash memory device includes a flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes a host controller and the host memory module; Among them, a first host memory range in the host memory module is configured as a cache range of the flash memory device. The flash memory storage module is configured with a first flash memory storage area and a second flash memory storage area, and the capacity of a first minimum write block in the first flash memory storage area is smaller than the capacity of a second minimum write block in the second flash memory storage area. The flash memory controller accesses the first host memory range through a preset interface; Among them, the flash memory cache module is used to cache the host memory mapping table and the address mapping table of the flash memory device. The host memory mapping table includes the address information of the first host memory range and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory range. The address mapping table includes the mapping relationship between the physical address and the logical address of the data stored in the flash memory cache module, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory storage area. The third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory storage area; The method includes: Receiving a first data write instruction from the host; Parsing the first data write instruction to obtain the first data to be written; Querying the host memory mapping table in the flash memory cache module to obtain the first pointer, and calling the preset interface to cache the first data in the first host memory range according to the first pointer; Querying the address mapping table in the flash memory cache module to obtain the second pointer and the third pointer; Calling the preset interface to perform a first data filling operation to obtain a second data that can fill the first minimum write block; and updating the first pointer of the host memory mapping table; Calling the preset interface to write the second data into the first flash memory storage area according to the second pointer; and updating the second pointer in the address mapping table; and creating a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, writing the third data into the second flash memory storage area according to the third pointer; and updating the third pointer in the address mapping table; and updating the mapping relationship between the physical address and the logical address of the third data.

2. The method according to claim 1, wherein The capacity of the second minimum write block is an integer multiple of the capacity of the first minimum write block.

3. The method according to claim 2, wherein The configuration process of the first host memory range includes the following steps: After detecting that the flash memory device is powered on, performing a self-check operation and obtaining the remaining capacity of the storage space in the flash memory storage module where no data is stored; Send a memory configuration request message carrying the remaining capacity to the host controller, where the memory configuration request message is used to instruct the host controller to perform the following operations: determine a target capacity according to the remaining capacity and the current usage status of the host memory module; And mark the usage status of multiple host idle cache units whose sum of capacities is the target capacity in the host idle cache unit of the host memory module as the flash cache usage status; And create the host memory mapping table according to the memory addresses of the multiple host idle cache units; and call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash controller; Receive the memory configuration response message from the host controller; Cache the host memory mapping table in the flash cache module and store the host memory mapping table in the flash storage module.

4. The method according to claim 3, wherein Before calling the preset interface to perform the first data filling operation to obtain second data that can fill the first minimum write block, the method further includes: performing a modulo operation on the size of the first data with respect to the capacity of the first minimum write block to obtain a calculation result; and detecting that the calculation result is not zero; The method further includes: Detecting that the calculation result is zero; Call the preset interface to write the first data into the first flash storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the fourth data written in the first flash storage area is equal to the capacity of the second minimum write block, write the fourth data into the second flash storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the fourth data.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: When it is determined that the size of the third data written in the first flash storage area is less than the capacity of the second minimum write block, receive a second data write instruction from the host; Parse the second data write instruction to obtain the fifth data to be written; Query the host memory mapping table in the flash cache module to obtain the first pointer, and call the preset interface to cache the fifth data in the first host memory interval according to the first pointer; Query the address mapping table in the flash cache module to obtain the second pointer and the third pointer; Call the preset interface to perform a second data filling operation to obtain sixth data that can fill the first minimum write block; and update the first pointer of the host memory mapping table; Call the preset interface to write the sixth data into the first flash storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the seventh data written in the first flash memory storage area is equal to the capacity of the second minimum write block, write the seventh data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the seventh data.

6. A pointer-based data filling dynamic control system, characterized in that, It includes a host and a flash memory device, the flash memory device is used for communicating and connecting with the host, the flash memory device includes a flash memory controller, a flash memory cache module and a flash memory storage module, and the host includes a host controller and a host memory module; Among them, the first host memory range in the host memory module is configured as the cache range of the flash memory device, the flash memory storage module is configured with a first flash memory storage area and a second flash memory storage area, and the capacity of the first minimum write block of the first flash memory storage area is smaller than the capacity of the second minimum write block of the second flash memory storage area, and the flash memory controller accesses the first host memory range through a preset interface; Among them, the flash memory cache module is used for caching the host memory mapping table and the address mapping table of the flash memory device. The host memory mapping table includes the address information of the first host memory range and a first pointer, and the first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory range. The address mapping table includes the mapping relationship between the logical address and the physical address, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory storage area, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory storage area; The flash memory controller is used to perform the following operations: Receive a first data write instruction from the host; Parse the first data write instruction to obtain the first data to be written; Query the host memory mapping table in the flash memory cache module to obtain the first pointer, and call the preset interface to cache the first data in the first host memory range according to the first pointer; Query the address mapping table in the flash memory cache module to obtain the second pointer and the third pointer; Call the preset interface to perform a first data filling operation to obtain a second data that can fill the first minimum write block; and update the first pointer in the host memory mapping table; Call the preset interface to write the second data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the third data written in the first flash memory storage area is equal to the capacity of the second minimum write block, write the third data into the second flash memory storage area according to the third pointer; and update the third pointer in the address mapping table; and update the mapping relationship between the physical address and the logical address of the third data.

7. The system according to claim 6, wherein The capacity of the second smallest write block is an integer multiple of the capacity of the first smallest write block.

8. The system according to claim 7, wherein The configuration process of the first host memory range includes the following steps: After the flash memory controller detects that the flash memory device is powered on, it performs a self-check operation and obtains the remaining capacity of the storage space in the flash memory storage module where no data is stored; The flash memory controller sends a memory configuration request message carrying the remaining capacity to the host controller, and the memory configuration request message is used to instruct the host controller to perform the following operations: determine the target capacity according to the remaining capacity and the current usage status of the host memory module; And, mark the usage status of multiple host idle cache units whose total capacity is the target capacity in the host idle cache unit of the host memory module as the flash cache usage status; And, create the host memory mapping table according to the memory addresses of the multiple host idle cache units; and, call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash memory controller; The flash memory controller receives the memory configuration response message from the host controller; The flash memory controller caches the host memory mapping table in the flash cache module and stores the host memory mapping table in the flash memory storage module.

9. The system according to claim 8, wherein Before the flash memory controller calls the preset interface to perform the first data filling operation to obtain the second data that can fill the first smallest write block, it is also used for: performing a modulo operation on the size of the first data with respect to the capacity of the first smallest write block to obtain a calculation result; and, detecting that the calculation result is not zero; The flash memory controller is also used for: Detecting that the calculation result is zero; Calling the preset interface to write the first data into the first flash memory storage area according to the second pointer; and, updating the second pointer in the address mapping table; And, creating a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second smallest write block, writing the fourth data into the second flash memory storage area according to the third pointer; and, updating the third pointer in the address mapping table; And, updating the mapping relationship between the physical address and the logical address of the fourth data.

10. The system according to any one of claims 6-9, characterized in that, The flash memory controller is also used for: When it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second smallest write block, receiving a second data write instruction from the host; Parsing the second data write instruction to obtain the fifth data to be written; Querying the host memory mapping table in the flash cache module to obtain the first pointer, and calling the preset interface to cache the fifth data in the first host memory range according to the first pointer; Querying the address mapping table in the flash cache module to obtain the second pointer and the third pointer; Call the preset interface to perform a second data filling operation to obtain a sixth data that can fill the first minimum write block; and update the first pointer of the host memory mapping table; Call the preset interface to write the sixth data into the first flash storage area according to the second pointer; and update the second pointer in the address mapping table; And create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table; When it is determined that the size of the seventh data already written in the first flash storage area is equal to the capacity of the second minimum write block, write the seventh data into the second flash storage area according to the third pointer; and update the third pointer in the address mapping table; And update the mapping relationship between the physical address and the logical address of the seventh data.

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