Display device and method of driving same

Abstract

The invention relates to a display device and a method of driving the same. The display device includes: a display panel including a plurality of pixels; a power management circuit configured to supply a voltage to the display panel through a power voltage line, and the power management circuit configured to reduce the voltage when a power current of the display panel flowing through the power voltage line is greater than a reference current; and a controller configured to control the power management circuit, and the controller includes: a panel degradation calculator configured to calculate a panel degradation amount of the display panel; a maximum power current calculator configured to calculate a maximum power current of the display panel based on the panel degradation amount; and a reference current calculator configured to calculate the reference current by multiplying the maximum power current by a gain.

Description

Technical Field

[0001] Embodiments relate to a display device for reducing or preventing damage caused by overcurrent, and a method of driving the display device. Background Art

[0002] A display device may include a display panel and a panel driver. The display panel may include a plurality of pixels. The panel driver may include a data driver and a power management circuit. The data driver may provide a data voltage to the pixels. The power management circuit may provide a high power voltage to the pixels through a power voltage line.

[0003] The display device may detect a current flowing through the display panel by measuring a power current flowing through the power voltage line. When the power current is greater than a reference current (e.g., a predetermined reference current), the power management circuit may reduce the high power voltage to reduce or prevent an overcurrent flowing through the display panel.

[0004] As the driving time of the display panel increases, the pixels may deteriorate, and the driving current flowing through the light-emitting elements included in the pixels may decrease. To compensate for the deterioration of the display panel, the data voltage provided to the pixels may increase, and thus, the driving current flowing through the light-emitting elements included in the pixels may increase. Summary of the Invention

[0005] Embodiments provide a display device for controlling a high power voltage in consideration of an increase in power current caused by deterioration compensation of a display panel, and a method of driving the display device.

[0006] Embodiments provide a display device for reducing power consumption, and a method of driving the display device.

[0007] A display device according to an embodiment may include: a display panel including a plurality of pixels; a power management circuit configured to provide a voltage to the display panel through a power voltage line, and the power management circuit is configured to reduce the voltage when a power current flowing through the power voltage line of the display panel is greater than a reference current; and a controller configured to control the power management circuit, and the controller includes: a panel deterioration calculator configured to calculate a panel deterioration amount of the display panel; a maximum power current calculator configured to calculate a maximum power current of the display panel based on the panel deterioration amount; and a reference current calculator configured to calculate the reference current by multiplying the maximum power current by a gain.

[0008] The panel deterioration calculator may include: a block stress accumulator configured to calculate a plurality of lifetimes of a plurality of blocks each including at least one pixel among the plurality of pixels by accumulating a plurality of stresses of the plurality of blocks; and a block deterioration calculator configured to calculate a plurality of block deterioration amounts of the plurality of blocks based on the plurality of lifetimes of the plurality of blocks.

[0009] The panel degradation amount can be equal to the maximum block degradation amount among a plurality of block degradation amounts.

[0010] The controller may further include: a degradation compensator configured to convert input image data into output image data based on a plurality of block degradation amounts.

[0011] The controller may further include: a sensing circuit configured to measure a plurality of sensing values for a plurality of pixels, wherein the panel degradation calculator includes a pixel degradation calculator configured to calculate a plurality of pixel degradation amounts for the plurality of pixels based on the plurality of sensing values.

[0012] The panel degradation amount can be equal to the maximum pixel degradation amount among a plurality of pixel degradation amounts.

[0013] The controller may further include: a degradation compensator configured to convert input image data into output image data based on a plurality of pixel degradation amounts.

[0014] The gain can be configured to remain constant regardless of the driving time of the display panel.

[0015] The gain can be configured to decrease as the driving time of the display panel increases.

[0016] The gain can be greater than 1.

[0017] The power current can be the sum of the driving currents of the plurality of light-emitting elements flowing through the plurality of pixels.

[0018] The maximum power current can correspond to the maximum brightness of the image displayed by the display panel.

[0019] A method for driving a display device according to an embodiment may include: calculating a panel degradation amount of a display panel including a plurality of pixels; calculating a maximum power current of the display panel based on the panel degradation amount; calculating a reference current by multiplying the maximum power current by a gain; and reducing the voltage of the display panel when the power current of the display panel is greater than the reference current.

[0020] Calculating the panel degradation amount may include: calculating a plurality of lifetimes of the plurality of blocks by accumulating a plurality of stresses of the plurality of blocks each including at least one of the plurality of pixels; and calculating a plurality of block degradation amounts of the plurality of blocks based on the lifetimes of the plurality of blocks.

[0021] The panel degradation amount can be equal to the maximum block degradation amount among a plurality of block degradation amounts.

[0022] Calculating the panel degradation amount may include: measuring sensing values for a plurality of pixels and calculating a plurality of pixel degradation amounts for the plurality of pixels based on the sensing values.

[0023] The panel degradation amount may be equal to the maximum pixel degradation amount among a plurality of pixel degradation amounts.

[0024] The method may further include: keeping the gain constant regardless of the driving time of the display panel.

[0025] The method may further include: decreasing the gain as the driving time of the display panel increases.

[0026] The gain may be greater than 1.

[0027] In the display device and the method of driving the display device according to the embodiments, the reference current may be calculated by multiplying the maximum power current calculated based on the panel degradation amount of the display panel by the gain, and when the power current of the display panel is greater than the reference current, the high-power voltage of the display panel may be reduced, so that the high-power voltage can be controlled in consideration of the degradation compensation of the display panel, and the frequent reduction of the high-power voltage can be reduced or prevented. In addition, the gain may decrease as the driving time of the display panel increases, so that an increase in power consumption of the display device can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram showing a display device according to one or more embodiments.

[0030] Figure 2 is a diagram showing Figure 1 an example of a pixel included in the display device.

[0031] Figure 3 is a view for describing the control of the high-power voltage according to the increase and decrease of the power current.

[0032] Figure 4 is a view for describing the reference current according to a comparative example.

[0033] Figure 5 is a diagram showing Figure 1 an example of a controller included in the display device.

[0034] Figure 6 is a diagram showing Figure 1 an example of a display panel included in the display device.

[0035] Figure 7 is a view showing a reference current according to one or more embodiments.

[0036] Figure 8 is a view showing a reference current according to one or more embodiments.

[0037] Figure 9 is a block diagram showing an example of a controller included in a display device Figure 1 shown in

[0038] Figure 10 is a flowchart showing a method of driving a display device according to one or more embodiments.

[0039] Figure 11 is a flowchart showing an example of the calculation of the amount of panel degradation included in the method of driving a display device Figure 10 shown in

[0040] Figure 12 is a flowchart showing an example of the calculation of the amount of panel degradation included in the method of driving a display device Figure 10 shown in

[0041] Figure 13 is a block diagram showing an electronic device according to one or more embodiments.

[0042] Figure 14 is a view showing an example in which Figure 13 the electronic device shown in Detailed Description of Embodiments

[0043] Aspects of some embodiments of the present disclosure and methods of implementing the embodiments can be more easily understood by referring to the detailed description of the embodiments and the drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant to the description of the embodiments, or unnecessary processes, elements, and techniques for those of ordinary skill in the art to fully understand aspects of the present disclosure can be omitted. Unless otherwise noted, the same reference numerals, characters, or combinations thereof represent the same elements throughout the drawings and the written description, and thus, repeated descriptions thereof can be omitted.

[0044] The described embodiments can have various modifications and can be embodied in different forms and should not be construed as limited to the embodiments shown herein. "Can," "may," or "may not" used in describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0045] In view of the entirety of the present disclosure, those of ordinary skill in the art will understand that, unless otherwise stated or implied, the present disclosure encompasses all modifications, equivalents, and substitutions within the spirit and scope of the present disclosure. Each of the features of the embodiments of the present disclosure can be combined in part or in whole with each other, and various interlocks and operations can be performed technically, and each embodiment can be implemented independently of each other or can be implemented in association with each other.

[0046] It will be understood that when an element, layer, region, or component is referred to as being "formed on", "on", "connected to", or "(operatively or communicatively) coupled to" another element, layer, region, or component, the one element, layer, region, or component can be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or can be indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there can be one or more intervening elements, layers, regions, or components. Additionally, this can be collectively referred to as direct coupling or connection or indirect coupling or connection and integrally coupled or connected or non-integrally coupled or connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the one layer, region, or component can be directly electrically connected or coupled to the other layer, region, or component, or there can be one or more intervening layers, regions, or components. One or more intervening components can include switches, resistors, and / or capacitors, etc. In the description of the embodiments, unless explicitly described as a direct connection, the expression of connection means an electrical connection, and "direct connection / direct coupling" or "directly on..." means that one component is directly connected or coupled to another component, or on another component, without an intervening component.

[0047] For the purposes of the present disclosure, when expressions such as “at least one of...”, “any one of...”, or “one or more of...” appear after a list of elements, they modify the entire list of elements and not individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one of the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or both A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any combination and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or both A and B. Similarly, when expressions such as “at least one of...”, “a plurality of...”, “one of...”, and other prepositional phrases appear before / after a list of elements, they modify the entire list of elements and not individual elements in the list. Unless otherwise specified, when stating “C to D”, this means C or more (greater) and D or less (smaller).

[0048] It will be understood that although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority and are only used to distinguish one element, member, component, region, area, layer, section, or part from another element, member, component, region, area, layer, section, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first section described below may be referred to as the second element, second component, second region, second layer, or second section. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first”, “second”, etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first”, “second”, etc. may respectively represent “first category (or first group)”, “second category (or second group)”, etc.

[0049] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms, and the plural forms are also intended to include the singular form. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes", and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0050] When one or more embodiments can be implemented differently, a particular process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0051] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than degree terms and are intended to account for the inherent deviation of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of ±5% of the corresponding value. As used herein, taking into account the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" includes the stated value and represents an acceptable deviation from the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. In addition, when "may" is used to describe an embodiment of the present disclosure, it refers to "one or more embodiments of the present disclosure".

[0052] In some embodiments, well-known structures and devices may be described in the drawings in relation to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from those of the dedicated hardware. Additionally, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically divided into two or more separate interacting blocks, units, and / or modules. Additionally, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0054] Hereinafter, a display device and a method of driving the display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram showing a display device 100 according to one or more embodiments. Figure 2 is shown Figure 1 an example of a pixel PX included in the display device 100. Figure 3 is a view for describing the control of a high-power voltage ELVDD according to an increase and decrease in an electric current IDD. Figure 4 is a view for describing a reference current IREF according to a comparative example.

[0056] Referring to Figure 1, the display device 100 may include a display panel 110, a data driver 120, a scan driver 130, a power management circuit 140, and a controller 160. In one or more embodiments, the display device 100 may further include a sensing circuit 150.

[0057] The display panel 110 may include a plurality of pixels PX, a plurality of data lines DL, a plurality of first scan lines, a plurality of second scan lines, and a plurality of sensing lines SL. The pixel PX may be connected to the data line DL, the first scan line, the second scan line, and the sensing line SL. In one or more embodiments, each of the pixels PX may include a light-emitting element LED (refer to Figure 2 ), and the display panel 110 may be a light-emitting display panel.

[0058] In one or more embodiments, as Figure 2 shown, each of the pixels PX may include a first transistor T1, a second transistor T2, a third transistor T3, a capacitor CST, and a light-emitting element LED.

[0059] The capacitor CST may store the data voltage VDAT transmitted from the data line DL by the second transistor T2. The capacitor CST may be referred to as a storage capacitor for storing the data voltage VDAT, but the present disclosure is not limited thereto. In one or more embodiments, the capacitor CST may include a first electrode connected to a first node NG and a second electrode connected to a second node NS.

[0060] The first transistor T1 may generate a driving current IEL based on the data voltage VDAT stored in the capacitor CST. The first transistor T1 may be referred to as a driving transistor for generating the driving current IEL, but the present disclosure is not limited thereto. In one or more embodiments, the first transistor T1 may include a gate connected to the first node NG, a drain for receiving a high-power voltage ELVDD, and a source connected to the second node NS.

[0061] The second transistor T2 may transmit the data voltage VDAT to the first node NG in response to a first scan signal SC. The second transistor T2 may be referred to as a scan transistor, but the present disclosure is not limited thereto. In one or more embodiments, the second transistor T2 may include a gate for receiving the first scan signal SC, a drain connected to the data line DL, and a source connected to the first node NG.

[0062] The third transistor T3 may connect the sensing line SL to the second node NS in response to the second scan signal SS. While the switch SW of the sensing circuit 150 connects the sensing line SL to the power management circuit 140, the power management circuit 140 may apply an initialization voltage VINT to the sensing line SL, and the third transistor T3 may transfer the initialization voltage VINT of the sensing line SL to the second node NS in response to the second scan signal SS. In addition, while the switch SW of the sensing circuit 150 connects the sensing line SL to the analog-to-digital converter ADC of the sensing circuit 150, the third transistor T3 may connect the sensing line SL to the second node NS in response to the second scan signal SS, and the sensing circuit 150 may sense the characteristics of the pixel PX through the sensing line SL. In one or more embodiments, the third transistor T3 may include a gate for receiving the second scan signal SS, a drain connected to the second node NS, and a source connected to the sensing line SL.

[0063] In one or more embodiments, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented as an N-type transistor (e.g., an NMOS transistor), but the present disclosure is not limited thereto. In one or more other embodiments, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented as a P-type transistor (e.g., a PMOS transistor). In one or more embodiments, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented as an oxide semiconductor transistor, but the present disclosure is not limited thereto. In one or more other embodiments, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented as a polysilicon transistor.

[0064] In one or more embodiments, the pixel PX may include three transistors and one capacitor, but the present disclosure is not limited thereto. In one or more other embodiments, the pixel PX may include two or four transistors and / or two or more capacitors.

[0065] The light-emitting element LED may emit light in response to a driving current IEL flowing from the line transmitting the high power voltage ELVDD to the line transmitting the low power voltage ELVSS. In one or more embodiments, the light-emitting element LED may include an anode connected to the second node NS and a cathode for receiving the low power voltage ELVSS. In one or more embodiments, the light-emitting element LED may be an organic light-emitting diode (OLED). In one or more other embodiments, the light-emitting element LED may be a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, or an inorganic light-emitting diode, etc.

[0066] Also refer to Figure 1, the data driver 120 may generate a data voltage VDAT based on the data control signal DCTRL and the output image data ODAT received from the controller 160, and may provide the data voltage VDAT to the pixel PX through the data line DL. In one or more embodiments, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, a load signal, etc. In one or more embodiments, the output image data ODAT may include gray level values corresponding to the pixel PX.

[0067] The scan driver 130 may generate a first scan signal SC and a second scan signal SS based on the scan control signal SCTRL received from the controller 160, and may sequentially provide the first scan signal SC and the second scan signal SS to the pixel PX in a line-by-line manner through the first scan line and the second scan line. In one or more embodiments, the scan control signal SCTRL may include a first scan start signal and a first scan clock signal for generating the first scan signal SC, and may further include a second scan start signal and a second scan clock signal for generating the second scan signal SS. In one or more embodiments, the first scan signal SC may be referred to as a scan signal, and the second scan signal SS may be referred to as a sense signal.

[0068] The power management circuit 140 may generate an initialization voltage VINT, a high power voltage ELVDD, and a low power voltage ELVSS based on the power management signal PCTRL received from the controller 160, and may provide the initialization voltage VINT, the high power voltage ELVDD, and the low power voltage ELVSS to the display panel 110. The power management circuit 140 may provide the high power voltage ELVDD to the display panel 110 through the power voltage line PL. A power current IDD may flow through the power voltage line PL, and the power current IDD may be the sum of the drive currents IEL of the light emitting elements LED included in the pixels PX in the display panel 110.

[0069] The sensing circuit 150 may sense the characteristics of the pixel PX through the sensing line SL. In one or more embodiments, the sensing circuit 150 may include a switch SW that selectively connects the sensing line SL to the power management circuit 140 or the analog-to-digital converter ADC, and the sensing circuit 150 may further include an analog-to-digital converter ADC that converts an analog signal (sensing voltage or sensing current) into a digital signal (sensing value). The switch SW may connect the sensing line SL to the power management circuit 140 while not performing a sensing operation, and may connect the sensing line SL to the analog-to-digital converter ADC while performing a sensing operation. The analog-to-digital converter ADC may convert the sensing voltage or sensing current received from the pixel PX through the sensing line SL into a sensing value, and the sensing circuit 150 may provide the sensing value representing the characteristics of the pixel PX to the controller 160.

[0070] The controller 160 (e.g., timing controller (TCON)) may control the data driver 120, the scan driver 130, and the power management circuit 140. The controller 160 may be provided with input image data IDAT and a control signal CTRL from a host processor (e.g., graphics processing unit (GPU), application processor (AP), or graphics card). In one or more embodiments, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, etc. In one or more embodiments, the input image data IDAT may include grayscale values corresponding to the pixel PX. The controller 160 may generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a power management signal PCTRL based on the input image data IDAT and the control signal CTRL. The controller 160 may control the operation of the data driver 120 by providing the output image data ODAT and the data control signal DCTRL to the data driver 120, may control the operation of the scan driver 130 by providing the scan control signal SCTRL to the scan driver 130, and may control the operation of the power management circuit 140 by providing the power management signal PCTRL to the power management circuit 140.

[0071] The controller 160 may convert the input image data IDAT into the output image data ODAT to compensate for the degradation of the pixel PX (or to compensate for the degradation of the display panel 110). As the driving time of the pixel PX increases, the light-emitting element LED included in the pixel PX may degrade. As the light-emitting element LED degrades, the driving current IEL flowing through the light-emitting element LED may decrease, and thus the brightness of the pixel PX (or the brightness of the display panel 110) may decrease. Accordingly, the controller 160 may convert the input image data IDAT into the output image data ODAT based on the degradation amount of the pixel PX (or the degradation amount of the display panel 110), where the degradation amount of the pixel PX (or the degradation amount of the display panel 110) may be calculated based on the lifespan of the pixel PX or the sensed value of the pixel PX. Accordingly, the driving current IEL flowing through the light-emitting element LED included in the pixel PX (or the power current IDD flowing through the display panel 110) may increase, and thus the unnecessary decrease in the brightness of the pixel PX (or the brightness of the display panel 110) may be reduced or prevented.

[0072] In one or more embodiments, as Figure 3 shown, when the power current IDD increases above the reference current IREF, also refer to Figure 1 , the power management circuit 140 may perform an operation of reducing the power current IDD by reducing the high-power voltage ELVDD (hereinafter referred to as the high-power voltage ELVDD reduction operation). When the power current IDD increases above the reference current IREF, an overcurrent may occur in the display panel 110, and damage such as image sticking may occur in the display panel 110 due to the overcurrent. When the high-power voltage ELVDD is reduced, the driving current IEL flowing through the light-emitting element LED may decrease, and the power current IDD, which is the sum of the driving currents IEL, may decrease. Accordingly, when the power current IDD increases above the reference current IREF, the high-power voltage ELVDD reduction operation may be performed, and thus the overcurrent in the display panel 110 may be reduced or prevented.

[0073] When the power current IDD drops below the reference current IREF within a certain period of time, the power management circuit 140 may raise the high-power voltage ELVDD to the original value that occurred before the high-power voltage ELVDD was reduced. Although the high-power voltage ELVDD is raised to the original value, when the cause of the increase in the power current IDD disappears, the power current IDD may drop to the original value before the power current IDD increased.

[0074] In a comparative example according to the prior art, as Figure 4As shown, the reference current IREF can be determined based on the maximum power current IDD_M of the display panel 110 at the initial driving time of the display panel 110. For example, the reference current IREF can be determined as a value obtained by multiplying the maximum power current IDD_M of the display panel 110 at the initial driving time of the display panel 110 by a constant value (e.g., 1.3). The maximum power current IDD_M of the display panel 110 can be the power current IDD corresponding to the maximum brightness of the image displayed by the display panel 110. In one or more embodiments, when the display panel 110 displays an image in which a white box is located on a black background, the maximum power current IDD_M can flow through the power voltage line PL. In one or more other embodiments, when the display panel 110 displays a full-white image, the maximum power current IDD_M can flow through the power voltage line PL. In a comparative example according to the prior art, the reference current IREF can be determined based on the maximum power current IDD_M of the display panel 110 at the initial driving time of the display panel 110, such that the reference current IREF can be constant and independent of the driving time of the display panel 110.

[0075] As described above, the controller 160 can convert the input image data IDAT into the output image data ODAT to compensate for the deterioration of the pixel PX. Therefore, the driving current IEL flowing through the light-emitting element LED included in the pixel PX can increase as the driving time of the display panel 110 increases, and the power current IDD of the display panel 110, which is the sum of the driving currents IEL, can increase. Therefore, as the driving time of the display panel 110 increases, the power current IDD (or the maximum power current IDD_M) of the display panel 110 can increase.

[0076] As Figure 4As shown, when the maximum power current IDD_M of the display panel 110 becomes greater than the reference current IREF as the driving time of the display panel 110 increases, although there is no overcurrent flowing in the display panel 110, the situation where the power current IDD of the display panel 110 is greater than the reference current IREF may often occur. When the power current IDD of the display panel 110 is greater than the reference current IREF, the power management circuit 140 may determine that an overcurrent is flowing in the display panel 110 and may perform a high-power voltage ELVDD reduction operation. Therefore, although there is no overcurrent flowing in the display panel 110, the power current IDD of the display panel 110 may decrease, which may reduce the brightness of the display panel 110 and the display quality of the display panel 110 may deteriorate. In other words, in the comparative example according to the prior art, since the reference current IREF at the initial driving time of the display panel 110 remains constant without considering the increase in the power current IDD for compensating for the deterioration of the pixels PX (or for compensating for the deterioration of the display panel 110), although there is no overcurrent flowing in the display panel 110, as the driving time of the display panel 110 increases, the high-power voltage ELVDD reduction operation may be frequently performed.

[0077] Figure 5 is a diagram showing Figure 1 an example of the controller 200 included in the display device 100. Figure 5 The controller 200 may correspond to Figure 1 the controller 160. Figure 6 is a diagram showing Figure 1 an example of the display panel 110 included in the display device 100. Figure 7 is a diagram showing the reference current IREF according to one or more embodiments. Figure 8 is a diagram showing the reference current IREF according to one or more embodiments.

[0078] Referring to Figure 1 and Figure 5 , the controller 200 may include a panel deterioration calculator 210, a maximum power current calculator 220, a reference current calculator 230, a high-power voltage controller 240, and a deterioration compensator 250.

[0079] The panel deterioration calculator 210 may calculate the panel deterioration amount DA_PN of the display panel 110. The panel deterioration amount DA_PN may indicate the degree of deterioration of the display panel 110. In one or more embodiments, the panel deterioration calculator 210 may include a block stress accumulator 211 and a block deterioration calculator 212.

[0080] The block stress accumulator 211 may accumulate the blocks BL (refer to Figure 6) Calculate the lifetime AG of the block BL based on the stress STR. As Figure 6 shown, the display panel 110 may include a plurality of blocks BL that divide the display panel 110, and each of the blocks BL may include at least one pixel PX. Also refer to Figure 1 and Figure 5 , in one or more embodiments, the stress STR of the block BL may correspond to the sum or average of the gray-level values of the input image data IDAT corresponding to the pixels PX included in the block BL. In one or more embodiments, the block stress accumulator 211 may calculate the lifetime AG of the block BL by accumulating the stress STR of the block BL for each frame period.

[0081] The block deterioration calculator 212 may calculate the block deterioration amount DA_BL of the block BL based on the lifetime AG of the block BL. The block deterioration amount DA_BL may indicate the degree of deterioration of the block BL. In one or more embodiments, the panel deterioration amount DA_PN of the display panel 110 may be equal to the maximum block deterioration amount among the block deterioration amounts DA_BL of the blocks BL. In other words, the panel deterioration amount DA_PN of the display panel 110 may be determined as the block deterioration amount DA_BL of the block BL having the maximum block deterioration amount DA_BL among the blocks BL.

[0082] The maximum power current calculator 220 may calculate the maximum power current IDD_M of the display panel 110 based on the panel deterioration amount DA_PN. As the driving time of the display panel 110 increases, the panel deterioration amount DA_PN may increase, so that the maximum power current IDD_M of the display panel 110 may increase.

[0083] The reference current calculator 230 may calculate the reference current IREF by multiplying the maximum power current IDD_M by the gain GN. The reference current IREF may be a reference for determining whether the power current IDD of the display panel 110 is an overcurrent.

[0084] In one or more embodiments, as Figure 7 shown, the gain GN may be constant and independent of the driving time of the display panel 110. For example, when the gain GN at the initial driving time of the display panel 110 is 1.3, the gain GN may be 1.3 and independent of the driving time of the display panel 110. In this case, the reference current IREF may be proportional to the maximum power current IDD_M.

[0085] In one or more embodiments, as Figure 8As shown, the gain GN may decrease as the driving time of the display panel 110 increases. For example, when the gain GN at the initial driving time of the display panel 110 is 1.3, after the initial driving time of the display panel 110, the gain GN may be less than 1.3. When considering increasing the reference current IREF due to an increase in the power current IDD caused by compensating for the deterioration of the display panel 110, in the case where the power current IDD increases, although the frequent execution of the high power voltage ELVDD reduction operation is reduced or prevented, since the high power voltage ELVDD reduction operation is not performed when the power current IDD is less than the reference current IREF, the power consumption of the display device may increase. As Figure 8 As shown, when the gain GN decreases as the driving time of the display panel 110 increases, an excessive increase in the reference current IREF can be reduced or prevented, and thus, an increase in the power consumption of the display device can be reduced or prevented.

[0086] In one or more embodiments, the gain GN may be greater than 1. Although the gain GN decreases as the driving time of the display panel 110 increases, since the gain GN is greater than 1, the reference current IREF may not be less than the maximum power current IDD_M, and thus, an excessive execution of the high power voltage ELVDD reduction operation can be reduced or prevented.

[0087] When the power current IDD is greater than the reference current IREF, the high power voltage controller 240 may determine that the power current IDD is an overcurrent, and may provide a high power voltage control signal ELVDD_CS for reducing the high power voltage ELVDD to the power management circuit 140. The power management circuit 140 may perform a high power voltage ELVDD reduction operation based on the high power voltage control signal ELVDD_CS to reduce the high power voltage ELVDD.

[0088] The deterioration compensator 250 may convert the input image data IDAT into output image data ODAT based on the block deterioration amount DA_BL. In one or more embodiments, the deterioration compensator 250 may calculate a block compensation value for the block BL based on the block deterioration amount DA_BL, and may calculate the gray level value of the output image data ODAT by adding the block compensation value to the gray level value of the input image data IDAT. In one or more embodiments, the deterioration compensator 250 may include a look-up table (LUT) in which block compensation values corresponding to the block deterioration amount DA_BL are stored. Thus, the deterioration of the pixel PX (or the deterioration of the display panel 110) can be compensated.

[0089] Figure 9 is a block diagram showing Figure 1 an example of the controller 200_1 included in the display device 100.

[0090] Reference Figure 1 and Figure 9 ,the controller 200_1 may include a panel degradation calculator 210_1, a maximum power current calculator 220, a reference current calculator 230, a high-power voltage controller 240, and a degradation compensator 250_1. The description of the components of the controller 200_1 that are substantially the same as or similar to the components of the controller 200 described with reference to Figure 9 will be omitted. The components of the controller 200_1 that are substantially the same as or similar to the components of the controller 200 described with reference to Figure 5 will not be described again.

[0091] In one or more embodiments, the panel degradation calculator 210_1 may include a pixel degradation calculator 213. The pixel degradation calculator 213 may calculate a pixel degradation amount DA_PX of the pixel PX based on a sensed value SSV for the pixel PX measured by the sensing circuit 150. The pixel degradation amount DA_PX may indicate the degree of degradation of the pixel PX. In one or more embodiments, the panel degradation amount DA_PN of the display panel 110 may be equal to the maximum pixel degradation amount among the pixel degradation amounts DA_PX of the pixels PX. In other words, the panel degradation amount DA_PN of the display panel 110 may be determined as the pixel degradation amount DA_PX of the pixel PX having the maximum pixel degradation amount DA_PX among the pixels PX.

[0092] The degradation compensator 250_1 may convert the input image data IDAT into output image data ODAT based on the pixel degradation amount DA_PX. In one or more embodiments, the degradation compensator 250_1 may calculate a pixel compensation value for the pixel PX based on the pixel degradation amount DA_PX, and may calculate the gray-level value of the output image data ODAT by adding the pixel compensation value to the gray-level value of the input image data IDAT. In one or more embodiments, the degradation compensator 250_1 may include a look-up table in which pixel compensation values corresponding to the pixel degradation amount DA_PX are stored. Accordingly, the degradation of the pixel PX (or the degradation of the display panel 110) may be compensated.

[0093] Figure 10 is a flowchart showing a method of driving the display device 100 according to one or more embodiments. Figure 11 is a flowchart showing Figure 10 an example of the calculation of the panel degradation amount DA_PN included in the method of driving the display device 100 in Figure 12 is a flowchart showing Figure 10 an example of the calculation of the panel degradation amount DA_PN included in the method of driving the display device 100 in

[0094] Reference Figure 1 , Figure 5 , Figure 6 , Figure 9 andFigure 10 A method of driving a display device 100 may include: calculating a panel degradation amount DA_PN of a display panel 110 including a plurality of pixels PX (S110); calculating a maximum power current IDD_M of the display panel 110 based on the panel degradation amount DA_PN (S120); calculating a reference current IREF by multiplying the maximum power current IDD_M by a gain GN (S130); and reducing a high power voltage ELVDD of the display panel 110 when a power current IDD of the display panel 110 is greater than the reference current IREF (S140).

[0095] In one or more embodiments, as Figure 11 shown, calculating the panel degradation amount DA_PN (S110) may include calculating a lifetime of a block BL by accumulating a stress STR of the block BL (S111), and calculating a block degradation amount DA_BL of the block BL based on the lifetime AG of the block BL (S112). In one or more embodiments, the panel degradation amount DA_PN may be equal to a maximum block degradation amount among the block degradation amounts DA_BL.

[0096] In one or more embodiments, as Figure 12 shown, calculating the panel degradation amount DA_PN (S110) may include measuring a sensed value SSV for a pixel PX (S113), and calculating a pixel degradation amount DA_PX of the pixel PX based on the sensed value SSV (S114). In one or more embodiments, the panel degradation amount DA_PN may be equal to a maximum pixel degradation amount among the pixel degradation amounts DA_PX.

[0097] In one or more embodiments, as Figure 7 shown, the gain GN may be constant regardless of a driving time of the display panel 110. In this case, the reference current IREF may be proportional to the maximum power current IDD_M.

[0098] In one or more embodiments, as Figure 8 shown, the gain GN may decrease as the driving time of the display panel 110 increases. When the gain GN decreases as the driving time of the display panel 110 increases, an excessive increase in the reference current IREF may be reduced or prevented, and thus, an increase in power consumption of the display device may be reduced or prevented.

[0099] In one or more embodiments, the gain GN may be greater than 1. Although the gain GN decreases as the driving time of the display panel 110 increases, since the gain GN is greater than 1, the reference current IREF may not be less than the maximum power current IDD_M, and thus, an excessive execution of the high power voltage ELVDD reduction operation may be reduced or prevented.

[0100] Figure 13 is a block diagram showing an electronic device 1000 according to one or more embodiments. Figure 14 is a view showing an example in which Figure 13 the electronic device 1000 is implemented as a computer monitor.

[0101] Referring to Figure 13 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc., or communicating with other systems.

[0102] In one or more embodiments, as Figure 14 shown, the electronic device 1000 may be implemented as a computer monitor. However, the present disclosure is not limited thereto, and according to one or more other embodiments, the electronic device 1000 may be implemented as a television, a mobile phone, a video phone, a smart tablet, a tablet personal computer (PC), a car navigation, a laptop computer, or a head-mounted display, etc.

[0103] The processor 1010 may perform specific calculations or tasks. According to one or more embodiments, the processor 1010 may be a microprocessor or a central processing unit (CPU), etc. The processor 1010 may be connected to other components through an address bus, a control bus, a data bus, etc. According to one or more embodiments, the processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In one or more embodiments, the processor 1010 may provide input image data ( Figure 1 input image data IDAT of Figure 1 ) and a control signal (

[0104] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include: non-volatile memory devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM); and / or volatile memory devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), or mobile DRAM.

[0105] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a compact disc read only memory (CD-ROM), etc. The I / O device 1040 may include: an input device such as a keyboard, a keypad, a touchpad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1050 may supply power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components through a bus or other communication links. The display device 1060 may correspond to Figure 1 the display device 100.

[0106] In the display device 1060, a reference current may be calculated by multiplying a maximum power current calculated based on the panel degradation amount of the display panel by a gain, and when the power current of the display panel is greater than the reference current, the high power voltage of the display panel may be reduced, so that the high power voltage may be controlled in consideration of the degradation compensation of the display panel, and frequent reduction of the high power voltage may be reduced or prevented. In addition, the gain may decrease as the driving time of the display panel increases, so that an increase in power consumption of the display device 1060 may be reduced or prevented.

[0107] The display device according to an embodiment may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a smart watch, a portable multimedia player (PMP), a personal digital assistant (PDA), or a Moving Picture Experts Group Audio Layer 3 (MP3) player, etc.

[0108] Although the display device and the method for driving the display device according to an embodiment have been described with reference to the drawings, the illustrated embodiments are examples, and those of ordinary skill in the relevant technical field may make modifications and changes without departing from the technical spirit described in the appended claims, and functional equivalents thereof are included in the illustrated embodiments.

Claims

1. A display device, wherein, The display device includes: a display panel including a plurality of pixels; a power management circuit configured to supply a voltage to the display panel through a power voltage line, and the power management circuit is configured to reduce the voltage when a power current flowing through the power voltage line of the display panel is greater than a reference current; and a controller configured to control the power management circuit, and the controller includes: a panel degradation calculator configured to calculate a panel degradation amount of the display panel; a maximum power current calculator configured to calculate a maximum power current of the display panel based on the panel degradation amount; and a reference current calculator configured to calculate the reference current by multiplying the maximum power current by a gain.

2. The display device according to claim 1, wherein, The panel degradation calculator includes: a block stress accumulator configured to calculate a plurality of lifetimes of a plurality of blocks each including at least one pixel among the plurality of pixels by accumulating a plurality of stresses of the plurality of blocks; and a block degradation calculator configured to calculate a plurality of block degradation amounts of the plurality of blocks based on the plurality of lifetimes of the plurality of blocks.

3. The display device according to claim 2, wherein, The panel degradation amount is equal to a maximum block degradation amount among the plurality of block degradation amounts.

4. The display device according to claim 1, wherein, The display device further includes: a sensing circuit configured to measure a plurality of sensing values for the plurality of pixels, wherein the panel degradation calculator includes a pixel degradation calculator configured to calculate a plurality of pixel degradation amounts of the plurality of pixels based on the plurality of sensing values.

5. The display device according to claim 4, wherein, The panel degradation amount is equal to a maximum pixel degradation amount among the plurality of pixel degradation amounts.

6. The display device according to claim 1, wherein, The gain is configured to remain constant regardless of a driving time of the display panel.

7. The display device according to claim 1, wherein, The gain is configured to decrease as the driving time of the display panel increases.

8. A method for driving a display device, wherein, The method includes: calculating a panel degradation amount of a display panel including a plurality of pixels; calculating a maximum power current of the display panel based on the panel degradation amount; calculating a reference current by multiplying the maximum power current by a gain; and reducing a voltage of the display panel when a power current of the display panel is greater than the reference current.

9. The method according to claim 8, wherein Calculating the panel degradation amount includes: calculating a plurality of lifetimes of a plurality of blocks each including at least one pixel among the plurality of pixels by accumulating a plurality of stresses of the plurality of blocks; and calculating a plurality of block degradation amounts of the plurality of blocks based on the plurality of lifetimes of the plurality of blocks.

10. The method according to claim 9, wherein, The panel degradation amount is equal to a maximum block degradation amount among the plurality of block degradation amounts.

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