Gate driving device and display panel

Abstract

The invention provides a gate driving device and a display panel, and belongs to the technical field of display driving, and the gate driving device comprises a first gate driving unit and a second gate driving unit. Wherein the first gate driving unit is used for outputting a first scanning signal line by line according to a first initial signal and stopping outputting the first scanning signal according to an invalid signal. And the second gate driving unit is connected with the first gate driving unit and is used for outputting a second scanning signal line by line according to the first scanning signal and outputting a third scanning signal line by line according to the second initial signal. The first gate driving unit and the second gate driving unit respectively output a first scanning signal and a second scanning signal to realize full-screen display, and the first gate driving unit stops outputting the first scanning signal and the second gate driving unit outputs a third scanning signal to realize high-brush-rate display. Therefore, the display panel not only can meet the display requirement of a larger visual field, but also can meet the display requirement of a high-frequency refresh rate.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and particularly to a gate driving device and a display panel. Background Art

[0002] With the continuous development of electronic device technology, users' requirements for display screens are increasing day by day. As new screen forms, rollable screens and foldable screens can achieve large-size displays in a limited space, meeting users' display needs for a larger viewing field. Additionally, in some usage scenarios, such as gaming or animation scenarios, the requirement for high refresh rates also needs to be considered.

[0003] However, the larger the display screen area and the higher the refresh rate, the more energy is generally required. When the display screen is in a high-frequency refresh state, each pixel needs to be charged and refreshed at a faster speed, and the battery needs to provide a large amount of electrical energy in a short time, which easily causes the battery output voltage to be unstable, resulting in insufficient pixel charging and abnormal display screen images.

[0004] Therefore, how to achieve a large-area display screen that can both meet the display needs for a larger viewing field and consider the requirement for a high refresh rate is a technical problem that those skilled in the art have been committed to researching. Summary of the Invention

[0005] In view of the deficiencies in the prior art, this application provides a gate driving device and a display panel.

[0006] In a first aspect, a gate driving device provided by this application includes: A first gate driving unit, configured to output a first scan signal row by row according to a first start signal, and stop outputting the first scan signal according to an invalid signal; A second gate driving unit, connected to the first gate driving unit, configured to output a second scan signal row by row according to the first scan signal, and output a third scan signal row by row according to a second start signal; Wherein, the scan frequency of the first scan signal is the same as that of the second scan signal, and the scan frequency of the third scan signal is different from that of the second scan signal.

[0007] Optionally, the first gate driving unit includes a first control circuit and a plurality of cascaded first gate driving circuits; The first control circuit is connected to a first control signal, a second control signal, the first start signal, and the invalid signal, and is configured to: Output the first start signal to the first one of the first gate driving circuits according to the first control signal, so that each of the first gate driving circuits outputs the first scan signal row by row; and Output the invalid signal to the first one of the first gate driving circuits according to the second control signal, so that each of the first gate driving circuits stops outputting the first scan signal; Wherein, the first control circuit includes a first transistor and a second transistor; The first transistor includes a control electrode connected to the first control signal, a first electrode connected to the first start signal, and a second electrode connected to the first one of the first gate driving circuits; The second transistor includes a control electrode connected to the second control signal, a first electrode connected to the invalid signal, and a second electrode connected to the first one of the first gate driving circuits.

[0008] Optionally, the second gate driving unit includes a second control circuit and a plurality of cascaded second gate driving circuits; The second control circuit is connected to the last one of the first gate driving circuits and receives the first control signal, the second control signal, and the second start signal, and is configured to: Output the first scan signal output by the last one of the first gate driving circuits to the first one of the second gate driving circuits according to the first control signal, so that each of the second gate driving circuits outputs the second scan signal row by row; and Output the second start signal to the first one of the second gate driving circuits according to the second control signal, so that each of the second gate driving circuits outputs the third scan signal row by row; Wherein, the second control circuit includes a third transistor and a fourth transistor; The third transistor includes a control electrode connected to the first control signal, a first electrode connected to the last one of the first gate driving circuits, and a second electrode connected to the first one of the second gate driving circuits; The fourth transistor includes a control electrode connected to the second control signal, a first electrode connected to the second start signal, and a second electrode connected to the first one of the second gate driving circuits.

[0009] Optionally, the second control circuit further includes a fifth transistor; The fifth transistor includes a control electrode connected to a third control signal, a first electrode connected to the invalid signal, and a second electrode connected to the first one of the second gate driving circuits, and is configured to output the invalid signal to the first one of the second gate driving circuits according to the third control signal, so that each of the second gate driving circuits stops outputting the second scan signal or the third scan signal.

[0010] Optionally, it further includes a third gate driving unit, connected to the second gate driving unit, for outputting a fourth scanning signal row by row according to the second scanning signal and stopping outputting the fourth scanning signal according to the invalid signal.

[0011] Optionally, the third gate driving unit includes a third control circuit and several cascaded third gate driving circuits; The third control circuit is connected to the last second gate driving circuit and receives the first control signal, the second control signal, and the invalid signal, and is configured to: Output the second scanning signal output by the last second gate driving circuit to the first third gate driving circuit according to the first control signal, so that each third gate driving circuit outputs the fourth scanning signal row by row; and Output the invalid signal to the first third gate driving circuit according to the second control signal, so that each third gate driving circuit stops outputting the fourth scanning signal; Wherein, the third control circuit includes a sixth transistor and a seventh transistor; The sixth transistor includes a control electrode connected to the first control signal, a first electrode connected to the last second gate driving circuit, and a second electrode connected to the first third gate driving circuit; The seventh transistor includes a control electrode connected to the second control signal, a first electrode connected to the invalid signal, and a second electrode connected to the first third gate driving circuit.

[0012] Optionally, the scanning frequency of the first scanning signal and the scanning frequency of the second scanning signal are a first frequency, and the scanning frequency of the third scanning signal is a second frequency, and the second frequency is greater than the first frequency.

[0013] Optionally, in the first mode, the first gate driving unit outputs the first scanning signal row by row according to the first start signal, and the second gate driving unit outputs the second scanning signal row by row according to the first scanning signal, so that the display areas corresponding to the first gate driving unit and the second gate driving unit are refreshed at the first frequency; In the second mode, the first gate driving unit stops outputting the first scanning signal according to the invalid signal, and the second gate driving unit outputs the third scanning signal row by row according to the second start signal, so that the display area corresponding to the second gate driving unit is refreshed at the second frequency.

[0014] Optionally, each stage of the first gate driving circuit and each stage of the second gate driving circuit respectively include a light emitting control circuit, a driving circuit, and a reset circuit; The first start signal includes a first driving start signal, a first light-emitting start signal, and a first reset start signal that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the first gate driving circuit; The second start signal includes a second driving start signal, a second light-emitting start signal, and a second reset start signal that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the second gate driving circuit; In the first mode, the first driving start signal, the first light-emitting start signal, and the first reset start signal are sequentially in an active level state, and the second driving start signal, the second light-emitting start signal, and the second reset start signal are in an inactive level state; In the second mode, the first driving start signal, the first light-emitting start signal, and the first reset start signal are in an inactive level state, and the second driving start signal, the second light-emitting start signal, and the second reset start signal are sequentially in an active level state.

[0015] According to a second aspect of the present application, a display panel is provided, including the above-mentioned gate driving device.

[0016] In summary, in the present application, the first gate driving unit outputs a first scan signal according to the first start signal, and the second gate driving unit is cascaded with the first gate driving unit, so that the second gate driving unit synchronously outputs a second scan signal at the same scan frequency after receiving the first scan signal, so that all display areas corresponding to the first gate driving unit and the second gate driving unit are displayed at the scan frequency of the first scan signal to achieve a large field of view display for the entire screen. When the first gate driving unit receives an invalid signal, it stops outputting the first scan signal, so that a partial display area corresponding to the first gate driving unit stops working. At this time, the second gate driving unit can independently output a third scan signal according to the second start signal, so that a partial display area corresponding to the second gate driving unit is displayed at the scan frequency of the third scan signal, and a partial display area can be displayed at a higher refresh rate. In this way, the display panel can not only meet the display requirements of a larger field of view but also take into account the display requirements of a high refresh rate. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0018] Figure 1Schematic diagram of the application scenario of the gate driving device in an embodiment of the present application; Figure 2 Schematic diagram of the gate driving device in an embodiment of the present application; Figure 3 Schematic diagram of the first gate driving unit and the second gate driving unit in an embodiment of the present application; Figure 4 (a) Timing waveform diagram of the first gate driving unit and the second gate driving unit in an embodiment of the present application; Figure 4 (b) Timing waveform diagram of the first gate driving unit and the second gate driving unit in another embodiment of the present application; Figure 5 Schematic diagram of the second gate driving unit in an embodiment of the present application; Figure 6 Schematic diagram of the third gate driving unit in an embodiment of the present application; Figure 7 Circuit connection diagram of the third gate driving unit in an embodiment of the present application.

[0019] Explanation of reference numerals: 1, first gate driving unit; 11, first control circuit; 2, second gate driving unit; 21, second control circuit; 3, third gate driving unit; 31, third control circuit. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0021] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined. In the present application, the term "exemplary" is used to mean "serving as an example, illustration, or explanation". Any embodiment described as "exemplary" in the present application is not necessarily to be construed as more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the present application. In the following description, details are set forth for purposes of explanation. It should be understood that those of ordinary skill in the art can recognize that the present application can be implemented without the use of these specific details. In other instances, well-known structures and processes are not described in detail to avoid unnecessary details from obscuring the description of the present application. Therefore, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed in the present application.

[0022] Referring to Figure 1 as shown, Figure 1 is a schematic diagram of a display panel in an embodiment of the present application. The display panel includes a display area AA and a non-display area NA adjacent to the display area AA, and the non-display area NA surrounds the display area AA. The display area AA is an area within the display panel for performing a display function, and a plurality of display units for realizing its display function are provided therein. The non-display area NA may be a border area of the display panel, and functional components for assisting the display units in the display area AA to perform display may be provided therein.

[0023] Among them, a number of pixel circuits are arranged in an array in the display area AA. In the non-display area NA, related devices for driving the display panel to perform display, such as a timing controller 100 (Timing Controller, TCON), a source driver 200 (Source Driver), and a gate driver 300 (Gate Driver), may be provided.

[0024] Among them, in this embodiment, the display panel is taken as an organic light-emitting diode (OLED) display panel as an example. The timing controller 100 receives image data and control signals, and performs preprocessing such as format conversion and data sorting on the image data to obtain data signals. At the same time, the timing controller 100 also generates control signals and clock signals. Then, the data signals and control signals are respectively sent to the source driver 200 and the gate driver 300. After receiving the data signal and control signal from the timing controller 100, the source driver 200 stores the data signal (Data Signal) in an internal register.

[0025] The gate driver 300 may include a driving circuit SCAN, a reset circuit RST, and a light-emitting control circuit EM that are cascaded. The driving circuit SCAN is responsible for generating scan signals (GateSignal) row by row according to the control signals output by the timing controller, and transmitting the scan signals to the thin-film transistors of each row of pixel circuits through scan lines, so that the data signals provided by the source driver 200 are written into the pixel circuits. The reset circuit RST applies a reset pulse (Reset Pulse) to the pixel circuits before each frame display or during the row scan interval to clear the residual charges in the pixel circuits and avoid afterimages or uneven brightness caused by charge accumulation. After the data writing and reset are completed, the light-emitting control circuit EM outputs an emission enable signal (Emission EnableSignal) to precisely control the light-emitting timing and duration of the organic light-emitting diode (OLED).

[0026] As an example, the driving circuit SCAN, the reset circuit RST, and the light-emitting control circuit EM can be single-sided driving or double-sided driving, and the number of the driving circuit SCAN, the reset circuit RST, and the light-emitting control circuit EM is not specifically limited. At the same time, according to different pixel circuit architectures, the gate driver 300 may also include other cascaded functional circuits, such as a compensation circuit for compensating the conduction threshold of the thin-film transistors in the pixel circuits, etc., which are not specifically limited herein.

[0027] It should be noted that Figure 1 The application scenario of the shown gate driver is only an example. The application scenario of the gate driver described in the embodiments of the present application is to more clearly illustrate the technical solutions of the embodiments of the present application, and does not constitute a limitation on the technical solutions provided by the embodiments of the present application.

[0028] Based on the above application scenario of the gate driver, embodiments of the gate driver are proposed in the present application.

[0029] In the first aspect, as Figure 2As shown, in one embodiment, the present application provides a gate driving device, which includes a first gate driving unit 1 and a second gate driving unit 2. Among them, the first gate driving unit 1 is used to output a first scanning signal row by row according to a first start signal, and stop outputting the first scanning signal according to an invalid signal. The second gate driving unit 2 is connected to the first gate driving unit 1, and is used to output a second scanning signal row by row according to the first scanning signal, and output a third scanning signal row by row according to a second start signal.

[0030] Among them, V1 represents the first scanning signal, V2 represents the second scanning signal, V3 represents the third scanning signal, and VN represents the invalid signal. The first scanning signal, the second scanning signal, and the third scanning signal may include at least one of a row scanning signal, a light emission control signal, and a reset signal. The scanning frequency of the first scanning signal is the same as that of the second scanning signal, and the scanning frequency of the third scanning signal is different from that of the second scanning signal. For example, to achieve a higher refresh rate, the scanning frequencies of the first scanning signal and the second scanning signal are a first frequency, and the scanning frequency of the third scanning signal is a second frequency, and the second frequency is greater than the first frequency. As an example, the higher the scanning frequency, the higher the refresh rate for controlling the display of the display panel. The refresh rate refers to the number of times the display panel updates the displayed image per second. The higher the refresh rate, the smoother the picture of the display panel. For example, a refresh rate of 120Hz means that the display panel can completely display 120 pictures per second, and a refresh rate of 180Hz means that the display panel can display 180 pictures per second. The scanning frequency refers to the frequency of each scanning signal (including the first scanning signal, the second scanning signal, and the third scanning signal) output to each row of pixel circuits per second. If the display panel needs to display N (N is a positive integer) pictures per second, then the corresponding scanning signals need to control each row of pixels to be refreshed N times per second. Therefore, the scanning frequency of each scanning signal is the same as the refresh rate of the display panel. For example, the first scanning signal and the second scanning signal can control the display panel to display at a refresh rate of 60HZ or 120HZ, then the corresponding scanning frequencies of the first scanning signal and the second scanning signal are 60HZ or 120HZ. The third scanning signal can control the display panel to display at a refresh rate of 180HZ or 240HZ, then the corresponding scanning frequency of the third scanning signal is 180HZ or 240HZ.

[0031] Among them, the first gate driving unit 1 and the second gate driving unit 2 correspond to different display areas in the display panel. For example, if the resolution of the display panel is 2560×1440 pixels, the total number of rows is 1440 rows. The first gate driving unit 1 can correspondingly drive 720 rows in the upper half of the display panel, and the second gate driving unit 2 can correspondingly drive the remaining 720 rows. Then the first scan signal and the second scan signal will be output on the entire display panel corresponding to the first gate driving unit 1 and the second gate driving unit 2, while the third scan signal is only output in a partial area of the display panel corresponding to the second gate driving unit 2.

[0032] As an example, in the usage scenarios of a rollable screen or a foldable screen, the first gate driving unit 1 and the second gate driving unit 2 can correspond to all the display areas in the rollable screen or the foldable screen. The second gate driving unit 2 can correspond to a partial display area when the rollable screen or the foldable screen is curled to a preset position or in a folded form. Thus, when the rollable screen or the foldable screen is in an unfolded state, all the display areas are displayed at the scanning frequencies of the first scan signal and the second scan signal to meet the display requirements for a larger viewing field; when the rollable screen or the foldable screen is curled to a preset position or in a folded form, it is displayed at the scanning frequency of the third scan signal in the partial display area corresponding to the second gate driving unit 2 to meet the display requirements for a higher refresh rate.

[0033] In the above embodiments, the first gate driving unit 1 outputs the first scan signal according to the first start signal, and the second gate driving unit 2 is cascaded with the first gate driving unit 1, so that the second gate driving unit 2 synchronously outputs the second scan signal at the same scanning frequency after receiving the first scan signal, so that all the display areas corresponding to the first gate driving unit 1 and the second gate driving unit 2 are displayed at the scanning frequency of the first scan signal to achieve a large viewing field display for the full screen. When the first gate driving unit 1 receives an invalid signal, it stops outputting the first scan signal, so that a partial display area corresponding to the first gate driving unit 1 stops working. At this time, the second gate driving can independently output the third scan signal according to the second start signal, so that the partial display area corresponding to the second gate driving unit 2 is displayed at the scanning frequency of the third scan signal, and a partial display area can be displayed at a higher refresh rate. In this way, the display panel can not only meet the display requirements for a larger viewing field, but also take into account the display requirements for a high-frequency refresh rate.

[0034] In some embodiments, in the first mode, the first gate driving unit outputs a first scan signal line by line according to a first start signal, and the second gate driving unit outputs a second scan signal line by line according to the first scan signal, so that the display areas corresponding to the first gate driving unit and the second gate driving unit are refreshed at a first frequency; in the second mode, the first gate driving unit stops outputting the first scan signal according to an invalid signal, and the second gate driving unit outputs a third scan signal line by line according to a second start signal, so that the display area corresponding to the second gate driving unit is refreshed at a second frequency.

[0035] Referring to Figure 3 , in some embodiments, the first gate driving unit 1 includes a first control circuit 11 and a plurality of cascaded first gate driving circuits. Among them, the first control circuit 11 is connected to a first control signal Control1, a second control signal Control2, a first start signal, and an invalid signal. Among them, the first control circuit 11 outputs the first start signal to the first first gate driving circuit according to the first control signal Control1, so that each first gate driving circuit outputs a first scan signal line by line. In addition, the first control circuit 11 can also output the invalid signal to the first first gate driving circuit according to the second control signal Control2, so that each first gate driving circuit stops outputting the first scan signal.

[0036] In some embodiments, the second gate driving unit 2 includes a second control circuit 21 and a plurality of cascaded second gate driving circuits. Among them, the second control circuit 21 is connected to the last first gate driving circuit and is connected to a first control signal Control1, a second control signal Control2, and a second start signal. Among them, the second control circuit 21 outputs the first scan signal output by the last first gate driving circuit to the first second gate driving circuit according to the first control signal Control1, so that each second gate driving circuit outputs a second scan signal line by line. In addition, the second control circuit 21 can also output the second start signal to the first second gate driving circuit according to the second control signal Control2, so that each second gate driving circuit outputs a second scan signal line by line.

[0037] As an example, the types of the first gate driving circuit and the second gate driving circuit can be a light emission control circuit, a driving circuit, and a reset circuit, to output a line scan signal, a light emission control signal, and a reset signal respectively, and the circuit types included in each stage of the gate driving circuit (the first gate driving circuit and the second gate driving circuit) are the same, and the same types of circuits included in different stages of the gate driving circuit are cascaded in sequence.

[0038] As an example, in combination with Figure 3, the first first-gate driving circuit includes a light-emitting control circuit EM11, a driving circuit SCAN11, and a reset circuit RST11. The second-stage first-gate driving circuit includes a light-emitting control circuit EM12, a driving circuit SCAN12, and a reset circuit RST12, and so on. The nth-stage first-gate driving circuit 12 includes a light-emitting control circuit EM1n, a driving circuit SCAN1n, and a reset circuit RST1n, where n is a positive integer. Moreover, the light-emitting control circuits EM11, EM12, ……, EM1n are cascaded in sequence, the driving circuits SCAN11, SCAN12, ……, SCAN1n are cascaded in sequence, and the reset circuits RST11, RST12, ……, RST1n are cascaded in sequence.

[0039] Similarly, the first second-gate driving circuit includes a light-emitting control circuit EM21, a driving circuit SCAN21, and a reset circuit RST21. The second-stage second-gate driving circuit includes a light-emitting control circuit EM22, a driving circuit SCAN22, and a reset circuit RST22, and so on. The nth-stage second-gate driving circuit includes a light-emitting control circuit EM2n, a driving circuit SCAN2n, and a reset circuit RST2n, where n is a positive integer. Moreover, the light-emitting control circuits EM21, EM22, ……, EM2n are cascaded in sequence, the driving circuits SCAN21, SCAN22, ……, SCAN2n are cascaded in sequence, and the reset circuits RST21, RST22, ……, RST2n are cascaded in sequence.

[0040] Among them, when the types of the first-gate driving circuit and the second-gate driving circuit are the light-emitting control circuit, the driving circuit, and the reset circuit, correspondingly, the first start signal includes a first light-emitting start signal STV11, a first driving start signal STV12, and a first reset start signal STV13. And the first light-emitting control circuit EM11 in the first gate driving unit 1 accesses the first light-emitting start signal STV11 through the first control circuit 11, the first driving circuit SCAN11 accesses the first driving start signal STV12 through the first control circuit 11, and the reset circuit RST11 accesses the first reset start signal STV13 through the first control circuit 11. Similarly, the second start signal includes a second light-emitting start signal STV21, a second driving start signal STV22, and a second reset start signal STV23; the first light-emitting control circuit EM21 in the second gate driving unit 2 accesses the second light-emitting start signal STV21 through the second control circuit 21, the first driving circuit SCAN21 accesses the second driving start signal STV22 through the second control circuit 21, and the reset circuit RST21 accesses the second reset start signal STV23 through the second control circuit 21.

[0041] As an example, the first control signal Control1 and the second control signal Control2 can be output by a timing controller according to the status signal of the display panel. In the usage scenarios of a rollable screen or a foldable screen, the status information is used to characterize the curling or unfolding state of the rollable screen of the display panel and the folding and unfolding states of the foldable screen.

[0042] For example, if the status signal characterizes that the display panel is in an unfolded state, the timing controller outputs the first control signal Control1 to control the first control circuit 11 to output the first start signal to the first gate driving circuit of the first row, so that each first gate driving circuit outputs the first scanning signal row by row. At the same time, the first control signal Control1 also controls, through the second control circuit 21, the conduction between the last first gate driving circuit 12 and the first second gate driving circuit 22, so that the second gate driving circuit outputs the second scanning signal according to the first scanning signal output by the last first gate driving circuit, thereby enabling the entire area of the display panel corresponding to the first gate driving unit 1 and the second gate driving unit 2 to display an image.

[0043] If the status signal characterizes that the display panel is curled to a preset position or in a folded state, the timing controller outputs the second control signal Control2, causing the first control circuit 11 to control each first gate driving circuit to stop outputting the first scanning signal. At the same time, the second control signal Control2 controls the second control circuit 21 to output the second start signal to the first second gate driving circuit, so that each second gate driving circuit outputs the second scanning signal row by row. At this time, some areas in the display panel corresponding to the second gate driving unit 2 can display an image at a higher refresh rate, while the area corresponding to the first gate driving unit 1 is curled or folded and does not display an image, reducing power consumption.

[0044] Refer to Figure 3 , in some embodiments, the first control circuit 11 includes a first transistor T1 and a second transistor T2. Among them, the first transistor T1 includes a control electrode connected to the first control signal Control1, a first electrode connected to the first start signal, and a second electrode connected to the first gate driving circuit of the first row. The second transistor T2 includes a control electrode connected to the second control signal Control2, a first electrode connected to an invalid signal, and a second electrode connected to the first gate driving circuit of the first row.

[0045] In some embodiments, the second control circuit 21 includes a third transistor T3 and a fourth transistor T4. Among them, the third transistor T3 includes a control electrode connected to the first control signal Control1, a first electrode connected to the last first gate driving circuit, and a second electrode connected to the first second gate driving circuit. The fourth transistor T4 includes a control electrode connected to the second control signal Control2, a first electrode connected to the second start signal, and a second electrode connected to the first second gate driving circuit.

[0046] As an example, if the first gate driving circuit and the second gate driving circuit are of P-type transistor architecture, the invalid signal can be a high-level signal VGH. If the first gate driving circuit and the second gate driving circuit are of N-type transistor architecture, the invalid signal can be a low-level signal VGL.

[0047] In some embodiments, each stage of the first gate driving circuit and each stage of the second gate driving circuit respectively include a light-emitting control circuit, a driving circuit, and a reset circuit; the first start signal includes a first driving start signal STV12, a first light-emitting start signal STV11, and a first reset start signal STV13 that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the first first gate driving circuit; the second start signal includes a second driving start signal STV22, a second light-emitting start signal STV21, and a second reset start signal STV23 that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the first second gate driving circuit.

[0048] As an example, in the first mode, the first driving start signal STV12, the first light-emitting start signal STV11, and the first reset start signal STV13 are in an effective level state in sequence, and the second driving start signal STV22, the second light-emitting start signal STV21, and the second reset start signal STV23 are in an invalid level state.

[0049] In the second mode, the first driving start signal STV12, the first light-emitting start signal STV11, and the first reset start signal STV13 are in an invalid level state, and the second driving start signal STV22, the second light-emitting start signal STV21, and the second reset start signal STV23 are in an effective level state in sequence.

[0050] Combined with Figure 4(a), taking the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 as P-type transistors as an example, when the first control signal Control1 is at a low level and the second control signal Control2 is at a high level, the first transistor T1 conducts and the second transistor T2 is turned off. At this time, the timing controller sequentially outputs the first reset start signal STV13 in the low level state, the first drive start signal STV12, and the first light emission start signal STV11 to the reset circuit RST11, the drive circuit SCAN11, and the light emission control circuit EM11 respectively, so as to sequentially control each reset circuit of the first gate drive unit 1 to output a reset signal to perform a reset operation on the pixel circuit, each drive circuit to output a row scan signal to control the pixel circuit to conduct to write a data signal, and each light emission control circuit to output a light emission control signal to control the pixel circuit to emit light according to the written data signal, thereby realizing that the first gate drive unit 1 controls the pixel circuit in the corresponding display area to start displaying an image. At the same time, the third transistor T3 conducts and the fourth transistor T4 is turned off, and the timing controller controls the second reset start signal STV23, the second drive start signal STV22, and the second light emission start signal STV21 to be in a high level state, so that the second gate drive unit 2 outputs a second scan signal according to the first scan signal output by the last-stage first gate drive circuit.

[0051] Combined with Figure 4 (b), when the first control signal Control1 is at a high level and the second control signal Control2 is at a low level, the first transistor T1 is turned off and the second transistor T2 conducts. The invalid signal is respectively output to the reset circuit RST11, the drive circuit SCAN11, and the light emission control circuit EM11 through the second transistor T2, so that the first gate drive unit 1 stops outputting the first scan signal. At the same time, the third transistor T3 is turned off and the fourth transistor T4 conducts. At this time, the timing controller sequentially outputs the second reset start signal STV23 in the low level state, the second drive start signal STV22, and the second light emission start signal STV21 to the reset circuit RST21, the drive circuit SCAN21, and the light emission control circuit EM21 respectively, so as to sequentially control each reset circuit of the second gate drive unit 2 to output a reset signal to perform a reset operation on the pixel circuit, each drive circuit to output a row scan signal to control the pixel circuit to conduct to write a data signal, and each light emission control circuit to output a light emission control signal to control the pixel circuit to emit light according to the written data signal, thereby realizing that the second drive gate unit controls the pixel circuit in the corresponding display area to start displaying an image.

[0052] Refer to Figure 5, in some embodiments, the second control circuit 21 further includes a fifth transistor T5. The fifth transistor T5 includes a control electrode connected to a third control signal Control3, a first electrode connected to an invalid signal, and a second electrode connected to the first second gate driving circuit, and is configured to output the invalid signal to the first second gate driving circuit according to the third control signal Control3, so that each second gate driving circuit stops outputting the second scanning signal or the third scanning signal.

[0053] As an example, the fifth transistor T5 may be a P-type transistor. When the third control signal Control3 is in a high level state, it can control the second gate driving unit 2 to be turned off alone, and at the same time control the first gate driving unit 1 to output the first scanning signal. In this way, the effect of separately displaying a picture in a partial area of the display panel corresponding to the first gate driving unit 1 can be achieved.

[0054] Refer to Figure 6 , in some embodiments, the gate driving device further includes a third gate driving unit 3, connected to the second gate driving unit 2, and configured to output a fourth scanning signal row by row according to the second scanning signal and stop outputting the fourth scanning signal according to the invalid signal.

[0055] Refer to Figure 6 , as an example, V4 represents the fourth scanning signal. The area of the display panel corresponding to the third gate driving unit 3 is different from the areas corresponding to the second gate driving unit 2 and the first gate driving unit 1, and the area of the display panel can be further expanded. The scanning frequency of the fourth scanning signal is the same as the scanning frequencies of the first scanning signal and the second scanning signal. When the display panel performs full-screen display, the first gate driving unit 1, the second gate driving unit 2, and the third gate driving unit 3 sequentially transmit and output the first scanning signal, the second scanning signal, and the fourth scanning signal. For example, in a scenario where a foldable screen supports folding twice (triple-fold) or a rollable screen curls from both ends respectively, full-screen display can be achieved when the foldable screen and the rollable screen are fully unfolded, while in the triple-fold state of the foldable screen or the state where both ends of the rollable screen curl respectively, the effect of only the partial display area corresponding to the second gate driving unit 2 being displayed separately can be achieved.

[0056] In the above embodiments, by setting the third gate driving unit 3 after the second gate driving unit 2, the area of the display panel can be further expanded, achieving a display effect with a larger view. And by using the invalid signal, the third gate driving unit 3 can be controlled to stop outputting the fourth scanning signal, so that a partial area of the display panel corresponding to the third gate driving unit 3 can be separately turned off without affecting the function of the second gate driving unit 2 to perform independent display at a high refresh rate.

[0057] Refer to Figure 7, as an example, the third gate driving unit 3 includes a third control circuit 31 and several cascaded third gate driving circuits. The third control circuit 31 is connected to the last second gate driving circuit and receives the first control signal Control1, the second control signal Control2, and an invalid signal. Among them, the third control circuit 31 outputs the second scan signal output by the last second gate driving circuit to the first third gate driving circuit according to the first control signal Control1, so that each third gate driving circuit outputs a fourth scan signal row by row. In addition, the third control circuit also outputs the invalid signal to the first third gate driving circuit according to the second control signal Control2, so that each third gate driving circuit stops outputting the fourth scan signal.

[0058] Among them, the third control circuit 31 includes a sixth transistor T6 and a seventh transistor T7. The sixth transistor T6 includes a control electrode connected to the first control signal Control1, a first electrode connected to the last second gate driving circuit, and a second electrode connected to the first third gate driving circuit. The seventh transistor T7 includes a control electrode connected to the second control signal Control2, a first electrode connected to the invalid signal, and a second electrode connected to the first third gate driving circuit.

[0059] , as an example, the types of the third gate driving circuits are the same as those of the first gate driving circuit and the second gate driving circuit, and can be a light emission control circuit, a driving circuit, and a reset circuit to output a row scan signal, a light emission control signal, and a reset signal respectively. Moreover, the circuit types included in each stage of the third gate driving circuit are the same, and the same types of circuits included in different stages of the gate driving circuits are cascaded in sequence. For example, the first third gate driving circuit includes a light emission control circuit EM31, a driving circuit SCAN31, and a reset circuit RST31. The second stage of the third gate driving circuit includes a light emission control circuit EM32, a driving circuit SCAN32, and a reset circuit RST32, and so on. The nth stage of the third gate driving circuit includes a light emission control circuit EM3n, a driving circuit SCAN3n, and a reset circuit RST3n, where n is a positive integer. And the light emission control circuits EM31, EM32,..., EM3n are cascaded in sequence, the driving circuits SCAN31, SCAN32,..., SCAN3n are cascaded in sequence, and the reset circuits RST31, RST32,..., RST3n are cascaded in sequence.

[0060] As an example, taking the sixth transistor T6 and the seventh transistor T7 as P-type transistors, when the first control signal Control1 is at a low level and the second control signal Control2 is at a high level, the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, so that the third gate driving unit 3 outputs a fourth scan signal according to the second scan signal output by the last-stage second gate driving circuit. When the first control signal Control1 is at a high level and the second control signal Control2 is at a low level, the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, and the invalid signal is respectively output to the reset circuit RST31, the driving circuit SCAN31, and the light-emitting control circuit EM31 through the seventh transistor T7, so that the third gate driving unit 3 stops outputting the fourth scan signal.

[0061] According to a second aspect of the present application, there is provided a display panel including the above-mentioned gate driving device.

[0062] In the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0063] The embodiments, implementation manners, and related technical features of the present application can be combined and replaced with each other without conflict.

[0064] The above are only preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A gate driving device, characterized in that, Including: A first gate driving unit, configured to output a first scan signal row by row according to a first start signal, and stop outputting the first scan signal according to an invalid signal; A second gate driving unit, connected to the first gate driving unit, configured to output a second scan signal row by row according to the first scan signal, and output a third scan signal row by row according to a second start signal; Wherein, a scan frequency of the first scan signal is the same as that of the second scan signal, and a scan frequency of the third scan signal is different from that of the second scan signal.

2. The gate driving device according to claim 1, characterized in that, The first gate driving unit includes a first control circuit and a plurality of cascaded first gate driving circuits; The first control circuit is connected to a first control signal, a second control signal, the first start signal, and the invalid signal, and is configured to: Output the first start signal to the first one of the first gate driving circuits according to the first control signal, so that each of the first gate driving circuits outputs the first scan signal row by row; and Output the invalid signal to the first one of the first gate driving circuits according to the second control signal, so that each of the first gate driving circuits stops outputting the first scan signal; Wherein, the first control circuit includes a first transistor and a second transistor; The first transistor includes a control electrode connected to the first control signal, a first electrode connected to the first start signal, and a second electrode connected to the first one of the first gate driving circuits; The second transistor includes a control electrode connected to the second control signal, a first electrode connected to the invalid signal, and a second electrode connected to the first one of the first gate driving circuits.

3. The gate driving device according to claim 2, wherein The second gate driving unit includes a second control circuit and a plurality of cascaded second gate driving circuits; The second control circuit is connected to the last one of the first gate driving circuits, and is connected to the first control signal, the second control signal, and the second start signal, and is configured to: Output the first scan signal output by the last one of the first gate driving circuits to the first one of the second gate driving circuits according to the first control signal, so that each of the second gate driving circuits outputs the second scan signal row by row; And Output the second start signal to the first one of the second gate driving circuits according to the second control signal, so that each of the second gate driving circuits outputs the third scan signal row by row; Wherein, the second control circuit includes a third transistor and a fourth transistor; The third transistor includes a control electrode connected to the first control signal, a first electrode connected to the last one of the first gate driving circuits, and a second electrode connected to the first one of the second gate driving circuits; The fourth transistor includes a control electrode connected to the second control signal, a first electrode connected to the second start signal, and a second electrode connected to the first one of the second gate driving circuits.

4. The gate driving device according to claim 3, wherein The second control circuit further includes a fifth transistor; The fifth transistor includes a control electrode for receiving a third control signal, a first electrode for receiving the invalid signal, and a second electrode connected to the first of the second gate driving circuits, and is configured to output the invalid signal to the first of the second gate driving circuits according to the third control signal, so that each of the second gate driving circuits stops outputting the second scan signal or the third scan signal.

5. The gate driving device according to claim 2, characterized in that It further includes a third gate driving unit, connected to the second gate driving unit, and configured to output a fourth scan signal row by row according to the second scan signal and stop outputting the fourth scan signal according to the invalid signal.

6. The gate driving device according to claim 5, wherein The third gate driving unit includes a third control circuit and a plurality of cascaded third gate driving circuits; The third control circuit is connected to the last of the second gate driving circuits and receives the first control signal, the second control signal, and the invalid signal, and is configured to: Output the second scan signal output by the last of the second gate driving circuits to the first of the third gate driving circuits according to the first control signal, so that each of the third gate driving circuits outputs the fourth scan signal row by row; And Output the invalid signal to the first of the third gate driving circuits according to the second control signal, so that each of the third gate driving circuits stops outputting the fourth scan signal; Wherein, the third control circuit includes a sixth transistor and a seventh transistor; The sixth transistor includes a control electrode for receiving the first control signal, a first electrode connected to the last of the second gate driving circuits, and a second electrode connected to the first of the third gate driving circuits; The seventh transistor includes a control electrode for receiving the second control signal, a first electrode for receiving the invalid signal, and a second electrode connected to the first of the third gate driving circuits.

7. The gate driving device according to claim 3, characterized in that, The scan frequency of the first scan signal and the scan frequency of the second scan signal are a first frequency, the scan frequency of the third scan signal is a second frequency, and the second frequency is greater than the first frequency.

8. The gate driving device according to claim 7, wherein: In the first mode, the first gate driving unit outputs a first scan signal row by row according to the first start signal, and the second gate driving unit outputs a second scan signal row by row according to the first scan signal, so that the display areas corresponding to the first gate driving unit and the second gate driving unit are refreshed at the first frequency; In the second mode, the first gate driving unit stops outputting the first scan signal according to the invalid signal, and the second gate driving unit outputs the third scan signal row by row according to the second start signal, so that the display area corresponding to the second gate driving unit is refreshed at the second frequency.

9. The gate driving device according to claim 8, wherein, Each stage of the first gate driving circuit and each stage of the second gate driving circuit respectively include a light emission control circuit, a driving circuit, and a reset circuit; The first start signal includes a first driving start signal, a first light-emitting start signal, and a first reset start signal that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the first gate driving circuit; The second start signal includes a second driving start signal, a second light-emitting start signal, and a second reset start signal that are respectively connected to the driving circuit, the light-emitting control circuit, and the reset circuit of the second gate driving circuit; In the first mode, the first driving start signal, the first light-emitting start signal, and the first reset start signal are in an active level state in sequence, and the second driving start signal, the second light-emitting start signal, and the second reset start signal are in an inactive level state; In the second mode, the first driving start signal, the first light-emitting start signal, and the first reset start signal are in an inactive level state, and the second driving start signal, the second light-emitting start signal, and the second reset start signal are in an active level state in sequence.

10. A display panel, characterized in that, It includes the gate driving device according to any one of claims 1 to 9 above.

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