Control device of converter with high-efficiency power factor correction function and low cost and corresponding control method

Abstract

The invention relates to a control device of a converter with a high-efficiency power factor correction function and low cost and a corresponding control method. The control device comprises a rectifier bridge (1), a DC-DC converter (2), a control module (3), a power switch MOS Q, an inductor LPFC and a detection resistor Rs, and a grid electrode of the power switch MOS Q is connected with an output DR of the control module (3); the pin VRs of the control module (3) receives the voltage on the detection resistor Rs, and the current in the boost inductor LPFC is limited through the control module (3); a pin FB input of the control module (3) controls whether the power switch MOS Q is switched on or not; the control switch pulse of the DC-DC converter (2) can be used as the input of the pin PWM sequence of the control module (3). And the internal reference level VREF and the input VRs are compared by the comparator to output a logic level. According to the circuit, the input current harmonic wave can meet the harmonic wave requirement.

Description

Technical Field

[0001] The present invention relates to a control device for a converter with high-efficiency power factor correction function and low cost, and a corresponding control method. Background Art

[0002] The power factor correction circuit is usually completed by a boost circuit. This boost circuit accomplishes two tasks simultaneously. One is to correct the input AC current waveform so that the input current waveform follows the input voltage waveform, and the harmonic current of the input AC current meets various corresponding standards. The other is to increase the output DC bus voltage to create good working conditions for the subsequent DC-DC converter. Although introducing the power factor correction circuit can accomplish the above two important tasks, corresponding costs also need to be paid, that is, the cost corresponding to all components of the power factor correction circuit and the required space, as well as the losses brought about by the operation of the power factor correction circuit. How to reduce the cost corresponding to all components of the power factor correction circuit and the required space and reduce the losses brought about by the operation of the power factor correction circuit is an urgent problem to be solved in this industry.

[0003] The inventions of CN116131596A, "Hybrid Mode Power Factor Correction Converter and Its Control Method", and CN113872432A, "A Power Factor Correction Converter and Control Method", cannot solve the above problems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a control device for a converter with low cost and high-efficiency power factor correction function and a corresponding control method.

[0005] To solve the above technical problem, the present invention provides a control device for a converter with high-efficiency power factor correction function and low cost. The control device includes a rectifier bridge, a DC-DC converter, a control module, a power switch MOS Q, an inductor L PFC , and a detection resistor Rs. The control module is a control module for the power MOS Q;

[0006] The gate of the power switch MOS Q is connected to the output DR of the control module;

[0007] The control module is respectively provided with a pin V Rs , a pin FB, and a pin PWM sequence;

[0008] The pin V of the control module Rs receives the voltage on the detection resistor Rs and effectively limits the current in the boost inductor L PFC ;

[0009] The pin FB of the control module inputs to control whether the power switch MOS Q conducts;

[0010] The PWM sequence of the pins of the control module can take the control switch pulses of the subsequent DC-DC converter as its input.

[0011] As an improvement to the high-efficiency power factor correction function and low-cost converter control device of the present invention:

[0012] The control module further includes a pin VREF; the input of this pin VREF is the output of the voltage dividing network composed of the voltage dividing resistors R1 and R2 of the DC bus.

[0013] As another improvement to the high-efficiency power factor correction function and low-cost converter control device of the present invention:

[0014] The control module further includes a pin LOAD; the signal received by this pin LOAD comes from the subsequent DC-DC converter.

[0015] As a further improvement to the high-efficiency power factor correction function and low-cost converter control device of the present invention:

[0016] The source of the power switch MOS Q is grounded through the resistor Rs, the drain of the power switch MOS Q is connected to one end of the boost inductor L PFC The drain of the power switch MOS Q is connected to the positive pole of the DC bus electrolytic capacitor C through the anode and cathode of the boost diode D. The other end of the boost inductor L PFC is connected to the positive output end of the rectifier bridge; the negative output end of the rectifier bridge is connected to the input ground end of the DC-DC converter (i.e., connected to the power ground);

[0017] The anode of the bypass diode D F is connected to the positive end of the rectifier bridge; the cathode of the bypass diode D F is connected to the positive pole of the DC bus electrolytic capacitor C. The negative pole of the DC bus electrolytic capacitor C is connected to the power ground;

[0018] The positive input end of the DC-DC converter is connected to the positive pole of the DC bus electrolytic capacitor C.

[0019] As an improvement to the high-efficiency power factor correction function and low-cost converter control device of the present invention, the source of the power switch MOS Q is grounded through the resistor Rs, the drain of the power switch MOS Q is connected to one end of the boost inductor L PFC and then divides into two paths after passing through the anode and cathode of the boost diode D. One path is connected to the voltage dividing resistor R1, and the voltage dividing resistor R1 is connected to the power ground through the voltage dividing resistor R2, and the other path is connected to the positive pole of the DC bus electrolytic capacitor C.

[0020] The boost inductor L PFCThe other end is connected to the positive output of the rectifier bridge; the negative output of the rectifier bridge is connected to the input ground terminal of the DC-DC converter;

[0021] The bypass diode D F has its anode connected to the positive terminal of the rectifier bridge; the bypass diode D F has its cathode connected to the positive electrode of the DC bus electrolytic capacitor C; the negative electrode of the DC bus electrolytic capacitor C is connected to the power ground;

[0022] The positive input of the DC-DC converter is connected to the positive terminal of the DC bus electrolytic capacitor C.

[0023] As a further improvement of the converter control device with high-efficiency power factor correction function and low cost of the present invention:

[0024] The control module is composed of a comparator, a logic inverter, and a three-input AND gate; the output of the comparator is used as one of the inputs of the three-input AND gate, the PWM sequence is the second input of the three-input AND gate, the FB input is output through the logic inverter and used as the third input of the three-input AND gate, and the output DR of the three-input AND gate drives the power switch MOS Q to conduct and cut off.

[0025] As an improvement of the converter control device with high-efficiency power factor correction function and low cost of the present invention:

[0026] The control module is composed of a comparator, a logic inverter, and a three-input AND gate; the output of the comparator is used as one of the inputs of the three-input AND gate, the PWM sequence is the second input of the three-input AND gate, the FB input is output through the logic inverter and used as the third input of the three-input AND gate, and the output DR of the three-input AND gate drives the power switch MOS Q to conduct and cut off;

[0027] The signal VREF and LOAD are output through an adder circuit to form a control voltage as a comparison level V BJ ; V BJ contains information about the DC bus voltage and the magnitude of the subsequent DC-DC output power.

[0028] The present invention also provides a converter control method with high-efficiency power factor correction function and low cost at the same time. Using the above control device, the control method includes the following:

[0029] The internal reference level VREF and the input V Rs are compared by a comparator to output a logic level;

[0030] When the input V Rs voltage is less than the internal reference level VREF, the comparator outputs a high level; if the input FB is low, the output DR of the three-input AND gate follows the PWM sequence pulse, that is, the output DR of the three-input AND gate = PWM;

[0031] When the input V Rs voltage ≥ the internal reference level VREF, the comparator outputs a low level, and the output DR of the three-input AND gate follows the switching period of the PWM sequence, but the corresponding duty cycle is smaller than that of the PWM sequence, that is, the corresponding duty cycle is determined by V Rs and VREF via the comparator;

[0032] When FB is at a high level, regardless of whether the comparator output is high or low, the output DR of the three-input AND gate is at zero level, that is, the power switch MOS Q is in the off state.

[0033] The pin V of the control module Rs receives the voltage on the detection resistor Rs, and effectively limits the current in the boost inductor L PFC through the control module.

[0034] As an improvement to the high-efficiency power factor correction function and low-cost converter control method of the present invention: it includes the following two modes:

[0035] Mode 1: When the instantaneous voltage of the rectifier bridge output voltage Vin is low, the current waveform in the boost inductor L PFC is a triangular wave sequence, and its peak current changes with the instantaneous voltage of the input AC voltage, but its maximum peak current is controlled by the internal reference level of the pin V of the control module Rs , and the current in the boost inductor L PFC does not continue to increase with the increase of the instantaneous voltage of the input AC voltage; the current in the boost inductor L PFC is output to the DC bus capacitor C through the boost diode D, thereby providing part of the energy; due to the pulling effect of the current in the boost inductor L PFC , the waveform of the rectifier bridge output voltage Vin follows the change of the input AC voltage, and the instantaneous voltage of the rectifier bridge output voltage Vin is less than the peak value of the rectifier bridge output voltage; therefore, the bypass diode D F is reverse-biased and turned off;

[0036] Mode 2: As the instantaneous voltage of the rectifier bridge output voltage Vin approaches the peak voltage, at the same time, the voltage on the DC bus capacitor C decreases due to supplying power to the subsequent DC-DC converter; the bypass diode D F is forward-biased and turned on, and similarly the boost diode D is also forward-biased and turned on; since the instantaneous voltage of the rectifier bridge output voltage Vin approaches the peak voltage, the corresponding voltage rising slope becomes gentle, and the rectifier bridge output voltage Vin directly supplies power to the DC bus capacitor C in parallel through the bypass diode D F and the boost diode D, and the voltage of the DC bus capacitor C increases to near the peak value; at the bypass diode D FDuring the period when it is connected in parallel with the boost diode D to directly supply power to the DC bus capacitor C, since it is close to the peak voltage, the rectifier bridge output voltage Vin is bypassed through the bypass diode D F and the boost diode D in parallel provides most of the energy to the DC bus capacitor C; when the bypass diode D F and the boost diode D are connected in parallel to directly supply power to the DC bus capacitor C, since the boost diode D is forward-biased and conducts, this makes the input of the pin FB of the control module a high level; this makes the power switch MOS Q in the cut-off state; as the instantaneous voltage of the rectifier bridge output voltage Vin starts to drop from the peak, the voltage difference between the instantaneous voltage of the rectifier bridge output voltage Vin and the voltage of the DC bus capacitor C starts to decrease, and the corresponding current that is directly supplied to the DC bus capacitor C through the bypass diode D F and the boost diode D in parallel also starts to decrease until it becomes zero; when the current that directly supplies power to the DC bus capacitor C through the bypass diode D F and the boost diode D is zero, the boost diode D is cut off and makes the pin FB of the control module a low level, and the power switch MOS Q will continue to conduct and cut off following the PWM sequence, that is, it switches from mode two to mode one; also due to the pulling effect of the current in the boost inductor L PFC the instantaneous voltage of the rectifier bridge output voltage Vin is less than the voltage of the DC bus capacitor C, and the bypass diode D F is reverse-biased and cut off.

[0037] As a further improvement of the converter control method with high-efficiency power factor correction function and low cost of the present invention: the instantaneous voltage of the rectifier bridge output voltage Vin drops to zero over time and increases from zero; in this case, the control is in mode one; until the instantaneous voltage of the rectifier bridge output voltage Vin is greater than or equal to the voltage of the DC bus capacitor C, it enters mode two.

[0038] As a further improvement of the converter control method with high-efficiency power factor correction function and low cost of the present invention: the control (effectively limiting) of the current in the boost inductor L PFC is specifically as follows: the PWM sequence pin input of the control module basically controls the switching period and duty cycle of the low-cost and high-efficiency power factor correction function converter; the PWM sequence input pin can take the control switch pulses of the subsequent DC-DC converter as its input; the input of the pin FB of the control module is to control whether the power MOS Q conducts; the pin FB of the control module is a logic level; the pin FB is generated according to whether the boost diode D conducts, that is, when the boost diode D conducts, the pin FB is a high level; and when the boost diode D is cut off, the pin FB is a low level; the low level of the pin FB when the boost diode D is cut off means that the current in the boost inductor L PFC decays to zero.

[0039] The beneficial effects of the present invention are mainly reflected in:

[0040] 1. The circuit of the present invention can make the input current harmonics meet the harmonic requirements.

[0041] 2. The switching loss of the circuit of the present invention is much lower than that of the conventional power factor correction circuit, which is beneficial to improving the efficiency of the system.

[0042] 3. The circuit of the present invention can be of low cost. Description of the Drawings

[0043] The following further details the specific embodiments of the present invention in conjunction with the drawings.

[0044] Figure 1 It is the circuit diagram of the implementation solution of Embodiment 1 (i.e., the circuit diagram of the power factor function solution of the present invention).

[0045] Figure 2 It is the waveforms of the rectifier bridge output current Iin and output voltage Vin.

[0046] Figure 3 For Figure 1 the specific solution of the control module 3 in

[0047] Figure 4 It is the specific solution of the method for detecting how the boost diode D conducts to make the input of the pin FB of the power MOS Q control module in block 3 be at a high level.

[0048] Figure 5 It is the circuit diagram of the implementation solution of Embodiment 2.

[0049] Figure 6 It is the circuit diagram of the implementation solution of Embodiment 3.

[0050] Figure 7 It is Figure 6 the specific solution of the control module 3 in Specific Embodiments

[0051] The following further describes the present invention in conjunction with specific embodiments, but the protection scope of the present invention is not limited thereto:

[0052] Embodiment 1

[0053] A high-efficiency power factor correction function and low-cost converter control device, as Figure 1 shown, includes a rectifier bridge 1, an inductor L PFC , a DC-DC converter 2, a power switch MOS Q, and a control module 3; the control module 3 is a power MOS Q control module;

[0054] The connection relationship is as follows:

[0055] The source of the power switch MOS Q is grounded through the resistor Rs, and the drain of the power switch MOS Q is connected to one end of the boost inductor L PFC ; the drain of the power switch MOS Q is connected to the positive electrode of the DC bus electrolytic capacitor C through the anode and cathode of the boost diode D; the gate of the power switch MOS Q is connected to the output DR of the control module 3; the other end of the boost inductor L PFC is connected to the positive output of the rectifier bridge 1; the negative output of the rectifier bridge 1 is connected to the power ground, that is, connected to the input ground terminal of the subsequent DC-DC converter 2. The anode of the bypass diode D F is connected to the positive terminal of the rectifier bridge 1; the cathode of the bypass diode D F is connected to the positive electrode of the DC bus electrolytic capacitor C. The negative electrode of the DC bus electrolytic capacitor C is connected to the power ground.

[0056] The positive input of the DC-DC converter 2 is connected to the positive terminal of the DC bus electrolytic capacitor C.

[0057] One of the inputs of the control module 3, V Rs , is connected to the detection resistor Rs; the other inputs of the control module 3 are the PWM control sequence and FB respectively.

[0058] The control module 3 is specifically as Figure 3 shown: The control module 3 is composed of a comparator, a logic inverter and a three-input AND gate; the output of the comparator is used as one of the inputs of the three-input AND gate, the PWM sequence is the second input of the three-input AND gate, and the FB input is output through the logic inverter as the third input of the three-input AND gate. The output of the three-input AND gate is DR to drive the power switch MOS Q to conduct and cut off. The internal reference level VREF and the input V Rs are compared by the comparator to output a logic level; as Figure 2 shown, the waveform of V Rs changes with the rising section waveform of the output current of the rectifier bridge.

[0059] If the input FB is at a low level:

[0060] When the input V Rs voltage is less than the internal reference level VREF, the comparator outputs a high level; the output DR of the three-input AND gate follows the PWM sequence pulse, that is, the output DR of the three-input AND gate = PWM;

[0061] When the input V Rs voltage ≥ the internal reference level VREF, the comparator outputs a low level, and the output DR of the three-input AND gate follows the switching period of the PWM sequence, but the corresponding duty cycle is smaller than the duty cycle of the PWM sequence, that is, the corresponding duty cycle is determined by V Rs and VREF through the comparator;

[0062] If the input FB is at a high level: Regardless of whether the comparator output is at a high level or a low level, the output DR of the three-input AND gate is at a zero level. That is, when FB is at a high level, the power switch MOS Q is in the off state.

[0063] In this embodiment, compared with the existing power factor correction circuit, the circuit connection relationships of the components in the power circuit are exactly the same. The difference from the existing power factor correction circuit lies in the control method of the control module 3.

[0064] For the boost circuit, the efficiency of the boost circuit changes with the difference between its input voltage and output voltage; the smaller the difference between the input voltage and output voltage of the boost circuit, the higher the efficiency of the boost circuit; conversely, the larger the difference between the input voltage and output voltage of the boost circuit, the lower the efficiency of the boost circuit.

[0065] In the critical discontinuous current control of the existing commonly used power factor correction circuit, the conduction moment of the power MOS is the moment when the current in the boost inductor L PFC decays to zero, and the conduction time of the power MOS is a fixed time, which is adjusted and changed with the size of the input power. Since the conduction time of the power MOS is a fixed time and the moment when the current in the boost inductor L PFC decays to zero is the start of the next switching cycle, this makes the peak value of the current in the boost inductor L PFC change with the instantaneous voltage of the input AC voltage, and the current in the boost inductor L PFC is a triangular wave sequence, and the peak values of each triangular wave change with the instantaneous voltage of the input AC voltage. From the relationship between the peak value of the triangular wave and twice its average value, the input AC current waveform can follow the input AC voltage through the critical discontinuous current control method of the existing commonly used power factor correction circuit. The harmonic current of this input AC current can be quite low, and the power factor can be quite high. In this control, the switching cycle changes with the difference between the input instantaneous voltage and the output voltage; the larger this difference, the shorter the corresponding switching cycle; the smaller this difference, the longer the corresponding switching cycle. In short, this switching cycle changes with the difference between the input voltage and the output voltage. To ensure that the current in the boost inductor L PFC can decay to zero, the output voltage must be greater than the peak value of the input voltage, that is, in the critical discontinuous current control of the existing commonly used power factor correction circuit, the output DC bus voltage must be greater than the input peak voltage by dozens of volts. Due to the relationship between the peak value of the triangular wave and twice its average value, using this critical discontinuous current control method, the current stress in the corresponding boost inductor L PFC is large. The large current stress will increase the switching and conduction losses, and also increase the size of the boost inductor L PFC (the boost inductor L PFCis determined by the product of its inductance value and the maximum peak current). If the maximum peak current in the boost inductor L can be limited and the output voltage can follow the input peak voltage, this can greatly reduce the switching and conduction losses, and also reduce the size of the boost inductor L PFC i.e., reduce the cost. PFC The present invention provides a control method for a low-cost and high-efficiency power factor correction function converter; as

[0066] shown, the pin V of the control module 3 Figure 1 receives the voltage on the detection resistor Rs, and the control module 3 can effectively limit the current in the maximum boost inductor L Rs The specific operation of how to effectively limit the current in the boost inductor L PFC is described as follows: The PWM sequence pin input of the control module 3 controls the switching period and duty cycle of the low-cost and high-efficiency power factor correction function converter; the PWM sequence input pin can use the control switch pulse of the subsequent DC-DC converter 2 as its input. The pin FB input of the control module 3 controls whether the power MOS Q is turned on; the pin FB of the control module 3 is a logic level. The pin FB is generated according to whether the boost diode D is turned on, that is, when the boost diode D is turned on, the pin FB is at a high level; when the boost diode D is off, the pin FB is at a low level; when the boost diode D is off, the low level of the pin FB means that the current in the boost inductor L PFC decays to zero. PFC The waveforms of the output voltage Vin (solid line) and current Iin (dashed line) of the rectifier bridge 1 shown in Figure 2 . The entire control is divided into two operating modes according to the instantaneous voltage level of the output voltage Vin of the rectifier bridge 1 (as Figure 2 shown):

[0067] Mode 1, when the instantaneous voltage of the rectifier bridge output voltage Vin is low, the current waveform in the boost inductor L PFC is like the current in the boost inductor L in the critical discontinuous current control of the existing common power factor correction circuit PFC is a triangular wave sequence, and its peak current changes with the instantaneous voltage of the input AC voltage, but its maximum peak current is controlled by the internal reference level VREF of the pin V of the control module 3, that is, the current in the boost inductor L Rs does not continue to increase with the increase of the instantaneous voltage of the input AC voltage. The current in the boost inductor L PFC is output to the DC bus capacitor C through the boost diode D to provide part of the energy. Since the boost inductor L PFC The current in the boost inductor L PFCDue to the pulling effect of the current in [description], the waveform of the output voltage Vin of the rectifier bridge 1 follows the change of the input AC voltage, that is, the instantaneous voltage of the output voltage Vin of the rectifier bridge 1 is less than the peak value of the output voltage of the rectifier bridge 1; thus, the bypass diode D F is reverse-biased and cut off.

[0068] Mode 2: As the instantaneous voltage of the output voltage Vin of the rectifier bridge approaches the peak voltage, at the same time, the voltage on the DC bus capacitor C decreases due to supplying power to the subsequent DC-DC converter 2; the bypass diode D F is forward-biased and conducts, and similarly, the boost diode D is also forward-biased and conducts; since the instantaneous voltage of the output voltage Vin of the rectifier bridge approaches the peak voltage, the corresponding voltage rising slope becomes gentle, and the output voltage Vin of the rectifier bridge is directly supplied to the DC bus capacitor C in parallel through the bypass diode D F and the boost diode D, and the voltage of the DC bus capacitor C increases to near the peak value; during the period when the bypass diode D F and the boost diode D are in parallel to directly supply power to the DC bus capacitor C, due to being close to the peak voltage, the output voltage Vin of the rectifier bridge provides most of the energy to the DC bus capacitor C through the bypass diode D F and the boost diode D in parallel. During the period when the bypass diode D F and the boost diode D are in parallel to directly supply power to the DC bus capacitor C, since the boost diode D is forward-biased and conducts, this makes the input of the pin FB of the control module 3 a high level; this makes the power MOS Q in the cut-off state. As the instantaneous voltage of the output voltage Vin of the rectifier bridge starts to decrease from the peak value, the voltage difference between the instantaneous voltage of the output voltage Vin of the rectifier bridge and the voltage of the DC bus capacitor C starts to decrease, and the corresponding current directly supplied to the DC bus capacitor C in parallel through the bypass diode D F and the boost diode D also starts to decrease until it becomes zero. When the current directly supplied to the DC bus capacitor C through the bypass diode D F and the boost diode D is zero, the boost diode D is cut off and makes the pin FB of the control module 3 a low level, and the power MOS Q will continue to conduct and cut off following the PWM sequence, that is, it changes from Mode 2 to Mode 1. Similarly, due to the pulling effect of the current in the boost inductor L PFC the instantaneous voltage of the output voltage Vin of the rectifier bridge is less than the voltage of the DC bus capacitor C, and the bypass diode D F is reverse-biased and cut off.

[0069] The instantaneous voltage of the output voltage Vin of the rectifier bridge 1 decreases to zero over time and then increases from zero; in this case, the control is in Mode 1; it enters Mode 2 until the instantaneous voltage of the output voltage Vin of the rectifier bridge is greater than or equal to the voltage of the DC bus capacitor C. Obviously, during Mode 2, the instantaneous voltage of the output voltage Vin of the rectifier bridge passes through the bypass diode D FIt is connected in parallel with the boost diode D to directly supply power to the DC bus capacitor C. At this time, the power MOS Q is in the cut-off state, and the loss of the circuit is quite low; and during Mode 2, the instantaneous voltage of the rectifier bridge output voltage Vin is bypassed through the diode D F and the boost diode D are connected in parallel to supply most of the energy of the entire AC half-cycle to the DC bus capacitor C. Therefore, this control method can make the power factor correction circuit highly efficient. Since the instantaneous voltage of the rectifier bridge output voltage Vin is bypassed through the diode D F and the boost diode D are connected in parallel to supply energy to the DC bus capacitor C, the current flowing through the boost diode D is equivalent to the current flowing through the bypass diode D F , that is, the current flowing through the boost inductor L PFC is half of the total current, that is, the effective value of the current of the boost inductor L PFC is one-half of the total effective value current; this enables the winding wire diameter of the boost inductor L PFC to be reduced, and the size of the boost inductor L PFC is reduced to reduce costs. Since the power MOS Q is in the cut-off state during Mode 2, within the entire AC half-cycle, the switching and conduction losses of the power MOS Q are greatly reduced, and a larger Rdson of the power MOS Q can be selected, thus reducing costs.

[0070] There are many methods for specifically detecting that the conduction of the boost diode D generates a high level at the input of the pin FB of the control module 3. For example, Figure 4 gives the specific implementation method; adding a PNP_BJT triode, a diode D1, and a base resistor Rb can provide the FB logic level for detecting the conduction of the boost diode D. As Figure 4 shown, when the boost diode D conducts, the forward voltage drop of the boost diode D forms a loop through the diode D1, the emitter and base of the PNP_BJT, and the base resistor Rb to generate a corresponding base current of the PNP_BJT; due to this base current, there is a collector current of the PNP_BJT; this collector current is β times the base current, and this collector current can generate a corresponding high-level FB logic signal through a resistor. When the boost diode D is cut off, the voltage drop of the boost diode D is a negative voltage; since the diode D1 is reverse-biased, the base current of the PNP_BJT is zero, and naturally the collector current of the PNP_BJT is also zero, and this collector current generates a corresponding low-level FB logic signal through a resistor. There are also many different methods for detecting that the conduction of the boost diode D generates a high level at the input of the pin FB of the power MOS Q control module in Block 3, which will not be further discussed here.

[0071] Embodiment 2

[0072] As Figure 5As shown: The connection of the power circuit is exactly the same as that of Embodiment 1, except that the control module 3 is different. That is, the control module 3 has one more pin than that of Embodiment 1. That is to say, the internal fixed VREF voltage in the control module 3 of Embodiment 1 becomes an externally input pin VREF, and the control module 3 still has the connection and control functions as Figure 3 shown. As Figure 5 shown, the input of this pin VREF is the output of the voltage division network composed of the voltage division resistors R1 and R2 of the DC bus. As described in Embodiment 1, this DC bus voltage is basically equal to the peak voltage of the input AC voltage. The input voltage of the pin VREF corresponds to the peak voltage of the input AC voltage. Since the VREF pin corresponds to the peak voltage of the input AC voltage, this makes the maximum peak current of the boost inductor L PFC controlled by the peak voltage of the corresponding input AC voltage, which enables the control method of the present invention to adapt to wide input AC voltage applications and ensure that the input current harmonic current meets the standards.

[0073] Embodiment 3

[0074] As Figure 6 shown: The connection of the power circuit is exactly the same as that of Embodiment 2, except that the control module 3 is different. That is, the control module 3 has one more pin LOAD than that of Embodiment 2. As Figure 6 shown, the signal received by this pin LOAD comes from the subsequent DC-DC converter 2.

[0075] The internal connection relationship of the control module 3 in Embodiment 3 is as Figure 7 shown. As Figure 7 shown, the signals VREF and LOAD are output through an adder circuit to form a control voltage as a comparison level V BJ of a comparator; V BJ contains information about the DC bus voltage and the output power size of the subsequent DC-DC. This makes the maximum peak current of the boost inductor L PFC controlled by the comparison level V BJ , that is, the maximum peak current of the boost inductor L PFC is controlled by the DC bus voltage and is also controlled by the output power of the subsequent DC-DC converter; that is to say, as the input AC mains voltage increases, the maximum peak current of the boost inductor L PFC increases, and vice versa. Similarly, as the output power of the subsequent DC-DC decreases, the maximum peak current of the boost inductor L PFCThe maximum peak current of the current decreases, and vice versa. If this function is not available, when the output power of the subsequent DC-DC decreases, the corresponding input power of the subsequent DC-DC also decreases; when the input power of the subsequent DC-DC decreases, the ripple voltage on the electrolytic capacitor on the corresponding DC bus decreases. The decrease in the ripple voltage on the electrolytic capacitor means that the duration of mode 2 decreases, while the duration of mode 1 increases; the increase in the duration of mode 1 means that the boost inductor L PFC The effective value of the current increases, that is, the loss increases; and if this function is available, when the output power of the subsequent DC-DC decreases, the corresponding input power of the subsequent DC-DC also decreases; due to this function, this makes the boost inductor L PFC The maximum peak current of the current decreases, but the ripple voltage on the electrolytic capacitor does not decrease much, which means that the duration of mode 2 does not decrease much, and the duration of mode 1 does not increase much; which means that the boost inductor L PFC The effective value of the current does not increase, that is, the loss is reduced; that is, the duration of mode one and mode two is basically fixed, and does not change with the input AC voltage or the output power; this is conducive to making its input current harmonics meet the harmonic current standards under the conditions of wide voltage range input AC input and output power changes.

[0076] Finally, it should be noted that the above examples are only some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments, and there are many variations. All variations that can be directly derived or associated with the content disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

Claims

1. A converter control device with high-efficiency power factor correction function and low cost, characterized in that: The control device includes a rectifier bridge (1), a DC-DC converter (2), a control module (3), a power switch MOS Q, and an inductor L PFC , a detection resistor Rs, and the control module (3) is a power MOS Q control module; The gate of the power switch MOS Q is connected to the output DR of the control module (3). The control module (3) is respectively provided with a pin V Rs , a pin FB, and a pin PWM sequence; Pin V of the control module (3) Rs Receives the voltage across the detection resistor Rs and limits the current in the boost inductor L via the control module (3) PFC in it; The control module (3) controls whether the power switch MOS Q conducts through the input of its pin FB. The control module (3) can take the control switch pulses of the DC-DC converter (2) as the input of its pin PWM sequence.

2. The high-efficiency power factor correction function low-cost converter control device according to claim 1, characterized in that: The control module (3) further includes a pin VREF; the input of this pin VREF is the output of the voltage dividing network composed of the voltage dividing resistors R1 and R2 of the DC bus.

3. The high-efficiency power factor correction function low-cost converter control device according to claim 2, wherein: The control module (3) further includes a pin LOAD; the signal received by this pin LOAD comes from the subsequent DC-DC converter (2).

4. The converter control device with high-efficiency power factor correction function and low cost according to claim 1, characterized in that: The source of the power switch MOS Q is grounded through the resistor Rs, and the drain of the power switch MOS Q is connected to one end of the boost inductor L PFC The drain of the power switch MOS Q is connected to the positive electrode of the DC bus electrolytic capacitor C through the anode and cathode of the boost diode D. The other end of the boost inductor L PFC is connected to the positive output terminal of the rectifier bridge (1); the negative output terminal of the rectifier bridge (1) is connected to the input ground terminal of the DC-DC converter (2); Bypass diode D F The anode of which is connected to the positive terminal of the rectifier bridge (1); the bypass diode D F The cathode of which is connected to the positive electrode of the DC bus electrolytic capacitor C; the negative electrode of the DC bus electrolytic capacitor C is connected to the power ground; The positive input terminal of the DC-DC converter (2) is connected to the positive terminal of the electrolytic capacitor C of the DC bus.

5. The converter control device with high-efficiency power factor correction function and low cost according to claim 2, characterized in that: The source of the power switch MOS Q is grounded through the resistor Rs, and the drain of the power switch MOS Q is connected to one end of the boost inductor L PFC One end of the power switch MOS Q is divided into two paths through the anode and cathode of the boost diode D. One path is connected to the voltage-dividing resistor R1, and the voltage-dividing resistor R1 is connected to the power ground through the voltage-dividing resistor R2. The other path is connected to the positive electrode of the DC bus electrolytic capacitor C Boost inductor L PFC The other end is connected to the positive output of the rectifier bridge (1); the negative output of the rectifier bridge (1) is connected to the input ground terminal of the DC-DC converter (2); Bypass diode D F The anode of which is connected to the positive terminal of the rectifier bridge (1); the bypass diode D F The cathode of which is connected to the positive electrode of the DC bus electrolytic capacitor C; the negative electrode of the DC bus electrolytic capacitor C is connected to the power ground; The positive input terminal of the DC-DC converter (2) is connected to the positive terminal of the electrolytic capacitor C of the DC bus.

6. The converter control device with high-efficiency power factor correction function and low cost according to claim 1, 2, 4 or 5, characterized in that: The control module (3) is composed of a comparator, a logic inverter and a three-input AND gate; the output of the comparator is one of the inputs of the three-input AND gate, the PWM sequence is the second input of the three-input AND gate, the FB input is output through the logic inverter as the third input of the three-input AND gate, and the output DR of the three-input AND gate drives the power switch MOS Q to conduct or cut off.

7. The converter control device with high-efficiency power factor correction function and low cost according to claim 3, characterized in that: The control module (3) is composed of a comparator, a logic inverter and a three-input AND gate; the output of the comparator is one of the inputs of the three-input AND gate, the PWM sequence is the second input of the three-input AND gate, the FB input is output through the logic inverter as the third input of the three-input AND gate, and the output DR of the three-input AND gate drives the power switch MOS Q to conduct or cut off; The signal VREF and LOAD are output through an adder circuit to form a control voltage as a comparison level V of a comparator BJ ; V BJ contains information on the DC bus voltage and the magnitude of the subsequent DC-DC output power.

8. A converter control method with high efficiency power factor correction function and low cost, characterized in that: Using the control device according to any one of claims 1 to 7, the control method includes the following: Internal reference level VREF and input V Rs The comparator compares and outputs a logic level; When the input V Rs The voltage is less than the internal reference level VREF, and the comparator outputs a high level; if the input FB is low, the output DR of the three-input AND gate follows the PWM sequence pulse, that is, the output DR of the three-input AND gate = PWM; When the input V Rs voltage ≥ internal reference level VREF, the comparator outputs a low level, and the output DR of the three-input AND gate follows the switching period of the PWM sequence, but the corresponding duty cycle is smaller than that of the PWM sequence, that is, the corresponding duty cycle is determined by V Rs and VREF through the comparator; When FB is at a high level, regardless of whether the output of the comparator is at a high level or a low level, the output DR of the three-input AND gate is at a zero level, that is, the power switch MOS Q is in a cut-off state; Pin V of the control module (3) Rs receives the voltage across the detection resistor Rs, and effectively limits the current in the boost inductor L PFC through the control module (3).

9. The high-efficiency power factor correction function low-cost converter control method according to claim 8, characterized in that, It includes the following two modes: Mode 1: When the instantaneous voltage of the rectifier bridge output voltage Vin is low, the current in the boost inductor L PFC flows through the boost diode D and outputs to the DC bus capacitor C, thereby providing part of the energy; due to the pulling effect of the current in the boost inductor L PFC , the waveform of the rectifier bridge (1) output voltage Vin follows the change of the input AC voltage, and the instantaneous voltage of the rectifier bridge (1) output voltage Vin is less than the peak value of the rectifier bridge (1) output voltage; therefore, the bypass diode D F is reverse-biased and cut off; Mode 2: As the instantaneous voltage of the rectifier bridge output voltage Vin approaches the peak voltage, the rectifier bridge output voltage Vin, through the bypass diode D F and the boost diode D in parallel, provides most of the energy to the DC bus capacitor C; during the period when the bypass diode D F and the boost diode D in parallel directly supply power to the DC bus capacitor C, since the boost diode D is forward-biased and conducts, the input of the pin FB of the control module (3) is at a high level; thus causing the power switch MOS Q to be in the cut-off state; as the instantaneous voltage of the rectifier bridge (1) output voltage Vin starts to drop from the peak, the voltage difference between the instantaneous voltage of the rectifier bridge (1) output voltage Vin and the voltage of the DC bus capacitor C starts to decrease, and correspondingly, the current supplied directly to the DC bus capacitor C through the bypass diode D F and the boost diode D in parallel also starts to decrease until it becomes zero; when the current supplied directly to the DC bus capacitor C through the bypass diode D F and the boost diode D is zero, the boost diode D is cut off and the pin FB of the control module (3) is at a low level, and the power switch MOS Q will continue to conduct and cut off following the PWM sequence, that is, it changes from Mode 2 to Mode 1; also due to the pulling effect of the current in the boost inductor L PFC the instantaneous voltage of the rectifier bridge (1) output voltage Vin is less than the voltage of the DC bus capacitor C, and the bypass diode D F is reverse-biased and cut off.

10. The converter control method with high-efficiency power factor correction function and low cost according to claim 9, characterized in that: The instantaneous voltage of the output voltage Vin of the rectifier bridge (1) decreases to zero over time and then increases from zero; in this case, the control is in Mode 1; until the instantaneous voltage of the output voltage Vin of the rectifier bridge (1) is greater than or equal to the voltage of the DC bus capacitor C, it enters Mode 2.

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