Semiconductor structure and preparation method thereof
By using N-sided conductive contact holes and chemical vapor deposition processes in the semiconductor structure, the problem of excessive contact resistance is solved and the current transmission capability of semiconductor devices is improved.
Patent Information
- Application Number
- CN202510421254.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-11
AI Technical Summary
As the size of the semiconductor device decreases, the Schottky barrier and metal-induced gap state when the metal contacts the semiconductor lead to excessive contact resistance and enhanced resistance and capacity delay, which affects the current size and cannot meet the working requirements of the semiconductor device.
The cross-sectional shape of the conductive contact hole is N-sided (N≥5), and a barrier layer covering the conductive hole is formed in combination with the chemical vapor deposition process, increasing the contact area between metal and semiconductor and reducing resistance.
It effectively reduces resistance, improves the performance of semiconductor devices, and improves the current transmission capability.
Smart Images
Figure CN120302674A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a method for preparing the same. Background Art
[0002] In the manufacturing of integrated circuits, as the size of semiconductor devices continues to shrink, when metals come into contact with semiconductors, Schottky barriers and metal-induced gap states result in excessive contact resistance, enhanced resistance-capacitance delay, such that the magnitude of the current cannot meet the working requirements of semiconductor devices, increasingly affecting the performance of semiconductor devices.
[0003] Therefore, how to reduce resistance and further improve the performance of semiconductor devices is an urgent problem to be solved. Summary of the Invention
[0004] Based on this, embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can reduce resistance and further improve the performance of semiconductor devices.
[0005] In some embodiments of the present application, on the one hand, the present application provides a semiconductor structure, including: a substrate, a dielectric layer, and a conductive contact hole. The dielectric layer is formed on one side of the substrate. The conductive contact hole penetrates the dielectric layer and extends into the substrate. Among them, the conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer, and the cross-sectional shape of the first conductive hole is an N-sided polygon, where N≥5.
[0006] In some embodiments of the present application, the semiconductor structure further includes: a first barrier layer. The first barrier layer covers the surface of the first conductive hole facing away from the substrate.
[0007] In some embodiments of the present application, the semiconductor structure further includes: a second barrier layer and a conductive contact structure. The second barrier layer covers the surface of the first barrier layer facing away from the first conductive hole and the surface of the second conductive hole facing away from the dielectric layer. The conductive contact structure fills the conductive contact hole.
[0008] In some embodiments of the present application, the material of the first barrier layer includes titanium. The material of the second barrier layer includes titanium nitride.
[0009] In some embodiments of the present application, the N-sided polygon includes: a pentagon, a hexagon, a heptagon, or an octagon.
[0010] In some embodiments of the present application, on the other hand, the present application also provides a method for preparing a semiconductor structure, including the following steps:
[0011] Provide a substrate;
[0012] Form a dielectric layer on one side of the substrate;
[0013] Form a conductive contact hole that penetrates the dielectric layer and extends into the substrate.
[0014] Among them, the conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer. The cross-sectional shape of the first conductive hole is an N-sided polygon, where N ≥ 5.
[0015] In some embodiments of the present application, the first conductive hole formed in the substrate includes: etching the substrate with tetramethylammonium hydroxide or ammonia monohydrate to form the first conductive hole in the substrate.
[0016] In some embodiments of the present application, the method for manufacturing a semiconductor structure further includes:
[0017] Form a first barrier layer covering the surface of the first conductive hole facing away from the substrate.
[0018] In some embodiments of the present application, the method for manufacturing a semiconductor structure further includes:
[0019] Form a second barrier layer covering the surface of the first barrier layer facing away from the first conductive hole and the surface of the second conductive hole facing away from the dielectric layer;
[0020] Fill the conductive contact hole to form a conductive contact structure.
[0021] In some embodiments of the present application, forming the first barrier layer covering the surface of the first conductive hole facing away from the substrate includes: forming the first barrier layer covering the surface of the first conductive hole facing away from the substrate by chemical vapor deposition.
[0022] The semiconductor structure and its manufacturing method provided by the present application can / at least have the following advantages:
[0023] In the embodiments of the present application, the conductive contact hole penetrates the dielectric layer and extends into the substrate. The conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer. The cross-sectional shape of the first conductive hole is an N-sided polygon, where N ≥ 5. That is, the cross-sectional shape of the conductive contact hole located in the substrate is an N-sided polygon, thereby increasing the contact area between the metal and the semiconductor, effectively reducing the resistance, and further improving the performance of the semiconductor device.
[0024] In addition, tetramethylammonium hydroxide or ammonia monohydrate has different etching rates for substrates with different crystal planes, thereby forming a first conductive hole with an N-sided polygon cross-sectional shape in the substrate.
[0025] Furthermore, by forming the first barrier layer covering the surface of the first conductive hole facing away from the substrate in combination with chemical vapor deposition, the filling ability is ensured, and voids at the bottom of the first conductive hole are avoided. Description of the Drawings
[0026] Figure 1A diagram showing the relationship between the size and resistance of a semiconductor structure;
[0027] Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application, or a cross-sectional schematic diagram of the structure in step S300 in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
[0028] Figure 3 A cross-sectional schematic diagram of another semiconductor structure provided by an embodiment of the present application, or a cross-sectional schematic diagram of the structure in step S600 in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
[0029] Figure 4 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
[0030] Figure 5 A flowchart of another method for manufacturing a semiconductor structure provided by an embodiment of the present application;
[0031] Figure 6 A cross-sectional schematic diagram of the structure in step S100 in another method for manufacturing a semiconductor structure provided by an embodiment of the present application;
[0032] Figure 7 A cross-sectional schematic diagram of the structure in step S200 in another method for manufacturing a semiconductor structure provided by an embodiment of the present application.
[0033] Description of reference numerals: 1, substrate; 2, dielectric layer; 3, conductive contact hole; 31, first conductive hole; 32, second conductive hole; 41, first conductive hole; 42, second barrier layer; 5, conductive contact structure; G, gate structure; 101, gate oxide layer; 102, oxide semiconductor layer; 103, gate dielectric layer; 104, gate electrode. Detailed embodiments
[0034] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0036] In the case of using "comprising", "having", and "including" described in this document, unless explicit limiting terms are used, such as "only", "consisting of", etc., another component may be added. Unless otherwise mentioned, terms in the singular form may include the plural form and should not be construed as having a quantity of one.
[0037] In addition, in order to clearly show multiple layers and regions in the drawings, the thicknesses of the layers and the regions in the illustrations are enlarged to clearly indicate the relative positions between the layers and the distribution of the regions. When a part of a layer, film, region, plate, etc. is stated to be "on one side" of another part, this statement includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And it can be understood that when a part of a layer, film, region, plate, etc. is stated to be "on one side" of another part, it generally refers to the side directly above the other part.
[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0040] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein, but include shape deviations resulting from, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of regions of the device, and do not limit the scope of the present disclosure.
[0041] Based on this, embodiments of the present application provide a method for measuring a semiconductor structure.
[0042] In integrated circuit manufacturing, as the size of semiconductor devices continues to shrink, when metal contacts the semiconductor, Schottky barriers and metal-induced gap states result in excessive contact resistance, enhanced resistance-capacitance delay, causing the magnitude of the current to fail to meet the operating requirements of semiconductor devices, and having an increasingly greater impact on the performance of semiconductor devices. Please refer to Figure 1 , in the via resistance, the interfacial resistance accounts for an increasingly large proportion, and improving the interfacial resistance has become the main method for reducing the via resistance.
[0043] Therefore, how to reduce the resistance to further improve the performance of semiconductor devices is an urgent problem to be solved.
[0044] Based on this, embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can reduce the resistance and thus further improve the performance of semiconductor devices.
[0045] Please refer to Figure 2, on the one hand, the present application provides a semiconductor structure, including: a substrate 1, a dielectric layer 2, and a conductive contact hole 3. The dielectric layer 2 is formed on one side of the substrate 1. The conductive contact hole 3 penetrates the dielectric layer 2 and extends into the substrate 1. Among them, the conductive contact hole 3 includes a first conductive hole 31 formed in the substrate 1 and a second conductive hole 32 formed in the dielectric layer 2, and the cross-sectional shape of the first conductive hole 31 is an N-sided polygon, where N≥5.
[0046] In an embodiment of the present application, the conductive contact hole 3 penetrates the dielectric layer 2 and extends into the substrate 1. The conductive contact hole 3 includes a first conductive hole 31 formed in the substrate 1 and a second conductive hole 32 formed in the dielectric layer 2, and the cross-sectional shape of the first conductive hole 31 is an N-sided polygon, where N≥5. That is, the cross-sectional shape of the conductive contact hole 3 located in the substrate 1 is an N-sided polygon, thereby increasing the contact area between the metal and the semiconductor, effectively reducing the resistance, and further improving the performance of the semiconductor device.
[0047] In some embodiments, please refer to Figure 3 , the semiconductor structure further includes: a first barrier layer 41. The first barrier layer 41 covers the surface of the first conductive hole 31 facing away from the substrate 1.
[0048] In some embodiments, please continue to refer to Figure 3 , the semiconductor structure further includes: a second barrier layer 42 and a conductive contact structure 5. The second barrier layer 42 covers the surface of the first barrier layer 41 facing away from the first conductive hole 31 and the surface of the second conductive hole 32 facing away from the dielectric layer 2. The conductive contact structure 3 fills the conductive contact hole 3.
[0049] In some embodiments, the material of the first barrier layer 41 includes titanium. The material of the second barrier layer 42 includes titanium nitride.
[0050] In some embodiments, the N-sided polygon includes: a pentagon, a hexagon, a heptagon, or an octagon.
[0051] In some embodiments, the semiconductor structure further includes: a gate structure G. The gate structure G includes a gate oxide layer 101, an oxide semiconductor layer 102, a gate dielectric layer 103, and a gate 104.
[0052] In some examples, the gate oxide layer 101 includes, but is not limited to: a silicon oxide layer.
[0053] In some examples, the material of the oxide semiconductor layer 102 includes, but is not limited to: one or a combination of several common oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or indium oxide tungsten oxide (In2O3:WO3, IWO).
[0054] In some examples, the material of the gate dielectric layer 103 includes, but is not limited to, one or a combination of several high-k dielectric materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO).
[0055] In some examples, the material of the gate 104 includes, but is not limited to, one or a combination of several conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminide (TiAl), or tantalum nitride (TaN).
[0056] Please refer to Figure 4 , the embodiment of the present application further provides a method for manufacturing a semiconductor structure, including steps S100 to S300.
[0057] S100, providing a substrate.
[0058] S200, forming a dielectric layer on one side of the substrate.
[0059] S300, forming a conductive contact hole that penetrates the dielectric layer and extends into the substrate.
[0060] Among them, the conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer. The cross-sectional shape of the first conductive hole is an N-sided polygon, where N≥5.
[0061] In the embodiment of the present application, the conductive contact hole 3 penetrates the dielectric layer 2 and extends into the substrate 1. The conductive contact hole 3 includes a first conductive hole 31 formed in the substrate 1 and a second conductive hole 32 formed in the dielectric layer 2. The cross-sectional shape of the first conductive hole 31 is an N-sided polygon, where N≥5. That is, the cross-sectional shape of the conductive contact hole 3 located in the substrate 1 is an N-sided polygon, thereby increasing the contact area between the metal and the semiconductor, effectively reducing the resistance, and further improving the performance of the semiconductor device.
[0062] In some embodiments, the first conductive hole formed in the substrate includes: etching the substrate with tetramethylammonium hydroxide or ammonia monohydrate to form the first conductive hole in the substrate.
[0063] In the embodiment of the present application, tetramethylammonium hydroxide or ammonia monohydrate has different etching rates for substrates with different crystal planes, thereby forming a first conductive hole with an N-sided polygon cross-sectional shape in the substrate.
[0064] In some embodiments, please refer to Figure 5 , the method for manufacturing a semiconductor structure further includes step S400.
[0065] S400 forms a first barrier layer covering the surface of the first conductive via away from the substrate surface.
[0066] In some embodiments, please continue to refer to Figure 5 , the method for preparing the semiconductor structure further includes steps S500 to S600.
[0067] S500 forms a second barrier layer covering the surface of the first barrier layer away from the first conductive via and the surface of the second conductive via away from the dielectric layer.
[0068] S600 fills the conductive contact via to form a conductive contact structure.
[0069] In some embodiments, step S500 forming a first barrier layer covering the surface of the first conductive via away from the substrate surface includes: forming a first barrier layer covering the surface of the first conductive via away from the substrate surface by chemical vapor deposition.
[0070] In the embodiments of the present application, by forming a first barrier layer covering the surface of the first conductive via away from the substrate surface in combination with chemical vapor deposition, the filling ability is ensured and voids at the bottom of the first conductive via are avoided.
[0071] It should be noted that in the above embodiments, the execution of each step in the method does not have a strict order limit. These steps may not necessarily be executed in the described order and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be executed at the same time but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding semiconductor structure.
[0072] To more clearly illustrate the method for preparing the semiconductor structure provided in the above embodiments, the following is combined with Figures 2 to 7 to elaborate on this preparation method in detail.
[0073] In step S100, please refer to Figure 4 in step S100 and Figure 6 , provide the substrate 1.
[0074] In some examples, the material of the substrate 1 can be any suitable substrate material known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc. Or it can be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Or it can also be double-sided polished wafers (DSP), and can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment does not limit here.
[0075] In step S200, please refer to Figure 4 step S200 in Figure 7 and form a dielectric layer 2 on one side of the substrate 1.
[0076] Specifically, taking the substrate 1 as a silicon substrate as an example, a silicon oxide layer can be formed on one side of the substrate 1 as the dielectric layer 2 by, but not limited to, a deposition process.
[0077] Specifically, the thickness of the dielectric layer 2 can be set according to actual needs.
[0078] In an alternative embodiment, before forming the dielectric layer 2 on one side of the substrate 1, it may further include a step of cleaning the substrate 1. By cleaning, impurities on the surface of the substrate 1 can be removed, avoiding affecting subsequent processes, and thus ensuring the performance of the device.
[0079] Specifically, the substrate 1 can be cleaned with a cleaning solution. The substrate 1 can be placed in a cleaning tank containing the cleaning solution for cleaning; of course, the substrate 1 can also be cleaned by spraying. The cleaning solution and cleaning process used for specifically cleaning the substrate 1 are known to those skilled in the art and will not be elaborated here.
[0080] It should be noted that after cleaning the substrate 1, it further includes a step of drying the substrate 1. The method of drying the substrate 1 is well known to those skilled in the art and will not be elaborated here.
[0081] In some embodiments, please continue to refer to Figure 7 and before forming the dielectric layer 2 on one side of the substrate 1, it may further include forming a gate structure G. The gate structure G includes a gate oxide layer 101, an oxide semiconductor layer 102, a gate dielectric layer 103, and a gate 104.
[0082] In some examples, the gate oxide layer 101 includes, but is not limited to, a silicon oxide layer.
[0083] In some examples, the material of the oxide semiconductor layer 102 includes, but is not limited to, one or a combination of several common oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or indium tungsten oxide (In2O3:WO3, IWO).
[0084] In some examples, the material of the gate dielectric layer 103 includes, but is not limited to, one or a combination of several high-k dielectric constant materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), or hafnium lanthanum oxide (HfLaO).
[0085] In some examples, the material of the gate 104 includes, but is not limited to, one or a combination of several conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminide (TiAl), or tantalum nitride (TaN).
[0086] In step S300, refer to Figure 4 step S300 in Figure 2 , and a conductive contact hole 3 is formed through the dielectric layer 2 and extending into the substrate 1.
[0087] Among them, the conductive contact hole 3 includes a first conductive hole 31 formed in the substrate 1 and a second conductive hole 32 formed in the dielectric layer 2. The cross-sectional shape of the first conductive hole 31 is an N-sided polygon, where N≥5.
[0088] In some embodiments, the N-sided polygon includes: a pentagon, a hexagon, a heptagon, or an octagon.
[0089] In some embodiments, the first conductive hole 31 formed in the substrate 1 includes: etching the substrate 1 with tetramethylammonium hydroxide or ammonia monohydrate to form the first conductive hole 31 in the substrate 1.
[0090] In the embodiments of the present application, tetramethylammonium hydroxide or ammonia monohydrate has different etching rates for substrates 1 with different crystal planes, so as to form the first conductive hole 31 with a cross-sectional shape of an N-sided polygon in the substrate 1.
[0091] In step S400, refer to Figure 5 step S400 in Figure 3 , and a first barrier layer 41 is formed to cover the surface of the first conductive hole 31 facing away from the substrate 1.
[0092] In some embodiments, the material of the first barrier layer includes titanium.
[0093] In some embodiments, forming the first barrier layer 41 covering the surface of the first conductive via 31 facing away from the substrate 1 includes: forming the first barrier layer 41 covering the surface of the first conductive via 31 facing away from the substrate 1 by chemical vapor deposition.
[0094] In the embodiments of the present application, by forming the first barrier layer 41 covering the surface of the first conductive via 31 facing away from the substrate 1 in combination with the chemical vapor deposition process, the filling ability is ensured, and voids at the bottom of the first conductive via 31 are avoided.
[0095] In step S500, please refer to Figure 5 step S500 in Figure 3 , and form a second barrier layer 42 covering the surface of the first barrier layer 41 facing away from the first conductive via 31 and the surface of the second conductive via 32 facing away from the dielectric layer 2.
[0096] In some embodiments, the material of the second barrier layer 42 includes titanium nitride.
[0097] In some embodiments, forming the second barrier layer 42 covering the surface of the first barrier layer 41 facing away from the first conductive via 31 and the surface of the second conductive via 32 facing away from the dielectric layer 2 includes: forming the second barrier layer 42 covering the surface of the first barrier layer 41 facing away from the first conductive via 31 and the surface of the second conductive via 32 facing away from the dielectric layer 2 by chemical vapor deposition.
[0098] In step S600, please refer to Figure 5 step S600 in Figure 3 , and fill the conductive contact via 3 to form a conductive contact structure 5.
[0099] In some embodiments, the material of the conductive contact via 3 includes metal. For example, the material of the conductive contact via 3 can be tungsten metal.
[0100] In some embodiments, filling the conductive contact via 3 to form a conductive contact structure 5 includes: filling the conductive contact via 3 by chemical vapor deposition to form a conductive contact structure 5.
[0101] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0102] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: Substrate; Dielectric layer, formed on one side of the substrate; Conductive contact hole, penetrating through the dielectric layer and extending into the substrate; Wherein, the conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer, and the cross-sectional shape of the first conductive hole is an N-sided polygon, N≥5.
2. The semiconductor structure according to claim 1, wherein Further comprising: First barrier layer, covering the surface of the first conductive hole facing away from the substrate.
3. The semiconductor structure according to claim 2, wherein Further comprising: Second barrier layer, covering the surface of the first barrier layer facing away from the first conductive hole and the surface of the second conductive hole facing away from the dielectric layer; Conductive contact structure, filling the conductive contact hole.
4. The semiconductor structure according to claim 3, wherein The material of the first barrier layer includes titanium; the material of the second barrier layer includes titanium nitride.
5. The semiconductor structure according to claim 1, wherein The N-sided polygon includes: pentagon, hexagon, heptagon or octagon.
6. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a dielectric layer on one side of the substrate; Forming a conductive contact hole penetrating through the dielectric layer and extending into the substrate; Wherein, the conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the dielectric layer, and the cross-sectional shape of the first conductive hole is an N-sided polygon, N≥5.
7. The method for preparing a semiconductor structure according to claim 6, wherein, The first conductive hole formed in the substrate includes: etching the substrate with tetramethylammonium hydroxide or aqueous ammonia to form the first conductive hole in the substrate.
8. The method for manufacturing a semiconductor structure according to claim 6, wherein Further comprising: Forming a first barrier layer covering the surface of the first conductive hole facing away from the substrate.
9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, Further comprising: Forming a second barrier layer covering the surface of the first barrier layer facing away from the first conductive hole and the surface of the second conductive hole facing away from the dielectric layer; Filling the conductive contact hole to form a conductive contact structure.
10. The method for fabricating a semiconductor structure according to claim 8, wherein, The forming of the first barrier layer covering the surface of the first conductive hole facing away from the substrate includes: forming a first barrier layer covering the surface of the first conductive hole facing away from the substrate by chemical vapor deposition process.