Heterojunction-based silicon carbide groove type MOSFET device structure and preparation process thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and particularly to a silicon carbide trench MOSFET device structure based on a heterojunction and a preparation process thereof. Background Art

[0002] Silicon carbide (SiC) MOSFETs have become an ideal choice for high-voltage and high-power devices due to their advantages such as high breakdown field strength, high thermal conductivity, and low on-resistance. However, traditional planar SiC MOSFETs have the "silicon limit" contradiction between specific on-resistance (Ron,sp) and breakdown voltage (BV), and although the trench structure can improve the on-state characteristics, it faces problems such as poor gate oxide reliability, a decrease in carrier mobility caused by heterojunction interface defects, and electric field concentration at the bottom of the trench.

[0003] A prior patent discloses a silicon carbide trench gate MOSFET based on a heterojunction and a manufacturing method thereof (publication number CN116130513A). The structure includes a drain electrode, a first-conductivity-type substrate, a first-conductivity-type epitaxial layer, a second-conductivity-type shielding region, a second trench, a first trench, a second-conductivity-type doped polysilicon, a gate dielectric, a gate electrode, a second-conductivity-type well region, a first-conductivity-type source region, an isolation dielectric layer, and a source electrode. In the technology disclosed in this patent, the single-conductivity-layer design in the trench limits the carrier transport efficiency, and the flat substrate structure easily causes uneven current distribution, further restricting the optimization of device performance. Summary of the Invention

[0004] The present invention provides a silicon carbide trench MOSFET device structure based on a heterojunction and a preparation process thereof to solve the existing technical problems, and solves the problems of electric field concentration, high on-resistance, large switching losses, and insufficient structural scalability existing in existing devices.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide trench MOSFET device structure based on a heterojunction includes a plurality of MOS cells arranged side by side. Each MOS cell includes a drain, a source, a gate, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. A trench is formed on the upper surface of each MOS cell and below the gate, and an N+ layer is deposited inside the trench. The N+ layer includes a left N+ layer and a right N+ layer, and a filling medium is formed between the left N+ layer and the right N+ layer by ion implantation; The cross-sectional profile of the N substrate layer inside each MOS cell is in the shape of being high and convex on both sides and low and concave in the middle. Contact layers are provided on both sides of the N substrate layer in each MOS cell, and the contact layers are in ohmic contact with the drain.

[0006] Further, the filling medium is a centered N-layer, and the contact layer is a P-type contact layer.

[0007] Further, a semi-circular groove is formed on the surface of the N-well layer by etching, and a metal dielectric layer is deposited in the semi-circular groove, and the metal dielectric layer is in direct contact with the source electrode.

[0008] Further, a plurality of blocking ion bubbles are formed by ion implantation on the left and right sides of the N drift layer inside a single MOS cell, and the plurality of blocking ion bubbles are arranged in a right triangle, and the hypotenuse side of the right triangle arrangement is close to the N+ layer.

[0009] Further, the filling medium is a centered P-layer, and the contact layer is an N-type contact layer.

[0010] Further, a doped P-layer is formed by ion implantation at the inner bottom end of the centered N-layer.

[0011] A preparation process of a silicon carbide trench MOSFET device structure based on a heterojunction, the specific steps are as follows: S1. Grow an N drift layer on an N substrate layer, and sequentially form a P+ layer, an N-well layer, and a P-well layer by ion implantation; S2. Perform trench etching on the upper surface of the cell, deposit an N+ layer on the inner wall of the trench, and separate it into a left N+ layer and a right N+ layer by a masking technique; S3. Form a centered N-layer by ion implantation between the left and right N+ layers, and implant a doped P-layer at the bottom of the centered N-layer; S4. Inject and form a P-type contact layer in the high convex regions on both sides of the N substrate to form an ohmic contact with the drain; S5. Etch a semi-circular groove on the surface of the N-well layer, deposit a metal dielectric layer and make it in direct contact with the source electrode; S6. Grow a gate oxide layer above the trench, deposit polysilicon to form a gate, prepare a drain on the back of the device, and prepare a source on the front and connect it to the metal dielectric layer.

[0012] Further, in the step S4, blocking ion bubbles arranged in a right triangle can be injected on the left and right sides of the N drift layer, and the hypotenuse faces the N+ layer.

[0013] A silicon carbide trench MOSFET device structure based on a heterojunction and a preparation process thereof provided by the present invention, compared with the prior art, the effects obtained by this method are as follows: 1. Through the design of the split left N+ layer and right N+ layer in the trench, combined with the centrally filled N- layer or P- layer in the middle, the present invention effectively disperses the electric field concentration at the bottom of the trench, and further suppresses the electric field peak at the edge of the N drift layer in cooperation with the right-angled triangle arrangement of the barrier ion bubbles, significantly improving the breakdown voltage and reliability of the device, and is applicable to high-voltage application scenarios.

[0014] 2. The present invention adopts a special-shaped structure with high protrusions on both sides and a low depression in the middle for the N substrate layer, and a P-type contact layer or an N-type contact layer is provided in the high protrusion areas on both sides to form a low-resistance ohmic contact with the drain. This design shortens the current path in the vertical direction, reduces the on-resistance, and at the same time improves the on-state efficiency under large current, optimizing the power transmission performance.

[0015] 3. The present invention etches a semi-circular groove on the surface of the N-well layer and deposits a metal dielectric layer to make it in direct contact with the source. This structure increases the source contact area, reduces the contact resistance and parasitic capacitance, and at the same time optimizes the carrier injection efficiency, helping to improve the switching speed and dynamic response performance.

[0016] 4. The preparation process of the present invention supports a variety of heterojunction configurations and optional functional layers, and precise doping is achieved through ion implantation and masking technology. This flexibility allows for (customizing device parameters) according to different application requirements, while maintaining the compatibility and scalability of the process steps. Brief Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the first embodiment in the present invention; Figure 2 It is a schematic diagram of the second embodiment in the present invention; Figure 3 It is a schematic diagram of the third embodiment in the present invention; Figure 4 It is a schematic diagram of the fourth embodiment in the present invention; Figure 5 It is a schematic diagram of the fifth embodiment in the present invention.

[0018] In the figure: 1. Drain; 2. Source; 3. Gate; 4. P+ layer; 5. N-well layer; 6. P-well layer; 7. N substrate layer; 8. N drift layer; 9. N+ layer; 10. Centrally filled N- layer; 11. P-type contact layer; 12. Barrier ion bubble; 13. N-type contact layer; 14. Centrally filled P- layer; 15. Doped P- layer; 21. Metal dielectric layer; 91. Left N+ layer; 92. Right N+ layer. Detailed Embodiments

[0019] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0020] AsFigures 1-5 As shown, according to one aspect of the present invention, a preparation process for a silicon carbide trench MOSFET device structure based on a heterojunction is provided, and the specific steps are as follows: Step 1: Grow an N-drift layer 8 on an N-substrate layer 7, and sequentially form a P+ layer 4, an N-well layer 5, and a P-well layer 6 by ion implantation; Step 2: Perform trench etching on the upper surface of the cell, deposit an N+ layer 9 on the inner wall of the trench, and separate it into a left N+ layer 91 and a right N+ layer 92 through a mask technique; Step 3: Form a centered N- layer 10 between the left and right N+ layers 9 by ion implantation, and implant a doped P- layer 15 at the bottom of the centered N- layer 10; Step 4: Inject and form a P-type contact layer 11 in the high convex regions on both sides of the N-substrate 7 to form an ohmic contact with the drain 1; this step can also inject barrier ion bubbles 12 arranged in a right triangle on both sides of the N-drift layer 8, and the hypotenuse faces the N+ layer 9 Step 5: Etch a semi-circular groove on the surface of the N-well layer 5, deposit a metal dielectric layer 21 and directly contact the source 2; Step 6: Grow a gate oxide layer above the trench, deposit polysilicon to form a gate 3, prepare a drain 1 on the back of the device, and prepare a source 2 on the front and connect it to the metal dielectric layer 21 Example 1 As Figure 1 shown, a silicon carbide trench MOSFET device structure based on a heterojunction includes a plurality of juxtaposed MOS cells. A single MOS cell includes a drain 1, a source 2, a gate 3, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N-substrate layer 7, an N-drift layer 8, a P+ layer 4, an N-well layer 5, and a P-well layer 6. A trench is opened on the upper surface of a single MOS cell and below the gate 3, and an N+ layer 9 is deposited inside the trench. The N+ layer 9 includes a left N+ layer 91 and a right N+ layer 92, and a filling medium is formed between the left N+ layer 91 and the right N+ layer 92 by ion implantation; the cross-sectional profile of the N-substrate layer 7 inside a single MOS cell is in a shape that is high and convex on both sides and low and concave in the middle. Contact layers are provided on both sides of the N-substrate layer 7 in a single MOS cell, and the contact layers are in ohmic contact with the drain 1. The filling medium is a centered N- layer 10, and the contact layer is a P-type contact layer 11. Filling the centered N- layer 10 in the trench, that is, injecting a lightly doped N- layer between the left and right N+ layers 9 to form a low-resistance current channel and reduce the channel resistance.

[0021] On the inner wall of the gate trench, separated left / right N+ layers 9 are deposited, and an N- layer 10 is implanted in the middle as a filling medium; at the same time, the N substrate layer 7 is designed as a special-shaped structure with high convexity on both sides and low concavity in the middle, and a P-type contact layer 11 is formed in the convex area to achieve ohmic contact with the drain. Through the N+ / N- hierarchical design in the trench, the carrier mobility is enhanced and the on-resistance is reduced; the special-shaped substrate structure combined with the P-type contact layer optimizes the drain current path, improving the current density and heat dissipation capacity.

[0022] Example 2 As Figure 2 shown, a semi-circular groove is formed on the surface of the N-well layer 5 by etching, and a metal dielectric layer 21 is deposited in the semi-circular groove. The metal dielectric layer 21 is in direct contact with the source electrode 2. An N-well layer 5 surface is etched to form a semi-circular groove and a metal dielectric layer 21 is deposited, making it in direct contact with the source electrode 2.

[0023] This semi-circular groove structure increases the source contact area, and the metal dielectric layer reduces the contact resistance, significantly improving the source carrier injection efficiency and enhancing the device's anti-current impact ability at the same time.

[0024] Example 3 As Figure 3 shown, several blocking ion bubbles 12 are formed by ion implantation on the left and right sides of the N drift layer 8 inside a single MOS cell. The several blocking ion bubbles 12 are arranged in a right triangle, and the hypotenuse side of the right triangle arrangement is close to the N+ layer 9. Blocking ion bubbles 12 arranged in a right triangle are implanted on both sides of the N drift layer 8, with the hypotenuse facing the trench N+ layer 9.

[0025] The geometric arrangement of these ion bubbles forms a directional electric field barrier, effectively suppressing the leakage current and optimizing the breakdown voltage characteristics; the hypotenuse design precisely blocks the electric field at the edge of the drift region, improving the breakdown voltage stability.

[0026] Example 4 As Figure 4 shown, the filling medium is a centered P- layer 14, and the contact layer is an N-type contact layer 13. The trench filling medium is replaced with a centered P- layer 14, and the contact layers on both sides of the N substrate 7 are changed to N-type contact layers 13.

[0027] This P- layer filling achieves carrier concentration gradient regulation, and combined with the N-type contact layer, it forms a bidirectional carrier acceleration channel, significantly reducing the switching loss and being suitable for high-frequency application scenarios.

[0028] Example 5 As Figure 5 shown, a doped P- layer 15 is formed by ion implantation at the inner bottom end of the centered N- layer 10. A doped P- layer 15 is implanted at the bottom of the centered N- layer 10 to form a local PN junction structure.

[0029] The charge compensation effect introduced by the P-layer optimizes the electric field distribution at the bottom of the trench, alleviates the peak electric field problem, improves the long-term reliability and avalanche withstand capacity of the device, and at the same time maintains the low on-resistance characteristic.

[0030] The above-described embodiments merely represent several implementation manners of the present invention. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. A silicon carbide trench MOSFET device structure based on a heterojunction, comprising a plurality of MOS cells arranged side by side. Each MOS cell includes a drain (1), a source (2), a gate (3), and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer (7), an N drift layer (8), a P+ layer (4), an N well layer (5), and a P well layer (6), characterized in that: A groove is formed on the upper surface of a single MOS cell and below the gate (3), and an N+ layer (9) is deposited inside the groove. The N+ layer (9) includes a left N+ layer (91) and a right N+ layer (92), and a filling medium is formed between the left N+ layer (91) and the right N+ layer (92) by ion implantation. The cross-sectional profile of the N substrate layer (7) inside a single MOS cell is in the shape of being high and convex on both sides and low and concave in the middle. Contact layers are provided on both sides of the N substrate layer (7) in a single MOS cell, and the contact layers are in ohmic contact with the drain (1).

2. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 1, characterized in that: The filling medium is a central N- layer (10), and the contact layer is a P-type contact layer (11).

3. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 2, characterized in that: A semi-circular groove is formed on the surface of the N well layer (5) by etching, and a metal dielectric layer (21) is deposited in the semi-circular groove. The metal dielectric layer (21) is in direct contact with the source (2).

4. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 2, characterized in that: A number of blocking ion bubbles (12) are formed by ion implantation on the left and right sides of the N drift layer (8) inside a single MOS cell. The number of blocking ion bubbles (12) is arranged in a right-angled triangle, and the hypotenuse side of the right-angled triangle arrangement is close to the N+ layer (9).

5. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 1, characterized in that: The filling medium is a central P- layer (14), and the contact layer is an N-type contact layer (13).

6. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 2, characterized in that: A doped P- layer (15) is formed by ion implantation at the inner bottom end of the central N- layer (10).

7. A manufacturing process for a silicon carbide trench MOSFET device structure based on a heterojunction, characterized in that, Applied to the heterojunction-based silicon carbide trench MOSFET device structure according to any one of claims 2-6, the preparation process of the heterojunction-based silicon carbide trench MOSFET device structure has the following specific steps: S1. Grow an N drift layer (8) on the N substrate layer (7), and sequentially form a P+ layer (4), an N well layer (5), and a P well layer (6) by ion implantation. S2. Perform trench etching on the upper surface of the cell, deposit an N+ layer (9) on the inner wall of the trench, and separate it into a left N+ layer (91) and a right N+ layer (92) by a masking technique. S3. Form a central N- layer (10) between the left and right N+ layers (9) by ion implantation, and inject a doped P- layer (15) at the bottom of the central N- layer (10). S4. Inject a P-type contact layer (11) in the high-convex regions on both sides of the N substrate (7) to form an ohmic contact with the drain (1). S5. Etch a semi-circular groove on the surface of the N well layer (5), deposit a metal dielectric layer (21) and make it in direct contact with the source (2). S6. Grow a gate oxide layer above the trench, deposit polysilicon to form a gate (3), prepare a drain (1) on the back of the device, and prepare a source (2) on the front and connect it to the metal dielectric layer (21).

8. The manufacturing process of the silicon carbide trench MOSFET device structure based on heterojunction according to claim 7, characterized in that: In the step S4, blocking ion bubbles (12) arranged in a right-angled triangle can be injected on the left and right sides of the N drift layer (8), and the hypotenuse faces the N+ layer (9).

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