Shield gate trench structure manufacturing method for improving polycrystalline silicon residue
By forming a protective layer and an isolation dielectric layer during the polysilicon etching process, the device short-circuit and leakage problems caused by polysilicon residue are solved, channel depth changes are improved, and device performance is improved.
Patent Information
- Application Number
- CN202510392971.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-11
AI Technical Summary
During the polysilicon etching process, the residual polysilicon in the transition region of the oxide layer thickness and the thicker region leads to shorting of the device gate and source, affecting the breakdown voltage and contact hole opening. The prior art causes polysilicon gate at the cell region by increasing the amount of polysilicon etching, affecting the channel length and Nplus connection with the channel.
By forming trenches, field oxide layers and source polysilicon layers on the substrate, grinding to the target thickness, a protective layer and an isolation dielectric layer are formed, and etching to the required height, ensuring that the polysilicon layer is flush, and finally forming a gate oxide layer and a polysilicon layer, the protective layer prevents damage to the mesa structure and improves angle cutting problems.
It effectively improves the leakage problem caused by polysilicon residue, protects the mesa structure, avoids channel depth changes, and improves device performance.
Smart Images
Figure CN120302702A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a shielded gate trench structure for improving polysilicon residue. Background Art
[0002] With the increase in the voltage specification of UDSGT (ultra-deep shielded gate trench) products, the requirement for the thickness of the field oxide layer increases. Under the existing process conditions, the thickness of the oxide layer in the area outside the active region also becomes thicker and thicker, and there is an obvious step difference at the junction between the active region and the non-active region. During the subsequent gate polysilicon etching process, polysilicon residue will be formed in the oxide layer thickness transition region and the position where the oxide layer is too thick; the polysilicon residue in the oxide layer thickness transition region will connect the gate connection region and the source connection region, resulting in a short circuit between the device gate and the source; in addition, the polysilicon residue in the area where the oxide layer is too thick causes the contact hole to not be opened normally, resulting in a decrease in the breakdown voltage.
[0003] Currently, the polysilicon residue in the oxide layer thickness transition region and the area where the oxide layer is too thick in SGT (shielded gate trench) is too thick. Simply increasing the polysilicon etching amount will cause over-etching of the gate polysilicon in the cell region, affecting technical problems such as the channel length and the connection between Nplus (N-type implantation region) and the channel.
[0004] To solve the above problems, a new method for manufacturing a shielded gate trench structure for improving polysilicon residue needs to be proposed. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for manufacturing a shielded gate trench structure for improving polysilicon residue, which is used to solve the problem that the polysilicon residue in the oxide layer thickness transition region and the area where the oxide layer is too thick in SGT (shielded gate trench) in the prior art is too thick, and simply increasing the polysilicon etching amount will cause over-etching of the gate polysilicon in the cell region.
[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing a shielded gate trench structure for improving polysilicon residue, including:
[0007] Step 1: Provide a substrate, the substrate includes an active region and a substrate lead-out region, and form trenches on the active region and the substrate lead-out region on the substrate;
[0008] Step 2: Form a field oxide layer on the surface of the trench and the surface of the substrate, form a source polysilicon layer in the remaining trenches, and then etch the source polysilicon layer to the height of the upper surface of the substrate;
[0009] Step 3: Grind the field oxide layer on the substrate mesa structure to a target thickness;
[0010] Step 4: Form a photoresist layer covering the substrate, open the photoresist layer on the active region by lithography, and then etch the exposed source polysilicon layer to the required height;
[0011] Step 5: Remove the field oxide layer on the sidewalls of the trench and the substrate surface in the active region;
[0012] Step 6: Remove the photoresist layer, form a protective layer on the surfaces of the exposed substrate, the field oxide layer and the source polysilicon layer, and then form an isolation dielectric layer that fills the remaining trench and covers the substrate. The protective layer is used to improve the chamfering effect on the mesa structure during the formation of the isolation dielectric layer;
[0013] Step 7: Etch the isolation dielectric layer so that it only covers or is flush with the source polysilicon layer in the trench in the active region, and at the same time remove the protective layer and the field oxide layer on the substrate mesa structure outside the active region;
[0014] Step 8: Form a gate oxide layer on the surface of the remaining trench in the active region and a gate polysilicon layer that fills the remaining trench.
[0015] Preferably, the method for forming the trench in Step 1 includes: forming a hard mask layer on the substrate; using lithography and etching methods to open the hard mask layer to expose the substrate below to define the formation region of the trench; using dry etching method to etch the exposed substrate to form the trench; removing the remaining hard mask layer.
[0016] Preferably, the substrate in Step 1 is a silicon substrate.
[0017] Preferably, at least one of thermal oxidation process and chemical vapor deposition is used to form the field oxide layer in Step 2.
[0018] Preferably, before grinding the field oxide layer on the substrate mesa structure to the target thickness in Step 3, a line oxide layer is formed on the upper surface of the source polysilicon layer.
[0019] Preferably, the line oxide layer is formed by thermal oxidation process or chemical vapor deposition method in Step 3.
[0020] Preferably, the grinding method in Step 3 is chemical mechanical planarization grinding.
[0021] Preferably, the field oxide layer on the substrate mesa structure is ground to 1000 to 2000 angstroms in Step 3.
[0022] Preferably, before etching the exposed source polysilicon layer to the required height in step four, it further includes removing the line oxide layer on the source polysilicon layer in the active region.
[0023] Preferably, in step four, the line oxide layer on the source polysilicon layer in the active region is removed by wet etching.
[0024] Preferably, in step four, the exposed source polysilicon layer is etched to the required height by dry etching.
[0025] Preferably, in step five, the field oxide layer is removed by wet etching.
[0026] Preferably, the material of the protective layer in step six is an oxide.
[0027] Preferably, the thickness of the protective layer in step six is 500 to 1000 angstroms.
[0028] Preferably, the isolation dielectric layer in step six is an oxide layer prepared by high-density plasma chemical vapor deposition.
[0029] Preferably, the etching method in step seven is wet etching.
[0030] As described above, the method for manufacturing a shielded gate trench structure for improving polysilicon residue of the present invention has the following beneficial effects:
[0031] The protective layer of the present invention, as the protective layer for the silicon above and on both sides of the substrate mesa structure, can ensure that no damage is caused to both sides of the mesa structure during the subsequent formation of the isolation dielectric layer, effectively improving the change in the channel depth caused by chamfering, and then effectively improving the leakage problem caused by the shallowing of the channel depth. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It shows a schematic process flow diagram of the present invention;
[0033] Figure 2 It shows a schematic diagram of forming a field oxide layer of the present invention;
[0034] Figure 3 It shows a schematic diagram of etching the source polysilicon layer of the present invention;
[0035] Figure 4 It shows a schematic diagram of forming a line oxide layer of the present invention;
[0036] Figure 5 It shows a schematic diagram of polishing the field oxide layer of the present invention;
[0037] Figure 6 It shows a schematic diagram of photolithography of the present invention;
[0038] Figure 7 Shown is a schematic diagram of removing the line oxide layer of the present invention;
[0039] Figure 8 Shown is a schematic diagram of etching the source polysilicon layer to the required height of the present invention;
[0040] Figure 9 Shown is a schematic diagram of etching the field oxide layer in the active region of the present invention;
[0041] Figure 10 Shown is a schematic diagram of forming a protective layer of the present invention;
[0042] Figure 11 Shown is a schematic diagram of forming an isolation dielectric layer of the present invention;
[0043] Figure 12 Shown is a schematic diagram of etching the isolation dielectric layer of the present invention;
[0044] Figure 13 Shown is a schematic diagram of forming a gate oxide layer and a gate polysilicon layer of the present invention;
[0045] Figure 14 Shown is a schematic diagram of the topography comparison of the mesa structure with or without the protective layer of the present invention. Detailed implementation manners
[0046] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0047] Please refer to Figure 1 , the present invention provides a method for manufacturing a shielded gate trench structure for improving polysilicon residue, including:
[0048] Step 1: Provide a substrate 101, the substrate 101 includes an active region and a substrate lead-out region, and form trenches on the active region and the substrate lead-out region on the substrate 101;
[0049] In some embodiments, the method for forming trenches in Step 1 includes: forming a hard mask layer on the substrate 101, the hard mask layer generally includes an oxide layer and a nitride layer. For example, the hard mask layer is an ONO layer, which is composed of a top oxide layer, a silicon nitride layer, and a bottom oxide layer stacked in sequence from bottom to top; using photolithography and etching methods to open the hard mask layer to expose the substrate 101 below to define the formation region of the trenches; using dry etching methods to etch the exposed substrate 101 to form trenches; removing the remaining hard mask layer.
[0050] In some embodiments, the substrate 101 in step one is a silicon substrate 101.
[0051] Step two: Form a field oxide layer 102 on the surface of the trench and the surface of the substrate 101 to form a structure as shown in Figure 2 , and form a source polysilicon layer 103 in the remaining trenches. After that, etch the source polysilicon layer 103 to the height of the upper surface of the substrate 101 to form a structure as shown in Figure 3 . The etching method is dry etching or wet etching;
[0052] In some embodiments, in step two, at least one of a thermal oxidation process and a chemical vapor deposition method is used to form the field oxide layer 102.
[0053] Step three: Polish the field oxide layer 102 on the mesa structure of the substrate 101 to a target thickness to form a structure as shown in Figure 5 ;
[0054] In some embodiments, before polishing the field oxide layer 102 on the mesa structure of the substrate 101 to the target thickness in step three, a line oxide layer 104 is further formed on the upper surface of the source polysilicon layer 103 to form a structure as shown in Figure 4 .
[0055] In some embodiments, in step three, the line oxide layer 104 is formed by a thermal oxidation process or a chemical vapor deposition method. By using the thermal oxidation process, the exposed source polysilicon surface can be oxidized to form the line oxide layer 104. By using the chemical vapor deposition method, a line oxide layer 104 can be formed on the surface of the substrate 101, which can solve the problem of mismatched grinding pollution properties.
[0056] In some embodiments, the polishing method in step three is chemical mechanical planarization polishing.
[0057] In some embodiments, in step three, the field oxide layer 102 on the mesa structure of the substrate 101 is polished to 1000 to 2000 angstroms.
[0058] Step four: Form a photoresist layer 105 covering the substrate 101, and open the photoresist layer 105 on the active region by lithography to form a structure as shown in Figure 6 , and then etch the exposed source polysilicon layer 103 to the required height to form a structure as shown in Figure 8 ;
[0059] In some embodiments, before etching the exposed source polysilicon layer 103 to the required height in step four, the line oxide layer 104 on the source polysilicon layer 103 in the active region is further removed.
[0060] In some embodiments, in step four, a wet etching method is used to remove the line oxide layer 104 on the source polysilicon layer 103 in the active region.
[0061] In some embodiments, in step four, a dry etching method is used to etch the exposed source polysilicon layer 103 to the required height.
[0062] Step five: Remove the field oxide layer 102 on the sidewalls of the trench and the surface of the substrate 101 in the active region to form a structure as shown in Figure 9 which can widen the filling window of the subsequent isolation dielectric layer 107;
[0063] In some embodiments, in step five, a wet etching method is used to remove the field oxide layer 102.
[0064] Step six: Remove the photoresist layer 105 and form a protective layer 106 on the surfaces of the exposed substrate 101, field oxide layer 102, and source polysilicon layer 103 to form a structure as shown in Figure 10 After that, an isolation dielectric layer 107 that fills the remaining trench and covers the substrate 101 is formed to form a structure as shown in Figure 11 The protective layer 106 is used to improve the chamfering effect on the mesa structure during the formation of the isolation dielectric layer 107, which can effectively improve the change in the channel depth caused by chamfering, and then effectively improve the leakage problem caused by the shallowing of the channel depth;
[0065] In some embodiments, the material of the protective layer 106 in step six is an oxide.
[0066] In some embodiments, the thickness of the protective layer 106 in step six is 500 to 1000 angstroms.
[0067] In some embodiments, the isolation dielectric layer 107 is an oxide layer prepared by high-density plasma (HDP) chemical vapor deposition. The protective layer 106 can protect both sides of the top of the mesa structure from damage by high-density plasma, and at the same time ensure the quality of the filling of the high-density plasma chemical vapor deposition oxide layer.
[0068] Step seven: Etch the isolation dielectric layer 107 so that it only covers the source polysilicon layer 103 in the trench in the active region or is flush with the source polysilicon layer 103 therein. At the same time, remove the oxide layer on the mesa structure of the substrate 101 outside the active region, such as the protective layer 106 and the field oxide layer 102 (if the line oxide layer 104 is formed in the previous step, it can also be removed in this step) to form a structure as shown in Figure 12 Please refer to Figure 14 which shows the morphological comparison diagram of the mesa structure with and without the protection of the protective layer. It can be seen that the mesa structure of the present invention improves the chamfering effect;
[0069] In some embodiments, the etching method in Step Seven is wet etching.
[0070] Step Eight: Form a gate oxide layer 108 on the surface of the remaining trenches in the active region and a gate polysilicon layer 109 to fill the remaining trenches, forming a structure as Figure 13 shown. Both the gate oxide layer 108 and the gate polysilicon layer 109 can be formed by chemical vapor deposition.
[0071] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0072] In summary, as a protective layer for the silicon above and on both sides of the substrate mesa structure, the protective layer of the present invention can ensure that no damage is caused to both sides of the mesa structure during the subsequent formation of the isolation dielectric layer, effectively improving the change in channel depth caused by chamfering, and then effectively improving the leakage problem caused by the shallowing of the channel depth. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0073] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A manufacturing method of a shield gate trench structure for improving polysilicon residue, characterized in that, At least including: Step 1: Provide a substrate, on which there are an active region and a substrate lead-out region, and form trenches on the active region and the substrate lead-out region on the substrate; Step 2: Form a field oxide layer on the surface of the trenches and the substrate surface, form a source polysilicon layer in the remaining trenches, and then etch the source polysilicon layer to the height of the upper surface of the substrate; Step 3: Polish the field oxide layer on the substrate mesa structure to a target thickness; Step 4: Form a photoresist layer covering the substrate, lithographically open the photoresist layer on the active region, and then etch the exposed source polysilicon layer to a required height; Step 5: Remove the field oxide layer on the sidewalls of the trenches and the substrate surface in the active region; Step 6: Remove the photoresist layer, form a protective layer on the surfaces of the exposed substrate, the field oxide layer, and the source polysilicon layer, and then form an isolation dielectric layer filling the remaining trenches and covering the substrate. The protective layer is used to improve the chamfering effect on the mesa structure during the formation of the isolation dielectric layer; Step 7: Etch the isolation dielectric layer so that it only covers the source polysilicon layer in the trenches in the active region or is flush with the source polysilicon layer therein, and at the same time remove the protective layer and the field oxide layer on the substrate mesa structure outside the active region; Step 8: Form a gate oxide layer on the surface of the remaining trenches in the active region and a gate polysilicon layer filling the remaining trenches.
2. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The method for forming the trenches in Step 1 includes: forming a hard mask layer on the substrate; using photolithography and etching methods to open the hard mask layer to expose the substrate below to define the formation region of the trenches; using dry etching methods to etch the exposed substrate to form the trenches; removing the remaining hard mask layer.
3. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The substrate in Step 1 is a silicon substrate.
4. The method for manufacturing a shielded gate trench structure for improving polysilicon residue according to claim 1, wherein: In Step 2, the field oxide layer is formed by at least one of thermal oxidation process and chemical vapor deposition.
5. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: Before polishing the field oxide layer on the substrate mesa structure to a target thickness in Step 3, it also includes forming a line oxide layer on the upper surface of the source polysilicon layer.
6. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 5, wherein: In Step 3, the line oxide layer is formed by thermal oxidation process or chemical vapor deposition.
7. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The polishing method in Step 3 is chemical mechanical planarization polishing.
8. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: In Step 3, the field oxide layer on the substrate mesa structure is polished to 1000 to 2000 angstroms.
9. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 6, wherein: Before etching the exposed source polysilicon layer to a required height in Step 4, it also includes removing the line oxide layer on the source polysilicon layer in the active region.
10. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: In Step 4, the line oxide layer on the source polysilicon layer in the active region is removed by wet etching.
11. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: In Step 4, the exposed source polysilicon layer is etched to a required height by dry etching.
12. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: In Step 5, the field oxide layer is removed by wet etching.
13. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, characterized in that: The material of the protective layer in Step 6 is oxide.
14. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The thickness of the protective layer in Step 6 is 500 to 1000 angstroms.
15. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The isolation dielectric layer in Step 6 is an oxide layer prepared by high-density plasma chemical vapor deposition.
16. The method for manufacturing a shield gate trench structure for improving polysilicon residue according to claim 1, wherein: The etching method in Step 7 is wet etching.