Enhanced end-to-end system failure recovery

Abstract

To ensure data validity of data read from a memory device of a data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of decoded data and compare the CRC signature of the decoded data to a CRC signature of the data. The CRC signature for the data is generated during a write operation of the data to the memory device. When the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes a read command again rather than returning an uncorrectable error correction code error (UECC) error to the host device. By using different buffers to store the decoded data, the controller may confirm whether the error originates from the read path or the error is not from the read path.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire content of U.S. Non - provisional Application No. 18 / 219,815, entitled "Enhanced End ToEnd System Failure Recovery", filed on July 10, 2023, with the United States Patent and Trademark Office, and incorporates its entire content by reference herein for all purposes. Background Art Field of the Invention

[0003] Embodiments of the present disclosure generally relate to data storage devices, such as solid - state drives (SSDs), and more particularly to improving end - to - end data protection.

[0004] Description of the Related Art

[0005] Data storage devices employ different data protection mechanisms to ensure data integrity. In other words, data protection mechanisms are utilized to protect data being returned to the host device from integrity errors. One type of data protection mechanism is block - level exclusive - or (XOR) protection, which can be used with data that is expected to have a very low uncorrectable bit error rate (UBER). To further ensure end - to - end protection of data, a data storage device can compute a flash management unit (FMU) cyclic redundancy code (CRC) signature for host data stored in the data storage device.

[0006] When reading data stored in a data storage device, the FMU CRC signature is checked against the computed FMU CRC signature calculated during the read operation in order to detect any possible bit errors that the data may have accumulated during the read operation. When the FMU CRC signature does not match the computed FMU CRC signature, even when the raw data read from the data storage device is valid, an uncorrectable error - correcting code (UECC) error is returned to the host device without realizing the full error - correcting code (ECC) decoding potential of the data storage device. In other words, the error point during the read operation can be localized to a part of the data path of the read operation.

[0007] Accordingly, there is a need in the art for an improved read operation to improve end - to - end protection of data. Summary of the Invention

[0008] The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and more particularly to improving end-to-end data protection. To ensure the data validity of data read from a memory device of a data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of decoded data and compare the CRC signature of the decoded data with the CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. When the CRC signature of the decoded data does not match the CRC signature of the data, the controller re-executes the read command instead of returning an uncorrectable error correction code (UECC) error to the host device. By using different buffers to store the decoded data, the controller can confirm whether the error originates from the read path or the error does not come from the read path.

[0009] In one embodiment, a data storage device includes a non-volatile memory device, a first volatile memory device, a second volatile memory device, and a controller coupled to the non-volatile memory device, the first volatile memory device, and the second volatile memory device. The controller is configured to receive a read command from a host device; read data from the non-volatile memory device; decode the data read from the non-volatile memory device; store the decoded data in the first volatile memory device; calculate a second cyclic redundancy code (CRC) signature of the stored decoded data; determine that the second CRC signature does not match a first CRC signature of the data, wherein the first CRC is generated and appended to the data when the data is programmed to the non-volatile memory device; and do any of the following: reissue the read command to reread the data from the non-volatile memory device, wherein the read command includes instructions for using the second volatile memory device to store the re-decoded data; or store the decoded data in the second volatile memory device.

[0010] In another embodiment, a data storage device includes a non-volatile memory device, a first volatile memory device, a second volatile memory device, where the first volatile memory device and the second volatile memory device are different, and a controller coupled to the non-volatile memory device, the first volatile memory device, and the second volatile memory device. The controller is configured to: determine that data read during a read operation has a cyclic redundancy code (CRC) signature that does not match a CRC signature calculated for the read operation, where the data associated with the read operation is stored in the first volatile memory; initiate a modified read operation, where the modified read operation uses the second volatile memory to store the data associated with the modified read operation; determine whether the CRC signature of the data matches a CRC signature calculated for the modified read operation; and when the CRC signature matches the CRC signature calculated for the modified read operation, return the data associated with the modified read operation to the requester of the data.

[0011] In another embodiment, a data storage device includes: means for storing non-volatile data; means for storing first volatile data; means for storing second volatile data; and a controller coupled to the means for storing non-volatile data, the means for storing first volatile data, and the means for storing second volatile data. The controller is configured to: receive a read command to read data from the means for storing non-volatile data, transfer the data from the means for storing non-volatile data to an error correction code (ECC) engine for decoding, decode the data, store the decoded data in the means for storing first volatile data, determine that a cyclic redundancy code (CRC) signature of the data does not match a CRC signature calculated for the decoded data, and reissue the read command as a modified read command, where the modified read command uses the means for storing second volatile data instead of the means for storing first volatile data to store the decoded data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To understand the above features of the present disclosure in detail, the present disclosure briefly summarized above may be described in more detail by reference to embodiments, some of which are illustrated in the drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, as the present disclosure may admit other equivalent embodiments.

[0013] Figure 1 is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device of a host device according to certain embodiments.

[0014] Figure 2 is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device of a host device according to some embodiments.

[0015] Figure 3A is a flowchart illustrating a method of programming data into a non-volatile memory (NVM) of a data storage device according to some embodiments.

[0016] Figure 3B is a flowchart illustrating a method of reading data from an NVM of a data storage device according to some embodiments.

[0017] Figure 4 is a flowchart illustrating a method of reading data from an NVM of a data storage device according to some embodiments.

[0018] Figure 5 is a schematic block diagram illustrating a storage system according to some embodiments, in which a controller is configured to allocate different volatile memory buffers for reissued read commands.

[0019] Figure 6 is a flowchart illustrating a method of reading data from an NVM of a data storage device according to some embodiments.

[0020] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Detailed Description

[0021] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements, whether or not they relate to different embodiments, is contemplated for implementing and practicing the present disclosure. Moreover, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly recited therein. Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly recited therein.

[0022] The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and more particularly to improved end-to-end data protection. To ensure the data validity of data read from a memory device of a data storage device to a host device, a controller of the data storage device may compute a cyclic redundancy code (CRC) signature of decoded data and compare the CRC signature of the decoded data with the CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. When the CRC signature of the decoded data does not match the CRC signature of the data, the controller re-executes the read command instead of returning an uncorrectable error correction code (UECC) error to the host device. By using different buffers to store the decoded data, the controller can confirm whether the error originates from the read path or the error does not come from the read path.

[0023] Figure 1 FIG. 1 is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104, according to some embodiments. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host DRAM 138. In some examples, the storage system 100 may include multiple storage devices that can operate as a storage array, such as the data storage device 106. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID), which together serve as a mass storage device for the host device 104.

[0024] The host device 104 may store data to and / or retrieve data from one or more storage devices, such as the data storage device 106. As Figure 1 illustrated, the host device 104 may communicate with the data storage device 106 via an interface 114. The host device 104 may include any of a wide range of devices, including: computer servers, network attached storage (NAS) units, desktop computers, notebooks (i.e., laptops) computers, tablet computers, set-top boxes, telephone handsets (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from a data storage device.

[0025] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated for exclusive use by the controller 108 of the data storage device 106 for data storage. For example, the controller 108 may store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would typically be stored in volatile memory 112, buffer 116, the internal memory of the controller 108 such as static random access memory (SRAM), etc. In an example where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.

[0026] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components, which are not shown for clarity in Figure 1 Additional components are shown. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDD or SSD), 2.5-inch data storage devices, 1.8-inch data storage devices, Peripheral Component Interconnect (PCI), Extended PCI (PCI-X), Express PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini card, mini PCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of the host device 104.

[0027] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface eXtension (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to controller 108, providing an electrical connection between host device 104 and controller 108, enabling data to be exchanged between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 illustrated, power supply 111 may receive power from host device 104 via interface 114.

[0028] NVM 110 may include a plurality of memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, the memory cells of NVM 110 may receive data and a message indicating that the memory cell stores the data from controller 108. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each memory cell in the memory cells may be referred to as a die. In some examples, NVM 110 may include a plurality of dies (i.e., a plurality of memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0029] In some examples, each memory cell may include any type of non-volatile memory device such as: flash memory devices, phase change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory device.

[0030] The NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory devices may include NAND- or NOR-based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In the NVM flash memory devices, the flash memory devices may be divided into multiple dies, where each of the multiple dies includes multiple physical blocks or logical blocks, and the multiple physical blocks or logical blocks may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of the NVM cells may be electrically connected using word lines to define the pages among the multiple pages. The corresponding cells in each of the multiple pages may be electrically connected to corresponding bit lines. In addition, the NVM flash memory devices may be 2D or 3D devices, and may be single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). It should be understood that the listed memory architectures are not intended to be limiting, but rather provide examples of possible implementations. For example, it is envisioned that higher-level cell memories may be applicable, such as five-level cell (PLC) memories, etc. (e.g., six-level cells, seven-level cells, etc.). The controller 108 may write data to and read data from the NVM flash memory device at the page level, and erase data from the NVM flash memory device at the block level.

[0031] The power supply 111 may supply power to one or more components of the data storage device 106. When operating in the standard mode, the power supply 111 may use the power provided by an external device such as the host device 104 to supply power to one or a component. For example, the power supply 111 may use the power received from the host device 104 via the interface 114 to supply power to one or more components. In some examples, the power supply 111 may include one or more power storage components configured to supply power to one or more components when operating in the off mode, such as in the case of stopping receiving power from an external device. In this way, the power supply 111 can be used as an on-vehicle backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electric power that can be stored by the one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of electric power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0032] The controller 108 may use the volatile memory 112 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 may use the volatile memory 112 as a cache. For example, the controller 108 may store the information in the cache in the volatile memory 112 before the information in the cache is written to the NVM 110. As Figure 1 illustrated, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include but are not limited to random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)), pseudo SRAM (PSRAM), block RAM (BRAM), thyristor RAM (TRAM), accelerator RAM (XRAM), etc. Similarly, the optional DRAM 118 may be used to store mapped data, buffered commands, logical to physical (L2P) tables, metadata, cached data, etc. in the optional DRAM 118. In some examples, the data storage device 106 does not include the optional DRAM 118, such that the data storage device 106 is DRAM-less. In other examples, the data storage device 106 includes the optional DRAM 118.

[0033] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command to store the data to the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data in an internal memory or a write buffer 116 before sending the data associated with the write command to the NVM 110.

[0034] The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to the volatile memory 112. For example, the optional second volatile memory 120 may be SRAM. The controller 108 may allocate a portion of the optional second volatile memory 120 to the host device 104 as a controller memory buffer (CMB) 122. The CMB 122 may be directly accessible by the host device 104. For example, the host device 104 may utilize the CMB 122 to store one or more submission queues that are typically maintained in the host device 104, rather than maintaining the one or more submission queues in the host device 104. In other words, the host device 104 may generate commands and store the generated commands with or without associated data in the CMB 122, where the controller 108 accesses the CMB 122 to retrieve the stored generated commands and / or associated data. It should be understood that either or both of the controller 108 and the data storage device may have other volatile memories in addition to the volatile memory 112 and the optional second volatile memory 120.

[0035] Figure 2 is a schematic block diagram illustrating a storage system 200 according to certain embodiments, where the data storage device 204 may be used as a storage device for the host device 202. It should be understood that the storage system 200 may be similar to Figure 1 the storage system 100.

[0036] The host device 202 is coupled to the data storage device 204. The data storage device includes a controller 206 and NVM 220. In some examples, the data storage device 204 may include additional components, which are not shown for clarity Figure 2 in. The controller 206 includes a host interface module (HIM) 208 coupled to the host device 202, a control path 210 coupled to the HIM 208, a data path 212 coupled to the HIM 208 and the control path 210, and a flash interface module (FIM) 218 coupled to the control path 210, the data path 212, and the NVM 220. Data and commands are transferred from the host device 202 to the data storage device 204 via the HIM 208, and data is transferred from the data storage device 204 to the host device 202 via the HIM 208. The HIM 208 may operate under any applicable protocol such as PCIe, NVMe, etc.

[0037] When the controller 206 receives a command and associated data at the HIM 208, the command is provided from the HIM 208 to the control path 210, and the data is provided from the HIM 208 to the data path 212. The control path 210 may include one or more components configured to perform one or more of processing commands, generating additional commands based on the received commands, initiating control processes, etc. The data path 212 includes an Error Correction Code (ECC) engine 216. The ECC engine 216 may be an encoder / decoder unit. The ECC engine 216 is configured to generate ECC data, append the generated ECC data to the relevant data, and encode the data including the appended generated ECC data. In addition, the ECC engine 216 is configured to decode the encoded data and check / correct any errors in the decoded data (which may use methods such as Reed-Solomon error correction, Single Error Correction / Double Error Detection (SECDED) codes, etc.). The encoded data, together with the instructions generated from the control path 210, is provided to the FIM 218. The FIM 218 is configured to access the NVM 220 to read data from the NVM 220 and program data into the NVM 220.

[0038] When data is received at the HIM 208, the HIM 208 may be configured to generate a Cyclic Redundancy Code (CRC) signature for the received data, which may be for each 4KB (i.e., flash management unit) data block. The CRC signature is then checked before encoding the data to be programmed into the NVM 220. Similarly, when data is read from the NVM 220, the data is decoded by the ECC engine 216. The ECC engine 216 verifies the CRC signature of the decoded data against the calculated CRC signature, which may be calculated after decoding the data. When a mismatch occurs (i.e., the CRC signature does not match the calculated CRC signature), the controller 206 returns an Uncorrectable Error Correction Code (UECC) error to the host device 202. In other words, a read failure is reported to the host device 202.

[0039] Figure 3A is an illustration of a method 300 for programming data into a non-volatile memory (NVM) of a data storage device (such as Figure 1 data storage device 106 or Figure 2 data storage device 204) according to certain embodiments. The method 300 may be implemented by a controller (such as Figure 1 controller 108 or Figure 2 controller 206). For illustrative purposes, reference may be made herein to Figure 1 controller 108 or Figure 2 controller 206). For illustrative purposes, reference may be made herein to Figure 1the storage system 100 and Figure 2 aspects of the storage system 200.

[0040] At block 302, the controller 206 receives data to be programmed into the NVM 220 from the host device 202. At block 304, the HIM 208 generates a CRC signature for each flash memory management unit (FMU) of the received data. At block 308, an ECC encoder (which may be the ECC engine 216) checks whether the generated CRC signature matches the FMU CRC signature in the ECC encoder. If, at block 306, the generated CRC signature does not match the FMU CRC signature in the ECC encoder, then at block 310, a read failure indication is programmed into the FMU header of the data. However, if, at block 306, the generated CRC signature matches the FMU CRC signature in the ECC encoder, or after the read failure indication is programmed into the FMU header at block 310, the ECC encoder encodes the data and the controller 206 programs the data into the NVM 220.

[0041] Figure 3B is an illustration of a method 350 for reading data from a non-volatile memory (NVM) of a data storage device (such as Figure 1 the data storage device 106 or Figure 2 the data storage device 204) such as Figure 1 the NVM 110 or Figure 2 the NVM 220) according to some embodiments. The method 350 may be implemented by a controller (such as Figure 1 the controller 108 or Figure 2 the controller 206). For illustrative purposes, aspects of the Figure 1 storage system 100 and Figure 2 the storage system 200 may be referred to herein.

[0042] At block 352, the controller 206 receives a read command to read data from the NVM 220. At block 354, relevant data including ECC is decoded by an ECC decoder, which may be the ECC engine 216. At block 356, the HIM 208 determines whether the FMU CRC signature in the ECC decoder matches the calculated CRC signature of the data. In other words, the HIM 208 determines whether the CRC signature stored with the data matches the CRC signature calculated after decoding the data. If the CRC signature does not match at block 356, then the controller 206 returns a UECC error to the host device 202 at block 360. However, if the CRC signature matches at block 356, then the decoded data is returned to the host device 202 at block 358.

[0043] Figure 4Illustrates a method 400 for reading data from a non-volatile memory (NVM) of a data storage device (such as Figure 1 data storage device 106 or Figure 2 data storage device 204) of Figure 1 NVM 110 of Figure 2 or NVM 220 of Figure 1 controller 108 of Figure 2 or controller 206 of Figure 1 For purposes of illustration, aspects of storage system 100 of Figure 2 and storage system 200 of

[0044] At block 402, controller 206 receives a read request from host device 202 to read data from NVM 220. At block 404, ECC engine 216 decodes the ECC associated with the data read from NVM 220. After decoding the data, the data is buffered in a volatile memory device, such as optional second volatile memory 120. At block 406, HIM 208 determines whether the FMUCRC signature in the ECC decoder matches the calculated CRC signature of the data. In other words, HIM 208 determines whether the CRC signature stored with the data matches the CRC signature calculated after decoding the data. If the CRC signatures do not match at block 406, then controller 206 issues a critical warning status to host device 202 at block 410. The critical warning status indicates that host device 202 reset data storage device 204 and resend the read command, or utilize a different volatile memory device in a subsequently resent read command, because the decoded data may have been corrupted. For example, the volatile memory device utilized may be SRAM, and the different volatile memory device utilized may be DRAM, XRAM, BRAM, TRAM, etc. At block 412, controller 206 resends the read command using a read recovery configuration (i.e., utilizing a different volatile memory device). It is contemplated that when the CRC signature does not match after the data is extracted to another different volatile memory device, the different volatile memory device may be read again (e.g., there are three or more volatile memory devices in data storage device 204). However, if the CRC signatures match at block 406, then the decoded data is returned to host device 202 at block 408.

[0045] Figure 5 Illustrates a schematic block diagram of a storage system 500 according to certain embodiments, where controller 506 is configured to allocate different volatile memory buffers for a resent read command. For purposes of illustration, aspects ofFigure 1 storage system 100 and Figure 2 aspects of storage system 200.

[0046] The controller 506 includes a Command Automation Processor (CAP) 508 that is configured to accommodate options that specify different volatile memory device allocations for a current read command. For example, if a current read command has returned a UECC error, then when the same read command is reissued subsequently, the CAP 508 can be configured to allocate a different volatile memory device for the reissued read command, where the different volatile memory device is different from the volatile memory device used for the current read command.

[0047] The host device 502 generates a read command 504 and sends the read command to the controller 506. In some examples, the controller 506 may extract the read command 504 from the host device 502. The read command 504 is provided to the CAP 508, where at block 510, the CAP 508 allocates a corresponding volatile memory device for the decoded data associated with the read command 504. If the read command is an original read command (i.e., not a reissued read command), then at block 510, the CAP 508 allocates the primary volatile memory device (e.g., SRAM) that is typically used to store the decoded data. Otherwise, if the read command is not an original read command (i.e., a reissued read command), then at block 510, the CAP 508 allocates a secondary volatile memory device (e.g., DRAM, XRAM, TRAM, BRAM, etc.) to store the decoded data. At block 512, the controller 506 reads data from the NVM 220, decodes the data read from the NVM 220, and places the decoded data in the allocated buffer allocated at block 510. At block 514, the CRC matching logic of the controller 506 determines whether the CRC signature of the data matches the calculated CRC signature of the decoded data. If the CRC signatures match, the data is provided back to the host device 502. However, if the CRC signatures do not match, the controller 506 is configured to issue a severe warning status to the host device 502 at block 516, and / or modify the read command at block 518 to use a secondary volatile memory device.

[0048] Figure 6 illustrates a method 600 for reading data from a non-volatile memory (NVM) (such as Figure 1 the NVM 110 of data storage device 106 or Figure 2 the NVM 220 of data storage device 204) of a data storage device (such as Figure 1 the NVM 110 of Figure 2 a controller (such as Figure 1controller 108 or Figure 2 controller 206). For illustrative purposes, reference may be made herein to Figure 1 storage system 100, Figure 2 storage system 200, and / or Figure 5 aspects of storage system 500.

[0049] At block 602, controller 206 receives a read request from host device 202 to read data from NVM 220. At block 604, ECC engine 216 decodes the ECC associated with the data read from NVM 220. After the data is decoded, the data is buffered in a volatile memory device, such as optional second volatile memory 120. At block 606, HIM 208 determines whether the FMUCRC signature in the ECC decoder matches the calculated CRC signature of the data. In other words, HIM 208 determines whether the CRC signature stored with the data matches the CRC signature calculated after the data is decoded. If the CRC signatures do not match at block 606, controller 206 determines at block 610 whether the decoded data is still in the internal memory of ECC engine 216. ECC engine 216 may include a certain amount of volatile memory sufficient to store the data being decoded / encoded.

[0050] If the decoded data is still in the internal memory of the ECC engine 216, at block 614, the decoded data can be retrieved from the ECC engine 216 again into a different volatile memory device that is different from the original volatile memory device. For example, the original volatile memory device utilized can be SRAM, and the different volatile memory device utilized can be DRAM, XRAM, BRAM, TRAM, etc. It is contemplated that when it is determined that the CRC signature does not match after retrieving the data into another different volatile memory device (e.g., there are three or more volatile memory devices in the data storage device 204), the different volatile memory device can be retrieved again. After retrieving the data from the ECC engine 216 again into a different volatile memory device, the HIM 208 determines at block 606 whether the FMU CRC signature in the ECC decoder matches the calculated CRC signature of the data stored in the different volatile memory. If the decoded data is not in the internal memory of the ECC engine at block 610, the controller 206 reissues the command at 612 using a read recovery configuration (i.e., using a different volatile memory device). It should be understood that if the CRC signature of the data stored in the different volatile memory does not match the CRC signature of the decoded data (generated by the ECC encoder of the ECC engine 216 when the data was encoded), the controller 206 can report a UECC error to the host device 202. If the CRC signature matches at block 606, the data is returned to the host device 202 at 608.

[0051] By storing the decoded data read from the memory device of the data storage device in a different buffer in response to a mismatch between the CRC signature of the decoded data and the CRC signature of the data, error accumulation due to the read path can be avoided, thereby reducing read failures of the data storage device.

[0052] In one embodiment, a data storage device includes a non-volatile memory device, a first volatile memory device, a second volatile memory device, and a controller coupled to the non-volatile memory device, the first volatile memory device, and the second volatile memory device. The controller is configured to receive a read command from a host device; read data from the non-volatile memory device; decode the data read from the non-volatile memory device; store the decoded data in the first volatile memory device; calculate a second cyclic redundancy code (CRC) signature of the stored decoded data; determine that the second CRC signature does not match a first CRC signature of the data, wherein the first CRC was generated and appended to the data when the data was programmed to the non-volatile memory device; and perform any one of the following: reissue the read command to reread the data from the non-volatile memory device, wherein the read command includes instructions to store the reread decoded data using the second volatile memory device; or store the decoded data in the second volatile memory device.

[0053] The first volatile memory device is different from the second volatile memory device. The controller is further configured to issue a critical warning status to the host device in response to determining that the second CRC signature does not match the first CRC signature. The critical warning status indicates that the host device resets the data storage device or utilizes the second volatile memory device in a reissued read command. The controller is further configured to return the decoded data to the host device when the second CRC signature matches the first CRC signature of the data. The controller is further configured to, in response to a reissued read command, reread data from the memory device, re-decode the reread data from the memory device, store the re-decoded data in the second volatile memory device, calculate a third CRC signature of the stored re-decoded data, and determine whether the third CRC signature matches the first CRC signature of the data. The controller is further configured to return the re-decoded data to the host device in response to determining that the third CRC signature matches the first CRC signature of the data. The controller is further configured to return an uncorrectable error correction code (UECC) error to the host device in response to determining that the third CRC signature does not match the first CRC signature of the data. The controller is further configured to, in response to storing the decoded data in the second volatile memory device, calculate a third CRC signature of the decoded data stored in the second volatile memory device, and determine whether the third CRC signature matches the first CRC signature of the data. The controller is further configured to return the decoded data from the second volatile memory device to the host device in response to determining that the third CRC signature matches the first CRC signature of the data. The controller is further configured to return an uncorrectable error correction code (UECC) error to the host device in response to determining that the third CRC signature does not match the first CRC signature of the data.

[0054] In another embodiment, a data storage device includes a non-volatile memory device, a first volatile memory device, a second volatile memory device, where the first volatile memory device and the second volatile memory device are different, and a controller coupled to the non-volatile memory device, the first volatile memory device, and the second volatile memory device. The controller is configured to: determine that data read during a read operation has a cyclic redundancy code (CRC) signature that does not match a CRC signature calculated for the read operation, where the data associated with the read operation is stored in the first volatile memory; initiate a modified read operation, where the modified read operation uses the second volatile memory to store the data associated with the modified read operation; determine whether the CRC signature of the data matches a CRC signature calculated for the modified read operation; and when the CRC signature matches the CRC signature calculated for the modified read operation, return the data associated with the modified read operation to the requester of the data.

[0055] The read operation includes transferring data from the internal memory of an error correction code (ECC) engine used to decode the data to the first volatile memory device. The modified read operation includes transferring data from the internal memory of the ECC engine used to decode the data to the second volatile memory device. In response to determining that the data is present in the ECC engine, the data is transferred from the internal memory of the ECC engine used to decode the data to the second volatile memory device. In response to determining that the data is not present in the ECC engine, the modified read operation includes rereading the data from the memory device, decoding the data using the ECC engine, and transferring the data to the second volatile memory device. In response to determining that the CRC signature of the data does not match the CRC signature calculated for the read operation, the controller is further configured to issue a critical warning status to the requester, where the critical warning status indicates that the requester perform a reset of the data storage device, where the read operation is re-executed upon reset of the data storage device, or the command corresponding to the modified read operation is reissued. The controller is further configured not to send an uncorrectable error correction code (UECC) error to the requester when the CRC signature of the data does not match the CRC signature calculated for the read operation. The controller is further configured to send a UECC error to the requester when the CRC signature of the data does not match the CRC signature calculated for the modified read operation.

[0056] In another embodiment, a data storage device includes: means for storing non-volatile data; means for storing first volatile data; means for storing second volatile data; and a controller coupled to the means for storing non-volatile data, the means for storing first volatile data, and the means for storing second volatile data. The controller is configured to: receive a read command to read data from the means for storing non-volatile data, transfer the data from the means for storing non-volatile data to an error correction code (ECC) engine for decoding, decode the data, store the decoded data in the means for storing first volatile data, determine that a cyclic redundancy code (CRC) signature of the data does not match a computed CRC signature of the decoded data, and reissue the read command as a modified read command, wherein the modified read command stores the decoded data using the means for storing second volatile data instead of the means for storing first volatile data. The controller includes a command automation processor (CAP). The CAP is configured to specify the use of the means for storing second volatile data for the modified read command.

[0057] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: A non - volatile memory device; A first volatile memory device; A second volatile memory device; And A controller, the controller being coupled to the memory device, the first volatile memory device, and the second volatile memory device, wherein the controller is configured to: Receive a read command from a host device; Read data from the non - volatile memory device; Decode the data read from the non - volatile memory device; Store the decoded data in the first volatile memory device; Calculate a second cyclic redundancy check (CRC) signature of the stored decoded data; Determine that the second CRC signature does not match a first CRC signature of the data, wherein the first CRC is generated and appended to the data when the data is programmed into the non - volatile memory device; And Perform any of the following: Re - issue the read command to re - read the data from the non - volatile memory device, wherein the read command includes instructions for using the second volatile memory device to store the re - decoded data; Or Store the decoded data in the second volatile memory device.

2. The data storage device according to claim 1, wherein the first volatile memory device is different from the second volatile memory device.

3. The data storage device according to claim 1, wherein the controller is further configured to issue a critical warning status to the host device in response to determining that the second CRC signature does not match the first CRC signature.

4. The data storage device according to claim 3, wherein the critical warning status instructs the host device to: Reset the data storage device; or Use the second volatile memory device in a re - issued read command.

5. The data storage device according to claim 1, wherein the controller is further configured to return the decoded data to the host device when the second CRC signature matches the first CRC signature of the data.

6. The data storage device according to claim 1, wherein the controller is further configured in response to re - issuing the read command: Re - read the data from the non - volatile memory device; Re - decode the data re - read from the non - volatile memory device; Store the re - decoded data in the second volatile memory device; Calculate a third CRC signature of the stored re - decoded data; And Determine whether the third CRC signature matches the first CRC signature of the data.

7. The data storage device according to claim 6, wherein the controller is further configured to: Return the re - decoded data to the host device in response to determining that the third CRC signature matches the first CRC signature of the data.

8. The data storage device according to claim 6, wherein the controller is further configured to: In response to determining that the third CRC signature does not match the first CRC signature of the data, an uncorrectable error correction code (UECC) error is returned to the host device.

9. The data storage device according to claim 1, wherein the controller is further configured to, in response to storing the decoded data in the second volatile memory device: calculate a third CRC signature of the decoded data stored in the second volatile memory device; and determine whether the third CRC signature matches the first CRC signature of the data.

10. The data storage device according to claim 9, wherein the controller is further configured to: in response to determining that the third CRC signature matches the first CRC signature of the data, return the decoded data from the second volatile memory device to the host device.

11. The data storage device according to claim 9, wherein the controller is further configured to: in response to determining that the third CRC signature does not match the first CRC signature of the data, return an uncorrectable error correction code (UECC) error to the host device.

12. A data storage device, the data storage device comprising: a non-volatile memory device; a first volatile memory device; a second volatile memory device, wherein the first volatile memory device and the second volatile memory device are different; and a controller coupled to the non-volatile memory device, the first volatile memory device, and the second volatile memory device, wherein the controller is configured to: determine that data read during a read operation has a CRC signature that does not match a calculated cyclic redundancy code (CRC) signature associated with the read operation, wherein the data associated with the read operation is stored in the first volatile memory; initiate a modified read operation, wherein the modified read operation utilizes the second volatile memory to store data associated with the modified read operation; determine whether the CRC signature of the data matches a calculated CRC signature associated with the modified read operation; and when the CRC signature matches the calculated CRC signature associated with the modified read operation, return the data associated with the modified read operation to the requester of the data.

13. The data storage device according to claim 12, wherein: the read operation comprises: transferring the data from an internal memory of an error correction code (ECC) engine for decoding the data to the first volatile memory device; and the modified read operation comprises: transferring the data from the internal memory of the ECC engine for decoding the data to the second volatile memory device.

14. The data storage device according to claim 13, wherein in response to determining that the data exists in the ECC engine, the data is transferred from the internal memory of the ECC engine for decoding the data to the second volatile memory device.

15. The data storage device according to claim 14, wherein in response to determining that the data does not exist in the ECC engine, the modified read operation includes: Re-reading the data from the memory device; Decoding the data using the ECC engine; And Transferring the data to the second volatile memory device.

16. The data storage device according to claim 12, wherein in response to determining that the CRC signature of the data does not match the calculated CRC signature associated with the read operation, the controller is further configured to: Issue a severe warning status to the requester, wherein the severe warning status instructs the requester to perform any one of the following: Reset of the data storage device, wherein the read operation is re-executed upon the reset of the data storage device; or Re-issue a command corresponding to the modified read operation.

17. The data storage device according to claim 12, wherein the controller is further configured not to send an uncorrectable error correction code (UECC) error to the requester when the CRC signature of the data does not match the calculated CRC signature associated with the read operation.

18. The data storage device according to claim 17, wherein the controller is further configured to send the UECC error to the requester when the CRC signature of the data does not match the calculated CRC signature associated with the modified read operation.

19. A data storage device, the data storage device comprising: Means for storing non-volatile data; Means for storing first volatile data; Means for storing second volatile data; And A controller, the controller being coupled to the means for storing non-volatile data, the means for storing first volatile data, and the means for storing second volatile data, wherein the controller is configured to: Receive a read command to read data from the means for storing non-volatile data; Transfer the data from the means for storing non-volatile data to an error correction code (ECC) engine for decoding; Decode the data; Store the decoded data in the means for storing first volatile data; Determine that the cyclic redundancy code (CRC) signature of the data does not match the calculated CRC signature of the decoded data; And Re-issue the read command as a modified read command, wherein the modified read command uses the means for storing second volatile data instead of the means for storing first volatile data to store the decoded data.

20. The data storage device according to claim 19, wherein the controller includes a Command Automation Processor (CAP), and wherein the CAP is configured to specify the use of the device for storing the second volatile data for the modified read command.

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