Reconfigurable transmit digital-to-analog converter (DAC) circuit

Abstract

Methods and apparatus for sharing a digital-to-analog converter (DAC) in a reconfigurable digital-to-analog converter (DAC) circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. An example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands, and an interleaved DAC circuit as at least two channels having a second set of one or more frequency bands different from the first set of frequency bands.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 068,941, filed on December 20, 2022, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to reconfigurable digital - to - analog converter (DAC) circuits capable of supporting multiple radio access technologies (RATs), frequency bands, and / or transmitter architectures. Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasting, and so on. Such wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long - Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile Communications (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RAT (e.g., WiFi), Cellular Vehicle - to - Everything (C - V2X), etc.

[0005] A wireless communication network can include multiple base stations capable of supporting communication for multiple mobile stations. A mobile station (MS) can communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station can send data and control information to the mobile station on the downlink and / or can receive data and control information from the mobile station on the uplink. The base station and / or the mobile station can include at least one transceiver, which can include, for example, multiple transmit paths designated for transmission using different RATs. Different RATs can use different sets of frequency bands for transmission, and in some cases, a single RAT (e.g., 5G NR) can use different sets of one or more frequency bands. Summary of the Invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, none of which alone is responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," it will be understood how the features of the present disclosure provide advantages including reduced digital-to-analog converter (DAC) circuit area (e.g., in a transmitter) and cost by sharing hardware to support multiple radio access technologies (RATs), frequency bands, and / or transmitter architectures.

[0007] Certain aspects of the present disclosure provide a DAC circuit. The DAC circuit generally includes: a first DAC; a first set of one or more switches coupled between an output of the first DAC and a first output of the DAC circuit; a second DAC; a second set of one or more switches coupled between an output of the second DAC and a second output of the DAC circuit; a third DAC; a third set of one or more switches coupled between an output of the third DAC and a third output of the DAC circuit; a fourth DAC; a fourth set of one or more switches coupled between an output of the fourth DAC and a fourth output of the DAC circuit; a fifth set of one or more switches coupled between an output of the first DAC and a fifth output of the DAC circuit; a sixth set of one or more switches coupled between an output of the second DAC and the fifth output of the DAC circuit; a seventh set of one or more switches coupled between an output of the third DAC and a sixth output of the DAC circuit; and an eighth set of one or more switches coupled between an output of the fourth DAC and the sixth output of the DAC circuit.

[0008] Certain aspects of the present disclosure provide a wireless device including the DAC circuit described herein. The wireless device generally further includes: a first mixer configured to receive a first oscillation signal; and a second mixer configured to receive a second oscillation signal, wherein the second oscillation signal is phase-shifted 90° relative to the first oscillation signal.

[0009] Certain aspects of the present disclosure provide a DAC circuit. The DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands and configured as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

[0010] Certain aspects of the present disclosure provide a method for wireless communication. The method generally includes: configuring a DAC circuit in a first configuration configured to support at least four channels, converting a plurality of first digital signals into a plurality of first analog signals using the DAC circuit in the first configuration, configuring the DAC circuit in a second configuration configured to support at least one channel but less than four channels, and converting a plurality of second digital signals into one or more second analog signals using the DAC circuit in the second configuration.

[0011] To achieve the foregoing and related purposes, one or more aspects include the features described in full below and particularly pointed out in the claims. The following description and the drawings set forth in detail some illustrative features of one or more aspects. However, these features are only indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To enable a more particular understanding of the manner in which the above-recited features of the present disclosure can be obtained, a more specific description, briefly summarized above, may be had by reference to the aspects, some of which are illustrated in the drawings. It is to be noted, however, that the drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, for the specification may admit of other equally effective aspects.

[0013] Figure 1 is a diagram of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0014] Figure 2 is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which aspects of the present disclosure may be practiced.

[0015] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0016] Figure 4A is a block diagram of a digital-to-analog converter (DAC) architecture that uses different DAC circuits for different sets of frequency bands.

[0017] Figure 4B is a block diagram of an example reconfigurable DAC architecture that uses a single DAC circuit to support different sets of frequency bands in accordance with certain aspects of the present disclosure.

[0018] Figure 4C is a block diagram of an example reconfigurable DAC architecture that uses a single DAC circuit to support different sets of frequency bands and different transmitter architectures in accordance with certain aspects of the present disclosure.

[0019] Figure 5A is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit to support different sets of frequency bands in accordance with some aspects of the present disclosure.

[0020] Figure 5B is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit to support different sets of frequency bands and different transmitter architectures in accordance with some aspects of the present disclosure.

[0021] Figure 6A is a block diagram of a portion of an example transmitter front end configured to support sub-6 GHz bands and coupled to a reconfigurable DAC circuit in accordance with some aspects of the present disclosure.

[0022] Figure 6B is a block diagram of a portion of an example transmitter front end configured to support millimeter wave (mmW) bands and coupled to a reconfigurable DAC circuit in accordance with some aspects of the present disclosure.

[0023] Figure 6C is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer orthogonal scheme in accordance with some aspects of the present disclosure.

[0024] Figure 6D is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer real intermediate frequency (IF) scheme with interleaving in accordance with some aspects of the present disclosure.

[0025] Figure 6E is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit supporting a single-layer real IF scheme with interleaving in accordance with some aspects of the present disclosure.

[0026] Figure 6F is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer real IF scheme without interleaving in accordance with some aspects of the present disclosure.

[0027] Figure 7 is a flowchart of an example operation for wireless communication in accordance with some aspects of the present disclosure.

[0028] For ease of understanding, the same reference numerals have been used, where possible, to denote the same elements common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized in other aspects without specific recitation. Detailed Description

[0029] Certain aspects of the present disclosure relate to techniques and apparatus for sharing a digital-to-analog (DAC) converter in a reconfigurable DAC circuit to support two or more transmit (TX) chains of a radio frequency (RF) transceiver or transmitter. Also referred to as a "converged DAC circuit," the reconfigurable DAC circuit may be capable of supporting different radio access technologies (RATs) (using different sets of frequency bands) and / or different transmitter architectures. Using a single reconfigurable DAC circuit instead of multiple DAC circuits reduces redundancy, saves area and cost of an integrated circuit (IC), and may reduce power consumption.

[0030] Aspects of the present disclosure are described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently or in combination with any other aspect of the present disclosure. For example, any number of the aspects set forth herein may be used to implement an apparatus or practice a method. In addition, the scope of the present disclosure is intended to cover such an apparatus or method practiced using other structures, functionality, or a combination of structures and functionality in addition to or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention.

[0031] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0032] As used herein, the term "coupled to" in various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly coupled to element B). In the context of electronic components, the term "coupled to" may also be used herein to mean that a wire, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected therebetween).

[0033] As used herein, a "transmission processor," "baseband processor," or "transmit front-end (TXFE) processor" generally refers to logic, such as phase control logic and delay control logic, for processing digital signals received from a modem (modulator-demodulator) before converting the digital signals to analog signals by a DAC for upconversion, filtering, amplification, and transmission. The baseband processor may also be referred to as a "digital baseband transmission processor."

[0034] Example wireless system

[0035] Figure 1 An example wireless communication network 100 is illustrated in which aspects of the present disclosure may be practiced. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth-generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth-generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second-generation / third-generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to IEEE standards such as one or more of the 802.11 standards.

[0036] As Figure 1 illustrated, the wireless communication network 100 may include several base stations (BSs) 110a through 110z (each also referred to herein individually as a "BS 110" or collectively as "BS 110") and other network entities. The BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next-generation Node B (gNodeB or gNB), or some other term.

[0037] The BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move according to the location of the mobile BS. In some examples, the BS 110 may use any suitable transport network to interconnect with each other and / or connect to one or more other BSs or network nodes (not shown) in the wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.). In Figure 1 the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. The BS may support one or more cells.

[0038] BS 110 communicates with one or more user equipments (UEs) 120a to 120y in the wireless communication network 100 (each also referred to herein individually as "UE 120" or collectively as "UE 120"). The UE can be fixed or mobile and can also be referred to as a user terminal (UT), mobile station (MS), access terminal, station (STA), client, wireless device, mobile device, or some other term. The user terminal can be a wireless device such as a cellular phone, smartphone, personal digital assistant (PDA), handheld device, wearable device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0039] BS 110 is considered a transmitting entity for the downlink and a receiving entity for the uplink. UE 120 is considered a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operating device or equipment capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operating device or equipment capable of receiving data via a frequency channel. In the following description, the subscript "dn" represents the downlink and the subscript "up" represents the uplink. N up UEs can be selected for simultaneous transmission on the uplink, and N dn UEs can be selected for simultaneous transmission on the downlink. N up can be equal to or can be not equal to N dn and N up and N dn can be a static value or can change for each scheduling interval. Beam control or some other spatial processing technique can be used at BS 110 and UE 120.

[0040] UEs 120 (e.g., 120x, 120y, etc.) can be scattered throughout the wireless communication network 100, and each UE 120 can be stationary or mobile. The wireless communication network 100 can also include relay stations (e.g., relay station 110r) (also referred to as repeaters, etc.), which receive the transmission of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and forward the transmission of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between devices.

[0041] The BS 110 can communicate with one or more UEs 120 on the downlink and uplink at any given moment. The downlink (i.e., the forward link) is the communication link from the BS 110 to the UE 120, and the uplink (i.e., the reverse link) is the communication link from the UE 120 to the BS 110. The UE 120 can also perform peer-to-peer communication with another UE 120.

[0042] The wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to send data on the downlink and uplink. The BS 110 can be equipped with several (N ap antennas) to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A group (N u antennas) of UEs 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to the BS 110 and / or receive user-specific data from the BS. Generally, each UE 120 can be equipped with one or more antennas. N u UEs 120 can have the same or different numbers of antennas.

[0043] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., when additional costs can be supported).

[0044] The network controller 130 (sometimes also referred to as the "system controller") can communicate with a group of BS 110s and provide coordination and control for these BS 110s (e.g., via the backhaul). In some cases (e.g., in a 5G NR system), the network controller 130 can include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 can communicate with the core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane function, policy control function, authentication server function, unified data management, application function, network exposure function, network repository function, network slice selection function, etc.

[0045] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a transmitter circuit having a reconfigurable digital-to-analog converter (DAC) circuit that is capable of supporting multiple radio access technologies (RATs), frequency band sets, and / or transmitter architectures and outputs an analog signal to two or more transmit chains, as described in detail herein.

[0046] Figure 2 Examples of components of BS 110a and UE 120a (e.g., from Figure 1 wireless communication network 100) in which aspects of the present disclosure may be implemented are illustrated.

[0047] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for the physical broadcast channel (PBCH), physical control format indicator channel (PCFICH), physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), physical downlink control channel (PDCCH), group common PDCCH (GC PDCCH), etc. Data may be designated for the physical downlink shared channel (PDSCH), etc. Medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that can be used for the exchange of control commands between wireless nodes. MAC-CE may be carried in a shared channel such as the PDSCH, physical uplink shared channel (PUSCH), or physical sidelink shared channel (PSSCH).

[0048] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for the primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0049] A transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on data symbols, control symbols, and / or reference symbols when applicable, and may provide an output symbol stream to a modulator (MOD) in transceivers 232a - 232t. Each modulator 232a - 232t in the transceivers may process its respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each transceiver in transceivers 232a - 232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from transceivers 232a - 232t may be transmitted via antennas 234a - 234t, respectively.

[0050] At the UE 120a, antennas 252a - 252r may receive the downlink signals from the BS 110a and may provide the received signals to transceivers 254a - 254r, respectively. The transceivers 254a - 254r may condition (e.g., filter, amplify, down-convert, and digitize) the respective received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a - 232t may further process the input samples (e.g., for OFDM, etc.) to obtain the received symbols. A MIMO detector 256 may obtain the received symbols from all the demodulators in transceivers 254a - 254r, perform MIMO detection on the received symbols when applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, de-interleave, and decode) the detected symbols, provide the decoded data for the UE 120a to a data sink 260, and provide the decoded control information to a controller / processor 280.

[0051] On the uplink, at the UE 120a, the transmit processor 264 may receive and process data (e.g., for the Physical Uplink Shared Channel (PUSCH)) from the data source 262, and receive and process control information (e.g., for the Physical Uplink Control Channel (PUCCH)) from the controller / processor 280. The transmit processor 264 may also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). The symbols from the transmit processor 264 may be pre-coded by the TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a - 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At the BS 110a, the uplink signal from the UE 120a may be received by the antenna 234, processed by a demodulator in the transceivers 232a - 232t, detected by the MIMO detector 236 (if applicable), and further processed by the receive processor 238 to obtain the decoded data and control information transmitted by the UE 120a. The receive processor 238 may provide the decoded data to the data sink 239 and the decoded control information to the controller / processor 240.

[0052] The memories 242 and 282 may store data and program codes for the BS 110a and the UE 120a, respectively. The memories 242 and 282 may also interface with the controller / processors 240 and 280, respectively. The scheduler 244 may schedule the UE for data transmission on the downlink and / or uplink.

[0053] The antenna 252, processors 258, 264, 266 and / or the controller / processor 280 of the UE 120a and / or the antenna 234, processors 220, 230, 238 and / or the controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0054] In certain aspects of the present disclosure, the transceiver 232 and / or the transceiver 254 may include a transmitter circuit having a reconfigurable digital-to-analog converter (DAC) circuit that is capable of supporting different radio access technologies (RATs), different one or more band sets, and / or different transmitter architectures, and outputting an analog signal to two or more transmit chains, as described in detail herein.

[0055] Example RF transceiver

[0056] Figure 3FIG. 0 is a block diagram of an example radio frequency (RF) transceiver circuit 300 in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via the antenna 306. When the TX path 302 and the RX path 304 share the antenna 306, these paths may be connected to the antenna via an interface 308, which may include any one of various suitable RF devices such as switches, diplexers, duplexers, multiplexers, etc.

[0057] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0058] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-converting from baseband to radio frequency). This frequency conversion process produces a sum frequency and a difference frequency between the LO frequency and the frequency of the baseband signal of interest. The sum frequency and the difference frequency are referred to as “beat frequencies”. The beat frequencies are typically in the RF range such that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, several mixers may be used to up-convert the filtered baseband signal to one or more intermediate frequencies and then up-convert the intermediate frequency (IF) signal to the frequency for transmission.

[0059] The RX path 304 may include a low-noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0060] Some transceivers may employ a frequency synthesizer with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320. The transmit LO may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332. The receive LO may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For some aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0061] The controller 336 (e.g., Figure 2 the controller / processor 280 in Figure 2 may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via the TX path 302 and / or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 338 (e.g.,

[0062] Example multiple individual transmit DAC circuits

[0063] In a transmitter that supports different radio access technologies (RATs), each RAT can be supported by at least one transmit chain (e.g., TX path 302), which can include a complete set of dedicated circuit elements such as a transmit processor, DAC 310, BBF 312, mixer 314, DA 316, and PA 318. For example, each transmit chain can include such a separate set of dedicated elements due to the different frequency, noise, power, and / or distortion specifications of each RAT. For example, a single wireless device that supports Cellular Vehicle-to-Everything (C-V2X), sub-6 GHz (or Frequency Range 1 (FR1)) of 5G, and 5G millimeter wave (or Frequency Range 2 (FR2)) communications can include TX chains, each TX chain including a separate set of dedicated circuit elements such as those listed above.

[0064] Figure 4A is a block diagram of a digital-to-analog converter (DAC) architecture 400A that uses different DAC circuits 402, 404 for different sets of frequency bands (or different radio access technologies (RATs)). As Figure 4A illustrated, the DAC architecture 400A is configured to support two different sets of frequency bands: sub-6 GHz and mmW. Thus, the DAC architecture 400A can include two DAC circuits: a sub-6 GHz DAC circuit 402 and a mmW DAC circuit 404.

[0065] In some cases, a harmonic rejection mixer (HRM) scheme can be used for some frequency bands (e.g., the sub-6 GHz band, but can additionally or alternatively be used for the mmW band). The HRM scheme can involve generating four phase-shifted outputs in the transmitter. Thus, the sub-6 GHz output 406 from the DAC circuit 402 can include a sub-6 GHz in-phase channel (sub6_Ich), a sub-6 GHz quadrature channel (sub6_Qch) that is phase-shifted 90° relative to the in-phase channel, a sub-6 GHz 45° phase-shifted channel (sub6_I45ch), and a sub-6 GHz 135° phase-shifted channel (sub6_Q45ch). Each of the sub-6 GHz outputs 406 can be an input to a corresponding transmit chain (e.g., TX path 302). In other aspects, when the HRM scheme is not used, the sub-6 GHz mode can use only two outputs (e.g., sub6_Ich and sub6_Qch).

[0066] The transmitter can generate two phase-shifted outputs in the mmW mode. The mmW output 408 from the DAC circuit 404 can include a mmW in-phase channel (mmW_Ich) and a mmW quadrature channel (mmW_Qch). Each of the mmW outputs 408 can be an input to a corresponding transmit chain.

[0067] Even though a transceiver may include multiple TX chains, for some aspects, a limited number of TX chains may be used simultaneously. Additionally, certain RATs may be prevented from transmitting simultaneously from a single device. For example, sub-6 GHz (or C-V2X) and mmW transmit chains may not be enabled concurrently. For example, if the sub-6 GHz DAC circuit 402 is in use, the mmW DAC circuit 404 may be idle (and vice versa). However, even when a DAC circuit is idle, the idle circuit may still consume power. Thus, providing a separate DAC circuit for each TX chain may be considered redundant, waste chip area, consume power unnecessarily, and not be cost-effective.

[0068] Example reconfigurable transmit DAC circuit

[0069] Certain aspects of the present disclosure provide a reconfigurable transmit DAC circuit (also referred to as a “converged DAC circuit”) that can support multiple RATs (and / or multiple different sets of one or more frequency bands) to reduce redundancy, save integrated circuit (IC) area and cost, and potentially reduce power consumption. The reconfigurable DAC circuit includes a shared DAC bank, the output of which is coupled to a plurality of switches that can route the DAC output to different transmit chains that support different RATs (and / or different frequency bands). Additionally or alternatively, for some aspects, the reconfigurable DAC circuit can be reconfigured to support different transmitter architectures, such as zero intermediate frequency (IF), complex IF, and real IF architectures, and can be reconfigured to support single-layer and double-layer transmitter architectures (whether with or without interleaving), thereby allowing for a more general transmitter. Such a reconfigurable DAC circuit can support a wide range of full-scale current (I FS ) scalability, can be able to drive different baseband filters and / or different mixer interfaces, and can operate at different sampling rates and clock phase specifications.

[0070] Figure 4B is a block diagram of an example DAC architecture that uses a reconfigurable DAC circuit 410B (labeled “converged DAC circuit”) in accordance with certain aspects of the present disclosure. The reconfigurable DAC circuit 410B can support different RATs and / or different sets of frequency bands, such as sub-6 GHz (in 5G or C-V2X) and mmW bands. Although sub-6 GHz and mmW bands are used throughout the present disclosure, it should be understood that these terms may be interchanged with frequency range 1 (FR1) and frequency range 2 (FR2) bands, respectively, unless otherwise explicitly or implicitly (e.g., by context) specified.

[0071] To support a harmonic rejection mixer (HRM) architecture for sub-6 GHz, the reconfigurable DAC circuit 410B can include four DACs 412, 414, 416, and 418 (which can also be referred to as "subDACs" or "DAC cores"). Although four DACs are shown in Figure 4B , the reader will understand that the reconfigurable DAC circuit is not limited thereto and can include any suitable number of DACs. In some aspects, DAC 412 (labeled "I") is designated as an in-phase (I) DAC, indicating that DAC 412 is configured to support the I channel in the HRM architecture. Similarly, DAC 414 (labeled "Q") can be designated as a quadrature (Q) DAC, indicating that DAC 414 is configured to support the Q channel in the HRM architecture. Continuing, DAC 416 (labeled "I45") can be designated as a 45° phase shift (I45) DAC, indicating that DAC 416 is configured to support the I45 channel in the HRM architecture, and DAC 418 (labeled "Q45") can be designated as a 135° phase shift quadrature (Q45) DAC, indicating that DAC 418 is configured to support the Q45 channel in the HRM architecture.

[0072] For some aspects, DAC 412 can be physically located near DAC 414 (e.g., to increase residual sideband (RSB) rejection in a particular DAC circuit configuration). Additionally or alternatively, DAC 416 can be physically located near DAC 418. For other aspects, DAC 412 can be physically located near DAC 416, and / or DAC 414 can be physically located near DAC 418.

[0073] The reconfigurable DAC circuit 410B can have at least six outputs, including four sub-6 GHz outputs 406 and two mmW outputs 408, as Figure 4B shown. To support reconfiguration, the DAC circuit 410B can include a set of one or more switches coupled between each output of DACs 412, 414, 416, 418 and the outputs of the DAC circuit 410B. In other words, each output of DACs 412, 414, 416, 418 can be selectively coupled to different outputs of the DAC circuit 410B through multiple sets of switches. The switch sets are used to route the outputs of DACs 412, 414, 416, 418 to one or more transmit chains that support the RAT (or frequency band) currently selected for the transmitter including the reconfigurable DAC circuit 410B. Each switch can be implemented by a transistor, a transmission gate, or any other suitable component for performing the switching function. A controller (e.g., Figure 3The controller 336) in can control the state (open or closed) of the switches in the reconfigurable DAC circuit 410B.

[0074] In Figure 4B the example shown, a first set of switches S1 can be coupled between the output of DAC 412 and the sub6_Ich output of DAC circuit 410B, a second set of switches S2 can be coupled between the output of DAC 414 and the sub6_Qch output of DAC circuit 410B, a third set of switches S3 can be coupled between the output of DAC 416 and the sub6_I45ch output of DAC circuit 410B, and a fourth set of switches S4 can be coupled between the output of DAC 418 and the sub6_Q45ch output of DAC circuit 410B. The switch groups S1 - S4 can be closed to support the sub-6 GHz mode (using an HRM scheme with four channels).

[0075] To support DAC aggregation and reconfigurability, DAC circuit 410B further includes a fifth set of switches S5 coupled between the output of DAC 412 and the mmW_Ich output of DAC circuit 410B. For some aspects, DAC circuit 410B further includes a sixth set of switches S6 coupled between the output of DAC 414 and the mmW_Ich output of DAC circuit 410B. That is, the mmW_Ich output of DAC circuit 410B can be shorted or otherwise coupled to both the fifth set of switches S5 and the sixth set of switches S6, as Figure 4B illustrated. Additionally, DAC circuit 410B can include a seventh set of switches S7 coupled between the output of DAC 416 and the mmW_Qch output of DAC circuit 410B. For some aspects, DAC circuit 410B further includes an eighth set of switches S8 coupled between the output of DAC 418 and the mmW_Qch output of DAC circuit 410B. In other words, the mmW_Qch output of DAC circuit 410B can be shorted or otherwise coupled to both the seventh set of switches S7 and the eighth set of switches S8, as Figure 4B illustrated.

[0076] For some aspects, any two of the fifth through eighth sets of switches S5 - S8 can be closed to support the mmW mode (with two channels). For other aspects, any two of the fifth through eighth sets of switches (e.g., the fifth set of switches S5 and the seventh set of switches S7) can be closed during a first interval, while a different two of the fifth through eighth sets of switches S5 - S8 (e.g., the sixth set of switches S6 and the eighth set of switches S8) can be closed in an alternating manner during a second interval after the first interval to support an interleaved mmW mode (e.g., for a faster DAC circuit sampling rate).

[0077] As described above, the switch bank can be used to route the outputs of DACs 412, 414, 416, 418 to the selected transmit chain. For example, when the DAC circuit 410B is configured to support a sub-6 GHz mode (and associated frequency bands), the first through fourth sets of switches S1 - S4 coupled between the outputs of DACs 412, 414, 416, 418 and the sub-6 GHz output 406 are closed, while the fifth through eighth sets of switches S5 - S8 coupled to the mmW output 408 are open. This routes the outputs of DACs 412, 414, 416, 418 to the four outputs used by the sub-6 GHz mode (for the HRM scheme).

[0078] Since the mmW mode may not utilize the HRM scheme, the mmW mode may use only two outputs of the DAC circuit 410B (one for in-phase and one for quadrature). However, since the reconfigurable DAC circuit 410B includes four DACs in the Figure 4B example, the signals of the output pairs from the four DACs 412, 414, 416, 418 can be interleaved. When the DAC circuit 410 is configured to support the mmW mode (and associated frequency bands), the first through fourth sets of switches S1 - S4 can remain open, and one of the two sets of switches coupled to each of the mmW outputs 408 can be closed, while the other set of switches in the pair can be open to route the outputs of two of the DACs 412, 414, 416, 418 to the mmW transmit chain during a first interval. Then, during a second interval, the previously closed set of switches coupled to each of the mmW outputs 408 can be opened, and the previously open set of switches coupled to each of the mmW outputs 408 can be closed. The first and second intervals can be repeated in an alternating manner to interleave the outputs of DACs 412, 414, 416, 418. For example, during the first interval, the switch sets S5 and S7 can be closed, and the switch sets S6 and S8 can be opened, thereby routing the output of DAC 412 to the mmW_Ich output and the output of DAC 416 to the mmW_Qch output. Then, during the second interval, the switch sets S5 and S7 can be opened, and the switch sets S6 and S8 can be closed, thereby routing the output of DAC 414 to the mmW_Ich output and the output of DAC 418 to the mmW_Qch output. In this way, the reconfigurable DAC circuit 410B can be configured as an interleaved DAC circuit with two channels (mmW_Ich and mmW_Qch).

[0079] Alternatively, in some aspects, the reconfigurable DAC circuit 410B may not be configured for interleaving in the mmW mode. In this case, for the mmW mode, switch groups S1 - S4 may be open, two of the switch groups S5 - S8 (e.g., groups S5 and S7) may be closed, and the other two of the switch groups S5 - S8 (e.g., groups S6 and S8) may be open.

[0080] Although DACs 412, 414, 416, 418 are illustrated as having single - ended outputs coupled to the single - ended output of the DAC circuit 410B in Figure 4B , each DAC may have a differential output that is selectively coupled to the differential output of the DAC circuit through switches (e.g., as Figure 5A is illustrated).

[0081] Figure 5A is a block diagram of a portion of an example wireless transmitter circuit 500A in accordance with some aspects of the present disclosure. The wireless transmitter circuit 500A may include a mmW finite impulse response (FIR) filter 502, a sub - 6 GHz FIR filter 504, a multiplexer (MUX) 506, a processing circuit 508, and a reconfigurable DAC circuit 509 configured to support different sets of frequency bands. The reconfigurable DAC circuit 509 may include DACs 510, 512, 514, 516, a clock distribution circuit 513 (labeled "Clk - Rx"), and a MUX 515. For some aspects, the DACs 510, 512, 514, 516 may have a scalable full - scale current I FS ).

[0082] At least a portion of the mmW FIR filter 502, the sub-6 GHz FIR filter 504, the MUX 506, and the processing circuit 508 can be part of a processor (such as a baseband processor). The mmW FIR filter 502 can receive and filter n-bit digital in-phase and quadrature mmW inputs (labeled "Din_mmW_I" and "Din_mmW_Q" respectively), which can be received, for example, from a modem or another part of the processor. Similarly, the sub-6 GHz FIR filter 504 can receive and filter n-bit digital in-phase and quadrature sub-6 GHz inputs (labeled "Din_mmW_I" and "Din_mmW_Q" respectively), which can also be received, for example, from a modem or another part of the processor. The MUX 506 can be used to select between the outputs of the mmW FIR filter 502 and the sub-6 GHz FIR filter 504 for routing to the processing circuit 508. The processing circuit 508 can include, for example, at least one of a decoder, a parallel-to-serial converter, and a level shifter. The n-bit digital outputs of the processing circuit 508 (labeled "Din_I", "Din_Q", "Din_I45", and "Din_Q45") can be routed to the corresponding DACs in the reconfigurable DAC circuit 509.

[0083] The reconfigurable DAC circuit 509 can be similar to Figure 4BThe reconfigurable DAC circuit 410B in, and the DACs 510, 512, 514, 516 can be similar to the DACs 412, 414, 416, 418 respectively, except that the reconfigurable DAC circuit 509 has differential outputs, the DACs 510, 512, 514, 516 have differential outputs, and each switch group S1 - S8 includes a pair of switches (indicated by the "a" and "b" labels). For example, the first switch group S1 includes switch S1a and switch S1b, which are coupled between the differential outputs of the DAC 510 and the sub6_Ich differential output. Similarly, the second switch group S2 includes switch S2a and switch S2b coupled between the differential outputs of the DAC 512 and the sub6_Qch differential output, the third switch group S3 includes switch S3a and switch S3b coupled between the differential outputs of the DAC 514 and the sub6_I45ch differential output, and the fourth switch group S4 includes switch S4a and switch S4b coupled between the differential outputs of the DAC 516 and the sub6_Q45ch differential output. To support the mmW band in the reconfigurable DAC circuit, the fifth switch group S5 includes switch S5a and switch S5b coupled between the differential outputs of the DAC 510 and the mmW_Ich differential output, the sixth switch group S6 includes switch S6a and switch S6b coupled between the differential outputs of the DAC 512 and the mmW_Ich differential output, the seventh switch group S7 includes switch S7a and switch S7b coupled between the differential outputs of the DAC 514 and the mmW_Qch differential output, and the eighth switch group S8 includes switch S8a and switch S8b coupled between the differential outputs of the DAC 516 and the mmW_Qch differential output.

[0084] The MUX 515 can receive clock signals from multiple sources (e.g., multiple frequency synthesizers, such as Figure 3 the TX frequency synthesizer 320 in), and select one of the received clock signals for output to the clock distribution circuit 513. This selection can be controlled by a control signal (e.g., from the controller 336) received through the control input of the MUX 515. For some aspects, as Figure 5A illustrated in, the MUX 515 can be implemented as a single - pole double - throw (SPDT) switch. In Figure 5A the example of, the MUX 515 can receive a clock signal corresponding to the sub - 6 GHz band (labeled "Pll_sub6") and a clock signal corresponding to the mmW band (labeled "Pll_mmW").

[0085] The clock distribution circuit 513 can output multiple clock lines for routing to different DACs in the reconfigurable DAC circuit 509. For some aspects, the clock distribution circuit 513 can output different clock lines to each DAC in the DACs. For example, as Figure 5A shown, the clock distribution circuit 513 can output four clock lines Clk1 - Clk4, and each of the four DACs in the reconfigurable DAC circuit 509 has one clock line. In this case, the clock line Clk1 can be coupled between the first output of the clock distribution circuit 513 and the clock input of the DAC 510, the clock line Clk2 can be coupled between the second output of the clock distribution circuit 513 and the clock input of the DAC 512, the clock line Clk3 can be coupled between the third output of the clock distribution circuit 513 and the clock input of the DAC 514, and the clock line Clk4 can be coupled between the fourth output of the clock distribution circuit 513 and the clock input of the DAC 516. By routing different clock lines to each DAC in the DACs, each clock line can be calibrated individually (e.g., by adjusting the delay of each output of the clock distribution circuit), so that the sampling timing of each DAC in the reconfigurable DAC circuit can be controlled individually, even though the physical lengths of the clock lines are different (and thus the delays caused by the clock lines are different). For other aspects, at least some DACs can share at least one clock line from the clock distribution circuit 513, so that there can be fewer than four clock lines in the case of four DACs.

[0086] Figure 5A The switch group in the reconfigurable DAC circuit 509 of Figure 4B can operate in the same manner as the corresponding switch group S1 - S8 in the reconfigurable DAC circuit 410B of Figure 4B described above. For example, when the sub - 6 GHz mode is selected, the Pll_sub6 clock signal can be selected by the MUX 515 and distributed from the clock distribution circuit 513. The switches S1a, S1b, S2a, S2b, S3a, S3b, and S4a and S4b can be closed, and the remaining switches S5a - S8b can be opened, so as to route the differential outputs of the DACs 510 - 514 to the corresponding differential sub - 6 GHz outputs of the DAC circuit 509. When the wireless transmitter circuit 500A is in the mmW mode, the operation of the switch group S1 - S8, whether with interleaving or not, has been described above with respect to

[0087] Figure 6AFIG. is a block diagram of a portion of an exemplary transmitter front-end 600A in accordance with certain aspects of the present disclosure, the transmitter front-end being configured to support sub-6 GHz bands and coupled to an output of a reconfigurable DAC circuit 509 selected to operate in a sub-6 GHz mode. Since the transmitter front-end 600A operates in a sub-6 GHz mode, it should be understood that the switch groups S1-S4 in the reconfigurable DAC circuit 509 are closed (but not explicitly shown) to route the outputs of DACs 510, 512, 514, 516 to a transmit path for sub-6 GHz transmission, and the switch groups S5-S8 are open (but not shown).

[0088] The transmitter front-end 600A includes four transmit paths for sub-6 GHz transmission using an HRM scheme. Each of the four sub-6 GHz differential outputs (Sub6_Ich, Sub6_Qch, Sub6_I45ch, and Sub6_Q45ch) of the DAC circuit 509 may be coupled to a different transmit path. Each of the four transmit paths includes a baseband filter (one of baseband filters 610, 612, 614, 616) and a mixer (one of mixers 618, 620, 622, 624). Each of the baseband filters 610, 612, 614, 616 may be similar to the BBF 312, and each of the mixers 618, 620, 622, 624 may be similar to the mixer 314. In Figure 6AIn the example, the differential outputs of the DAC 510 (and sub6_Ich) are coupled to the differential inputs of the baseband filter (BBF) 610, and the differential outputs of the BBF 610 are coupled to the differential inputs of the mixer 618. The mixer 618 can also receive an in-phase local oscillator signal (labeled "LO0"), which is the reason why the DAC 510 can be designated as an in-phase DAC (IDAC) in the sub-6 GHz mode. The differential outputs of the DAC 512 (and sub6_Qch) are coupled to the differential inputs of the BBF 614, and the differential outputs of the BBF 614 are coupled to the differential inputs of the mixer 622. The mixer 618 can also receive a quadrature local oscillator signal that is phase-shifted 90° relative to the in-phase local oscillator signal (labeled "LO90"), which is the reason why the DAC 512 can be designated as a quadrature DAC (QDAC) in the sub-6 GHz mode. The differential outputs of the DAC 514 (and sub6_I45ch) are coupled to the differential inputs of the BBF 612, and the differential outputs of the BBF 612 are coupled to the differential inputs of the mixer 620. The mixer 620 can also receive a local oscillator signal that is phase-shifted 45° relative to the in-phase local oscillator signal (labeled "LO45"), which is the reason why the DAC 514 can be designated as an I45DAC. The differential outputs of the DAC 516 (and sub6_Q45ch) are coupled to the differential inputs of the BBF 616, and the differential outputs of the BBF 616 are coupled to the differential inputs of the mixer 624. The mixer 624 can also receive a local oscillator signal that is phase-shifted 135° relative to the in-phase local oscillator signal (and 45° relative to the quadrature local oscillator signal) (labeled "LO135"), which is the reason why the DAC 516 can be designated as a Q45DAC.

[0089] The transmitter front-end 600A also includes an amplifier 626, which can represent a driver amplifier and / or a power amplifier (e.g., Figure 3 DA 316 and / or PA 318 in ). The differential outputs from each transmit path (e.g., the output of each mixer) can be combined and coupled to the input of the amplifier 626.

[0090] Figure 6BFIG. is a block diagram of a portion of an exemplary transmitter front end 600B in accordance with certain aspects of the present disclosure, the transmitter front end being configured to support the mmW band and coupled to the output of a reconfigurable DAC circuit 509 selected to operate in mmW mode. Since the transmitter front end 600B operates in mmW mode, it should be understood that the switch groups S1 - S4 in the reconfigurable DAC circuit 509 are open (but not explicitly shown), and the switch groups S5 - S8 are selectively closed (but not shown) to route the outputs of DACs 510, 512, 514, 516 to the transmit path for mmW transmission (as described above) with or without interleaving.

[0091] As Figure 6B illustrated, the transmitter front end 600B includes two transmit paths for mmW transmission. Each of the mmW differential outputs (mmW_Ich and mmW_Qch) of the DAC circuit 509 can be coupled to a different transmit path. Each of the two transmit paths includes a mixer (one of mixers 630, 632). Each of mixers 630, 632 can be similar to mixer 314. Due to interleaving, the differential output of DAC 510 or DAC 512 can be coupled to the mmW_Ich output of the reconfigurable DAC circuit 509. The mmW_Ich output can be coupled to the differential input of mixer 630. Mixer 630 can also receive an in-phase local oscillator signal (labeled "LO0"), which is the reason why this differential output of the DAC circuit 509 is designated as "mmW_Ich". The differential output of DAC 514 or DAC 516 (based on interleaving) can be coupled to the mmW_Qch output of the reconfigurable DAC circuit 509. The mmW_Qch output can be coupled to the differential input of mixer 632. Mixer 632 can also receive a quadrature local oscillator signal (labeled "LO90"), which is the reason why this differential output of the DAC circuit 509 is designated as "mmW_Qch".

[0092] Each of the transmit chains can include an optional baseband filter (BBF) disposed between the mmW output of the DAC circuit 509 and the input of each mixer 630, 632. For example, the differential mmW_Ich output can be coupled to the differential input of BBF 628, and the differential output of BBF 628 can be coupled to the differential input of mixer 630. Similarly, the differential mmW_Qch output can be coupled to the differential input of BBF 629, and the differential output of BBF 629 can be coupled to the differential input of mixer 632. Each of BBF 628, 629 can be similar to Figure 3 BBF 312 in

[0093] The transmitter front end 600B also includes an amplifier 634, which may represent a driver amplifier and / or a power amplifier (e.g., Figure 3 the DA 316 and / or the PA 318 in ). The differential outputs from each transmit path (e.g., the output of each mixer) may be combined and coupled to the input of the amplifier 634.

[0094] Example reconfigurable transmit DAC circuit supporting more than two RATs (or bands) and / or multiple transmitter architectures Circuit

[0095] It may be desirable to provide a DAC circuit that can be reconfigured to support more or different frequency bands (or RATs) compared to below 6 GHz and the mmW band. Additionally or alternatively, it may be desirable to provide a DAC circuit that can be reconfigured to support different transmitter architectures. For example, Figure 3 the transmitter architecture shown in is a zero intermediate frequency (IF) architecture, where a digital baseband signal is converted to an analog baseband signal by the DAC circuit, and the analog baseband signal is upconverted to a radio frequency (RF) signal for transmission. Other transmitter architectures (e.g., complex IF and real IF architectures) may involve generating a digital IF signal from the digital baseband signal, converting the digital IF signal to an analog IF signal, and upconverting the analog IF signal to an RF signal for transmission. Different transmitter architectures have different advantages, which may make a particular architecture more or less suitable for a given scenario. For example, due to favorable frequencies, the real IF architecture may be preferred in certain mmW bands, and these favorable frequencies enable low crosstalk, reduced power, reduced cable loss, and provide enhanced RSB suppression. In some designs, the real IF architecture may be preferred at lower bandwidths (e.g., <600 MHz), while orthogonal schemes (e.g., zero IF or complex IF architectures) may be preferred at higher bandwidths (e.g., at 1000 MHz).

[0096] Certain aspects of the present disclosure provide a reconfigurable DAC circuit capable of supporting multiple transmitter architectures and / or more than two RATs (or frequency bands). Sharing a reconfigurable common DAC circuit can reduce redundancy, save chip area, and reduce power consumption.

[0097] Figure 4CFIG. is a block diagram of an example reconfigurable DAC circuit 410C configured to support multiple RATs, multiple frequency bands, and / or different transmitter architectures in accordance with certain aspects of the present disclosure. The reconfigurable DAC circuit 410C may be similar to the reconfigurable DAC circuit 410B, with additional outputs and corresponding switch banks, e.g., for supporting multiple transmitter architectures and / or more than two RATs (or sets of frequency bands). For example, the reconfigurable DAC circuit 410C may be configured to support sub-6 GHz bands, mmW bands, a real IF architecture, and a dual-layer orthogonal scheme (conventional mmW architecture). For a scheme that supports an intermediate frequency (IF) signal (e.g., a real IF or complex IF architecture), the DACs 412, 414, 416, 418 should be able to process digital IF signals.

[0098] To achieve this, the reconfigurable DAC circuit 410C may include eight additional outputs and eight additional switch banks. Although in Figure 4CThe example illustrates a total of 16 DAC circuit outputs and 16 sets of switches, but the reader will understand that any suitable number of DAC circuit outputs and a suitable number of associated sets of switches can be selected. To support a real IF architecture with DAC circuit 410C, a ninth set of switches S9 can be coupled between the output of DAC 412 and the real IF horizontal polarization output (labeled "H_Real_IF1"). A tenth set of switches S10 can be coupled between the output of DAC 414 and another real IF horizontal polarization output (H_Real_IF2) of the DAC circuit 410C. For some aspects, the real IF horizontal polarization outputs H_Real_IF1 and H_Real_IF2 can be shorted or otherwise coupled together and regarded as a single output H_Real_IF. An eleventh set of switches S11 can be coupled between the output of DAC 416 and the real IF vertical polarization output (V_Real_IF1). A twelfth set of switches S12 can be coupled between the output of DAC 418 and another real IF vertical polarization output (V_Real_IF2) of the DAC circuit. For some aspects, the real IF vertical polarization outputs V_Real_IF1 and V_Real_IF2 can be shorted or otherwise coupled together and regarded as a single output V_Real_IF. To support a dual-layer orthogonal scheme with DAC circuit 410C, a thirteenth set of switches S13 can be coupled between the output of DAC 412 and the in-phase horizontal polarization output (I_H), a fourteenth set of switches S14 can be coupled between the output of DAC 414 and the quadrature horizontal polarization output (Q_H), a fifteenth set of switches S15 can be coupled between the output of DAC 416 and the in-phase vertical polarization output (I_V), and a set of switches including switch S16 can be coupled between the output of DAC 418 and the quadrature vertical polarization output (Q_V). The sets of switches S1 - S16 can be used to route the outputs of DACs 412, 414, 416, 418 to the selected transmit chain based on the desired RAT, set of frequency bands, or transmit architecture.

[0099] When the dual-layer orthogonal (conventional mmW) mode is selected, the sets of switches are controlled to couple DACs 412, 414, 416, 418 to the in-phase horizontal (I_H), quadrature horizontal (Q_H), in-phase vertical (I_V), and quadrature vertical (Q_V) polarization outputs. In the reconfigurable DAC circuit 410C, the twelfth to sixteenth sets of switches S13 - S16 are closed, and the other sets of switches S1 - S12 are open (see, for example, Figure 6C). This routes the output of DAC 412 to the I_H output, the output of DAC 414 to the Q_H output, the output of DAC 416 to the I_V output, and the output of DAC 418 to the Q_V output. In this configuration, DAC 412 is designated as the in-phase horizontal polarization (I_H) DAC, DAC 414 is designated as the quadrature horizontal polarization (Q_H) DAC, DAC 416 is designated as the in-phase vertical polarization (I_V) DAC, and DAC 418 is designated as the quadrature vertical polarization (Q_V) DAC.

[0100] When the real IF architecture is selected, the DAC circuit 410C can be configured to support different real IF modes, such as dual-layer real IF with or without interleaving or single-layer real IF.

[0101] When the dual-layer real IF mode with interleaving is selected, two pairs of related switch groups (e.g., the horizontal pair and the vertical pair) in the ninth to twelfth groups of switches S9 - S12 can be closed, where each switch in one pair of switches is closed in an alternating manner and the remaining switch groups (groups S1 - S8 and S13 - S16) are open. In this alternating manner, the designated horizontal switch pair (groups S9 and S10) intermittently couples the output of DAC 412 or the output of DAC 414 to the real IF horizontal polarization output (H_Real_IF), and the designated vertical switch pair (groups S11 and S12) intermittently couples the output of DAC 416 or the output of DAC 418 to the real IF vertical polarization output (V_Real_IF) to achieve interleaving.

[0102] When the single-layer real IF mode with interleaving is selected, the reconfigurable DAC circuit 410C can output only the real IF horizontal polarization signal (or only the real IF vertical polarization signal). Thus, two related switch groups (e.g., the horizontal switches or the vertical switches) in the ninth to twelfth groups of switches S9 - S12 can be closed in an alternating manner (e.g., groups S9 and S10), and the other two groups of switches (e.g., groups S11 and S12) can be open (see, for example Figure 6E), where the remaining switch groups (groups S1 - S8 and S13 - S16) are disconnected in the DAC circuit 410C. In this alternating manner, the two sets of switches coupled to the real IF horizontal polarization output (or coupled to the real IF vertical polarization output) are interleaved. For example, the switch groups S9 and S10 respectively coupled to the outputs H_Real_IF1 and H_Real_IF2 (which can be shorted or otherwise coupled together to form a single H_Real_IF output) can be interleaved, while the switch groups S11 and S12 remain disconnected in this mode. Alternatively, the switch groups S11 and S12 respectively coupled to the outputs V_Real_IF1 and V_Real_IF2 can be interleaved, while the switch groups S9 and S10 remain disconnected.

[0103] When selecting the double - layer real IF mode without interleaving, two of the ninth to twelfth switch groups S9 - S12 can be closed (e.g., groups S9 and S11), and the other two switch groups (e.g., groups S10 and S12) can be disconnected (see, for example Figure 6F ), where the remaining switch groups (groups S1 - S8 and S13 - S16) are disconnected in the DAC circuit 410C. This routes the output of DAC 412 to the H_Real_IF1 output (or routes the output of DAC 414 to the H_Real_IF2 output) as the horizontal real IF output. This also routes the output of DAC 416 to the V_Real_IF1 output (or routes the output of DAC 418 to the V_Real_IF2 output) as the vertical real IF output.

[0104] Figure 5B is a block diagram of a part of an example wireless transmitter circuit 500B according to certain aspects of the present disclosure. The wireless transmitter circuit 500B can include mmW processing circuit 540, sub - 6 GHz processing circuit 542, real IF processing circuit 544, legacy mmW processing circuit 546 (for the double - layer orthogonal scheme), MUX 506, processing circuit 508, and a reconfigurable DAC circuit 549, which is configured to support different RATs, different sets of frequency bands, and / or different transmitter architectures. The reconfigurable DAC circuit 549 can include a clock distribution circuit 513, DACs 510, 512, 514, 516, and MUX 555.

[0105] The mmW processing circuit 540, the sub-6 GHz processing circuit 542, the real IF processing circuit 544, and the legacy mmW processing circuit 546 can each be configured to process digital inputs, and the control bits of the MUX 506 can be used to select between the processed digital signals. The processed digital signals can be digital baseband signals (e.g., in the case of a zero IF transmitter architecture), or can be digital intermediate frequency (IF) signals (e.g., in the case of a complex IF or real IF architecture). Although these specific four processing circuits are shown in the example of Figure 5B , the reader will understand that the transmitter circuit 500B can include any suitable number of processing circuits that can process digital signals for different RATs, different sets of frequency bands, and / or transmitter architectures different from the example processing circuits shown.

[0106] The reconfigurable DAC circuit 549 can be similar to the reconfigurable DAC circuit 509 in Figure 5A , but has additional switch groups S9 - S12 to support the real IF architecture. The switch groups S1 - S12 are similar to the switch groups S1 - S12 in the reconfigurable DAC circuit 410C of Figure 4C , except that each switch group S1 - S12 includes a pair of switches (indicated by the "a" and "b" markings). To avoid cluttering the drawings, Figure 4C the switch groups S13 - S16 in Figure 5B are not added as differential pairs of switches to Figure 5B , but the reader will understand how these switch groups S13 - S16 can be added to the reconfigurable DAC circuit 549. For the additional switches illustrated in Figure 5B , the ninth group of switches includes switches S9a and S9b, which can be coupled between the differential outputs of the DAC 510 and the differential H_Real_IF1 output of the DAC circuit 549. Similarly, the tenth group of switches includes switches S10a and S10b coupled between the differential outputs of the DAC 512 and the differential H_Real_IF2 output, the eleventh group of switches includes switches S11a and S11b coupled between the differential outputs of the DAC 514 and the differential V_Real_IF1 output, and the twelfth group of switches includes switches S12a and S12b coupled between the differential outputs of the DAC 516 and the differential V_Real_IF2 output.

[0107] Additional or alternative switch differential pairs (e.g., switch groups S13a / b - S16a / b (not shown)) for coupling to the dual-layer quadrature (legacy mmW) outputs of the reconfigurable DAC circuit 410C can be included in the wireless transmitter circuit 500B, as indicated by the I_H, Q_H, I_V, and Q_V outputs shown in parentheses.

[0108] The MUX 555 (e.g., a 4:1 MUX) can receive clock signals from multiple sources (e.g., multiple frequency synthesizers, such as Figure 3 the TX frequency synthesizer 320 in Figure 5B ), and select one of the received clock signals for output to the clock distribution circuit 513. This selection can be controlled by a control signal (e.g., from the controller 336) received through the control input of the MUX 555. In the example of Figure 5B , the MUX 555 can receive a clock signal corresponding to the sub-6 GHz band (labeled "Pll_sub6"), a clock signal corresponding to the mmW band (labeled "Pll_mmW"), a clock signal corresponding to the real IF architecture (labeled "pll_real_IF"), and a clock signal corresponding to the dual-layer orthogonal (legacy mmW) scheme (labeled "pll_legacy_mmW").

[0109] Figure 5B The switch bank in the reconfigurable DAC circuit 549 of Figure 4C can operate in the same manner as the corresponding switch bank S1 - S12 (or S1 - S16) in the reconfigurable DAC circuit 410C of Figure 4C , and need not be repeated here.

[0110] Figure 6C is a block diagram of a part of a transmitter circuit 600C having a reconfigurable DAC circuit 410C implementing a dual-layer orthogonal scheme (legacy mmW scheme) according to certain aspects of the present disclosure. The legacy mmW processing circuit 640 receives digital baseband signals - including an in-phase horizontally polarized baseband signal (I_H*), a quadrature horizontally polarized baseband signal (Q_H*), an in-phase vertically polarized baseband signal (I_V*), and a quadrature vertically polarized baseband signal (Q_V*) - and generates corresponding signals routed to the corresponding DACs of the reconfigurable DAC circuit 410C. Thus, Figure 6C the legacy mmW processing circuit 640 of Figure 5B can represent the legacy mmW processing circuit 546, the MUX 506, and the processing circuit 508 of Figure 5B . As described above, the switch bank S13 - S16 can be closed (where the other switch banks S1 - S12 can be open), and each DAC output is routed to a signal for the corresponding transmit chain (not shown) for legacy mmW (for the dual-layer orthogonal scheme).

[0111] Figure 6DFIG. is a block diagram of a portion of an exemplary transmitter circuit 600D having a reconfigurable DAC circuit 410C in accordance with certain aspects of the present disclosure, implementing an interleaved double-layer real IF scheme. In this case, the actual IF signal generator 645 receives the digital baseband signal described above and generates a corresponding real IF output signal that is routed to the corresponding DAC of the reconfigurable DAC circuit 410C. Figure 6D The real IF signal generator 645 of Figure 6D can thus represent Figure 5B the real IF processing circuit 544, the MUX 506, and the processing circuit 508 of Figure 5B . When using an interleaved double-layer real IF, the outputs of the DACs 412, 414, 416, 418 can be provided to the programmable analog MUX 650, which can include an interleaver 652 and an interleaver 654. The interleaver 652 can be configured to receive the outputs of the DACs 412 and 414. The interleaver 652 can be implemented by switch groups S9 and S10 and operate in the same manner as described above to alternate between the two outputs in an interleaved manner. This causes the real IF horizontal polarization output (H_Real_IF) of the reconfigurable DAC circuit 410C to alternate between H_Real_IF1 from the output of the DAC 412 and H_Real_IF2 from the output of the DAC 414. The interleaver 654 can be configured to receive the outputs of the DACs 416 and 418. The interleaver 654 can be implemented by switch groups S11 and S12 and operate in the same manner as described above to alternate between the two outputs in an interleaved manner. This causes the real IF vertical polarization output (V_Real_IF) of the reconfigurable DAC circuit 410C to alternate between V_Real_IF1 from the output of the DAC 416 and V_Real_IF2 from the output of the DAC 418.

[0112] Figure 6E FIG. is a block diagram of a portion of an exemplary transmitter circuit 600E having a reconfigurable DAC circuit 410C in accordance with certain aspects of the present disclosure, implementing an interleaved single-layer real IF scheme. In some aspects, an interleaved single-layer real IF scheme can only involve outputting the real IF horizontal polarization output (H_Real_IF) from the programmable analog MUX 650. In Figure 6EIn the examples illustrated, only the horizontal baseband input may be received by the real IF signal generator 645 and / or only the DACs 412 and 414 and the interleaver 652 are enabled (i.e., the DACs 416 and 418 and the interleaver 654 are disabled). Thus, only the DACs 412 and 414 can receive the real IF signal and generate the analog IF output signals H_Real_IF1 and H_Real_IF2, respectively. Then, the interleaver 652 can operate in the same manner as described above, where the output H_Real_IF will alternate between H_Real_IF1 and H_Real_IF2. Alternatively, the single-layer real IF scheme may involve generating only the vertical polarization output V_Real_IF to the corresponding transmit chain (e.g., where the DACs 412 and 414 and the interleaver 652 are disabled, and the DACs 416 and 418 and the interleaver 654 are enabled).

[0113] Figure 6F is a block diagram of a portion of an example transmitter circuit 600F having a reconfigurable DAC circuit 410C in accordance with certain aspects of the present disclosure, implementing a two-layer real IF scheme without interleaving. Since a portion of the transmitter circuit 600F uses a two-layer real IF, both the H_Real_IF and V_Real_IF outputs are generated and routed to the corresponding transmit chains. However, since interleaving is not used in this example, the real IF signal generator 645 can generate only two in-phase real IF signals (and / or only the DACs 412 and 416 are enabled as illustrated) or two quadrature real IF signals (and / or only the DACs 414 and 418 are enabled). For example, as Figure 6F illustrated, the real IF signal generator 645 can send the real IF in-phase horizontal polarization signal to the DAC 412 and the real IF in-phase vertical polarization signal to the DAC 416. In this case, the clock signals for the DACs (e.g., Clk1 and Clk3 for the DACs 412 and 416, respectively) can be phase-shifted by 90°. The programmable analog MUX 650 can be selected (or the switch groups S9 and S11 can be effectively closed) to route the outputs of the DACs 412 and 416 to the H_Real_IF and V_Real_IF outputs of the reconfigurable DAC circuit 410C. Alternatively, the real IF signal generator 645 can send the real IF quadrature horizontal polarization signal to the DAC 414 and the real IF quadrature vertical polarization signal to the DAC 418, and the programmable analog MUX 650 can be selected (or the switch groups S10 and S12 can be effectively closed) to route the outputs of the DACs 414 and 418 to the H_Real_IF and V_Real_IF outputs of the reconfigurable DAC circuit 410C.

[0114] Example operations for wireless communication

[0115] Figure 7 is a flowchart of an example operation 700 for wireless communication according to certain aspects of the present disclosure. The operation 700 may be performed, for example, by a transmitter circuit (such as transmitter circuit 500A or 500B of Figure 4B , Figure 4C , Figure 5A or Figure 5B respectively) that utilizes a reconfigurable DAC circuit (such as reconfigurable DAC circuits 410B, 410C, 509, or 549 of Figure 5A or Figure 5B respectively) as described above.

[0116] Operation 700 may begin at block 702 by configuring a DAC circuit in a first configuration that is configured to support at least four channels. At block 704, the DAC circuit in the first configuration may convert a plurality of first digital signals into a plurality of first analog signals.

[0117] At block 706, the DAC circuit may be configured in a second configuration that is configured to support at least one channel but less than four channels. At block 708, the DAC circuit in the second configuration may convert a plurality of second digital signals into one or more second analog signals.

[0118] According to certain aspects, the plurality of first digital signals are in a first set of one or more frequency bands, and the plurality of second digital signals are in a second set of one or more frequency bands that is different from the first set of one or more frequency bands. For example, the first set of one or more frequency bands may be one or more sub-6 GHz bands, and the second set of one or more frequency bands may be one or more millimeter wave (mmW) bands. As another example, the first set of one or more frequency bands may be one or more frequency range 1 (FR1) bands, and the second set of one or more frequency bands may be one or more frequency range 2 (FR2) bands.

[0119] According to certain aspects, the DAC circuit includes a plurality of switches coupled to the outputs of at least four DACs. In such a case, configuring the DAC circuit in a second configuration can involve selectively closing a first set of the plurality of switches and selectively opening a second set of the plurality of switches, the second set of switches being different from the first set of the plurality of switches. For certain aspects, selectively closing can involve selectively closing the first set of the plurality of switches for a first interval, and selectively opening can involve selectively opening the second set of the plurality of switches for a first interval. In such a case, configuring the DAC circuit in a second configuration can further include: selectively closing a third set of the plurality of switches for a second interval, the third set of switches being different from the first set of the plurality of switches; and selectively opening a fourth set of the plurality of switches for a second interval, the fourth set of switches being different from the second set of the plurality of switches.

[0120] According to certain aspects, the plurality of second digital signals include intermediate frequency (IF) digital signals. In such a case, the DAC circuit can include at least four DACs capable of operating as IF DACs, and at least one channel can be at least one real IF channel.

[0121] Example aspects

[0122] In addition to the various aspects described above, specific combinations of aspects are also within the scope of the present disclosure, some details of which are as follows:

[0123] Aspect 1: A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: a first DAC; a first set of one or more switches, the first set of one or more switches being coupled between an output of the first DAC and a first output of the DAC circuit; a second DAC; a second set of one or more switches, the second set of one or more switches being coupled between an output of the second DAC and a second output of the DAC circuit; a third DAC; a third set of one or more switches, the third set of one or more switches being coupled between an output of the third DAC and a third output of the DAC circuit; a fourth DAC; a fourth set of one or more switches, the fourth set of one or more switches being coupled between an output of the fourth DAC and a fourth output of the DAC circuit; a fifth set of one or more switches, the fifth set of one or more switches being coupled between the output of the first DAC and a fifth output of the DAC circuit; a sixth set of one or more switches, the sixth set of one or more switches being coupled between the output of the second DAC and the fifth output of the DAC circuit; a seventh set of one or more switches, the seventh set of one or more switches being coupled between the output of the third DAC and a sixth output of the DAC circuit; and an eighth set of one or more switches, the eighth set of one or more switches being coupled between the output of the fourth DAC and the sixth output of the DAC circuit.

[0124] Aspect 2: The DAC circuit according to aspect 1, wherein the first DAC is configured as an in-phase (I) DAC, and wherein the second DAC is configured as a quadrature (Q) DAC.

[0125] Aspect 3: The DAC circuit according to aspect 1 or 2, wherein the first DAC is located near the second DAC.

[0126] Aspect 4: The DAC circuit according to any one of the preceding aspects, wherein the third DAC is configured as a 45° phase-shifted (I45) DAC, and wherein the fourth DAC is configured as a 135° phase-shifted quadrature (Q45) DAC.

[0127] Aspect 5: The DAC circuit according to any one of the preceding aspects, wherein the third DAC is located near the fourth DAC.

[0128] Aspect 6: The DAC circuit according to any one of the preceding aspects, wherein the first DAC is located near the second DAC.

[0129] Aspect 7: The DAC circuit according to any one of the foregoing aspects, the DAC circuit further comprising: a clock distribution circuit; a first clock line coupled between a first output of the clock distribution circuit and a clock input of the first DAC; a second clock line coupled between a second output of the clock distribution circuit and a clock input of the second DAC; a third clock line coupled between a third output of the clock distribution circuit and a clock input of the third DAC; and a fourth clock line coupled between a fourth output of the clock distribution circuit and a clock input of the fourth DAC, wherein the first output, the second output, the third output, and the fourth output of the clock distribution circuit are all different outputs.

[0130] Aspect 8: The DAC circuit according to aspect 7, the DAC circuit further comprising a multiplexer, the multiplexer including an output coupled to an input of the clock distribution circuit and including a plurality of inputs configured to receive clock signals from different sources.

[0131] Aspect 9: The DAC circuit according to any one of the foregoing aspects, wherein the DAC circuit is configured to use the first output, the second output, the third output, and the fourth output having a first set of one or more frequency bands, and wherein the DAC circuit is configured to use the fifth output and the sixth output having a second set of one or more frequency bands different from the first set of one or more frequency bands.

[0132] Aspect 10: The DAC circuit according to aspect 9, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0133] Aspect 11: The DAC circuit according to aspect 9, wherein the first set of one or more frequency bands includes one or more Frequency Range 1 (FR1) frequency bands, and wherein the second set of one or more frequency bands includes one or more Frequency Range 2 (FR2) frequency bands.

[0134] Aspect 12: The DAC circuit according to aspect 1 or any one of aspects 5 to 11, wherein: the first DAC is configured as an in-phase (I) DAC; the second DAC is configured as a 45° phase-shifted (I45) DAC; the third DAC is configured as a quadrature (Q) DAC; and the fourth DAC is configured as a 135° phase-shifted quadrature (Q45) DAC.

[0135] Aspect 13: The DAC circuit according to any one of Aspect 1 or Aspects 5 to 11, wherein: the first DAC is configured as an in-phase horizontal polarization (I_H) DAC; the second DAC is configured as an orthogonal (Q) horizontal polarization (Q_H) DAC; the third DAC is configured as an in-phase vertical polarization (I_V) DAC; and the fourth DAC is configured as an orthogonal (Q) vertical polarization (Q_V) DAC.

[0136] Aspect 14: The DAC circuit according to any one of the preceding aspects, the DAC circuit further comprising: a ninth set of one or more switches coupled between the output of the first DAC and the seventh output of the DAC circuit; and at least one of the following: a tenth set of one or more switches coupled between the output of the second DAC and the seventh output of the DAC circuit; or an eleventh set of one or more switches coupled between the output of the third DAC and the eighth output of the DAC circuit.

[0137] Aspect 15: The DAC circuit according to Aspect 14, the DAC circuit further comprising a twelfth set of one or more switches coupled between the output of the fourth DAC and the eighth output of the DAC circuit.

[0138] Aspect 16: The DAC circuit according to Aspect 14 or 15, wherein the seventh output of the DAC circuit is a real intermediate frequency (real IF) output.

[0139] Aspect 17: A wireless device comprising the DAC circuit according to any one of the preceding aspects, the wireless device further comprising: a first mixer configured to receive a first oscillation signal; and a second mixer configured to receive a second oscillation signal, wherein the second oscillation signal is configured to be phase-shifted 90° relative to the first oscillation signal.

[0140] Aspect 18: The wireless device according to Aspect 17, wherein the fifth output of the DAC circuit is coupled to the input of the first mixer, and wherein the sixth output of the DAC circuit is coupled to the input of the second mixer.

[0141] Aspect 19: The wireless device according to aspect 17 or 18, the wireless device further comprising: a third mixer configured to receive a third oscillation signal; a fourth mixer configured to receive a fourth oscillation signal, wherein the third oscillation signal is configured to be phase-shifted by 45° relative to the first oscillation signal; the fourth oscillation signal is configured to be phase-shifted by 135° relative to the first oscillation signal; the first output of the DAC circuit is coupled to the input of the first mixer; the second output of the DAC circuit is coupled to the input of the second mixer; the third output of the DAC circuit is coupled to the input of the third mixer; and the fourth output of the DAC circuit is coupled to the input of the fourth mixer.

[0142] Aspect 20: A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: at least four DACs; and a plurality of switches coupled to the outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands and is configured as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands different from the first set of one or more frequency bands.

[0143] Aspect 21: The DAC circuit according to aspect 20, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0144] Aspect 22: The DAC circuit according to aspect 20, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and wherein the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

[0145] Aspect 23: The DAC circuit according to aspect 20, wherein the DAC circuit is capable of operating as an intermediate frequency (IF) DAC circuit, and wherein the plurality of switches are coupled to the outputs of the at least four DACs such that the DAC circuit is capable of being reconfigured to have at least one real IF channel.

[0146] Aspect 24: A method of wireless communication, the method comprising: configuring a digital-to-analog converter (DAC) circuit in a first configuration configured to support at least four channels; using the DAC circuit in the first configuration to convert a plurality of first digital signals into a plurality of first analog signals; configuring the DAC circuit in a second configuration configured to support at least one channel but fewer than four channels; and using the DAC circuit in the second configuration to convert a plurality of second digital signals into one or more second analog signals.

[0147] Aspect 25: The method according to aspect 24, wherein the plurality of first digital signals are in a first set of one or more frequency bands, and wherein the plurality of second digital signals are in a second set of one or more frequency bands different from the first set of one or more frequency bands.

[0148] Aspect 26: The method according to aspect 25, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0149] Aspect 27: The method according to aspect 25, wherein the first set of one or more frequency bands includes one or more Frequency Range 1 (FR1) frequency bands, and wherein the second set of one or more frequency bands includes one or more Frequency Range 2 (FR2) frequency bands.

[0150] Aspect 28: The method according to any one of aspects 24 to 27, wherein the DAC circuit includes a plurality of switches coupled to the outputs of at least four DACs, and wherein configuring the DAC circuit in the second configuration includes: selectively closing a first set of the plurality of switches; and selectively opening a second set of the plurality of switches, the second set of switches being different from the first set of the plurality of switches.

[0151] Aspect 29: The method according to aspect 28, wherein: the selectively closing includes selectively closing the first set of the plurality of switches for a first interval; the selectively opening includes selectively opening the second set of the plurality of switches for the first interval; and configuring the DAC circuit in the second configuration further includes: selectively closing a third set of the plurality of switches for a second interval, the third set of switches being different from the first set of the plurality of switches; and selectively opening a fourth set of the plurality of switches for the second interval, the fourth set of switches being different from the second set of the plurality of switches.

[0152] Aspect 30: The method according to aspect 24, wherein the plurality of second digital signals includes intermediate frequency (IF) digital signals, wherein the DAC circuit includes at least four DACs capable of operating as an IF DAC, and wherein the at least one channel includes at least one real IF channel.

[0153] Additional considerations

[0154] The above description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of the present disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the methods described may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with respect to some examples may be combined in some other examples. For instance, any number of aspects set forth herein may be used to implement an apparatus or practice a method. Further, the scope of the present disclosure is intended to cover such apparatus or methods practiced using other structures, functional features, or a combination of structures and functional features in addition to or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the present invention. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0155] The various operations of the above-described method may be performed by any suitable component capable of performing the corresponding functions. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally, where there are operations illustrated in the figures, these operations may have corresponding component plus function components. For example, the component for conversion may include a digital-to-analog converter (DAC) circuit, such as the reconfigurable DAC circuits 410B or 410C, respectively, as Figure 4B or Figure 4C described.

[0156] As used herein, the phrase referring to "at least one of" a list of items refers to any combination of those items (which includes a single member). For example, "at least one of a, b, or c" is intended to cover: a, b, c, a - b, a - c, b - c, and a - b - c, as well as any combination having multiple identical elements (e.g., a - a, a - a - a, a - a - b, a - a - c, a - b - b, a - c - c, b - b, b - b - b, b - b - c, c - c, and c - c - c or any other ordering of a, b, and c).

[0157] The methods disclosed herein include one or more steps or acts for implementing the described methods. The steps and / or acts of the methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of the steps or acts is specified, the order and / or use of particular steps and / or acts may be modified without departing from the scope of the claims.

[0158] It should be understood that the claims are not limited to the exact configurations and components illustrated above. Various modifications, variations and alterations to the arrangement, operation and details of the methods and apparatuses described above may be made without departing from the scope of the claims.

Claims

1. A digital-to-analog converter (DAC) circuit, the DAC circuit comprising: A first DAC; A first group of one or more switches, the first group of one or more switches being coupled between an output of the first DAC and a first output of the DAC circuit; A second DAC; A second group of one or more switches, the second group of one or more switches being coupled between an output of the second DAC and a second output of the DAC circuit; A third DAC; A third group of one or more switches, the third group of one or more switches being coupled between an output of the third DAC and a third output of the DAC circuit; A fourth DAC; A fourth group of one or more switches, the fourth group of one or more switches being coupled between an output of the fourth DAC and a fourth output of the DAC circuit; A fifth group of one or more switches, the fifth group of one or more switches being coupled between the output of the first DAC and a fifth output of the DAC circuit; A sixth group of one or more switches, the sixth group of one or more switches being coupled between the output of the second DAC and the fifth output of the DAC circuit; A seventh group of one or more switches, the seventh group of one or more switches being coupled between the output of the third DAC and a sixth output of the DAC circuit; And An eighth group of one or more switches, the eighth group of one or more switches being coupled between the output of the fourth DAC and the sixth output of the DAC circuit.

2. The DAC circuit according to claim 1, wherein the first DAC is configured as an in-phase (I) DAC, and wherein the second DAC is configured as a quadrature (Q) DAC.

3. The DAC circuit according to claim 2, wherein the first DAC is located near the second DAC.

4. The DAC circuit according to claim 2, wherein the third DAC is configured as a 45° phase-shifted (I45) DAC, and wherein the fourth DAC is configured as a 135° phase-shifted quadrature (Q45) DAC.

5. The DAC circuit according to claim 4, wherein the third DAC is located near the fourth DAC.

6. The DAC circuit according to claim 5, wherein the first DAC is located near the second DAC.

7. The DAC circuit according to claim 1, the DAC circuit further comprising: A clock distribution circuit; A first clock line, the first clock line being coupled between a first output of the clock distribution circuit and a clock input of the first DAC; A second clock line, the second clock line being coupled between a second output of the clock distribution circuit and a clock input of the second DAC; A third clock line, the third clock line being coupled between a third output of the clock distribution circuit and a clock input of the third DAC; And A fourth clock line, the fourth clock line being coupled between a fourth output of the clock distribution circuit and a clock input of the fourth DAC, wherein the first output, the second output, the third output, and the fourth output of the clock distribution circuit are all different outputs.

8. The DAC circuit according to claim 7, the DAC circuit further comprising a multiplexer, the multiplexer including an output coupled to an input of the clock distribution circuit and including a plurality of inputs configured to receive clock signals from different sources.

9. The DAC circuit according to claim 1, wherein the DAC circuit is configured to use the first output, the second output, the third output, and the fourth output having a first set of one or more frequency bands, and wherein the DAC circuit is configured to use the fifth output and the sixth output having a second set of one or more frequency bands different from the first set of one or more frequency bands.

10. The DAC circuit according to claim 9, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

11. The DAC circuit according to claim 9, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and wherein the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

12. The DAC circuit according to claim 1, wherein: the first DAC is configured as an in-phase (I) DAC; the second DAC is configured as a 45° phase-shifted (I45) DAC; the third DAC is configured as a quadrature (Q) DAC; and the fourth DAC is configured as a 135° phase-shifted quadrature (Q45) DAC.

13. The DAC circuit according to claim 1, wherein: the first DAC is configured as an in-phase horizontal polarization (I_H) DAC; the second DAC is configured as a quadrature (Q) horizontal polarization (Q_H) DAC; the third DAC is configured as an in-phase vertical polarization (I_V) DAC; and the fourth DAC is configured as a quadrature (Q) vertical polarization (Q_V) DAC.

14. The DAC circuit according to claim 1, the DAC circuit further comprising: a ninth set of one or more switches, the ninth set of one or more switches being coupled between the output of the first DAC and a seventh output of the DAC circuit; and at least one of the following: a tenth set of one or more switches, the tenth set of one or more switches being coupled between the output of the second DAC and the seventh output of the DAC circuit; or an eleventh set of one or more switches, the eleventh set of one or more switches being coupled between the output of the third DAC and an eighth output of the DAC circuit.

15. The DAC circuit according to claim 14, wherein the DAC circuit further comprises a twelfth group of one or more switches, and the twelfth group of one or more switches are coupled between the output of the fourth DAC and the eighth output of the DAC circuit.

16. The DAC circuit according to claim 14, wherein the seventh output of the DAC circuit is a real intermediate frequency (real IF) output.

17. A wireless device comprising the DAC circuit according to claim 1, the wireless device further comprising: a first mixer configured to receive a first oscillation signal; and a second mixer configured to receive a second oscillation signal, wherein the second oscillation signal is configured to be phase-shifted by 90° relative to the first oscillation signal.

18. The wireless device according to claim 17, wherein the fifth output of the DAC circuit is coupled to the input of the first mixer, and wherein the sixth output of the DAC circuit is coupled to the input of the second mixer.

19. The wireless device according to claim 17, the wireless device further comprising: a third mixer configured to receive a third oscillation signal; a fourth mixer configured to receive a fourth oscillation signal, wherein: the third oscillation signal is configured to be phase-shifted by 45° relative to the first oscillation signal; the fourth oscillation signal is configured to be phase-shifted by 135° relative to the first oscillation signal; the first output of the DAC circuit is coupled to the input of the first mixer; the second output of the DAC circuit is coupled to the input of the second mixer; the third output of the DAC circuit is coupled to the input of the third mixer; and the fourth output of the DAC circuit is coupled to the input of the fourth mixer.

20. A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: at least four DACs; and a plurality of switches coupled to the outputs of the at least four DACs, such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first group of one or more frequency bands, and is configured as an interleaved DAC circuit having at least two channels for a second group of one or more frequency bands different from the first group of one or more frequency bands.

21. The DAC circuit according to claim 20, wherein the first group of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second group of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

22. The DAC circuit according to claim 20, wherein the first group of one or more frequency bands includes one or more Frequency Range 1 (FR1) frequency bands, and wherein the second group of one or more frequency bands includes one or more Frequency Range 2 (FR2) frequency bands.

23. The DAC circuit according to claim 20, wherein the DAC circuit is capable of operating as an intermediate frequency (IF) DAC circuit, and wherein the plurality of switches are coupled to the outputs of the at least four DACs such that the DAC circuit is capable of being reconfigured to have at least one real IF channel.

24. A method of wireless communication, the method comprising: configuring a digital-to-analog converter (DAC) circuit in a first configuration configured to support at least four channels; converting a plurality of first digital signals into a plurality of first analog signals using the DAC circuit in the first configuration; configuring the DAC circuit in a second configuration configured to support at least one channel but less than four channels; and converting a plurality of second digital signals into one or more second analog signals using the DAC circuit in the second configuration.

25. The method according to claim 24, wherein the plurality of first digital signals are in a first set of one or more frequency bands, and wherein the plurality of second digital signals are in a second set of one or more frequency bands different from the first set of one or more frequency bands.

26. The method according to claim 25, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and wherein the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

27. The method according to claim 25, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and wherein the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

28. The method according to claim 24, wherein the DAC circuit includes a plurality of switches coupled to the outputs of at least four DACs, and wherein configuring the DAC circuit in the second configuration includes: selectively closing a first set of the plurality of switches; and selectively opening a second set of the plurality of switches, the second set of switches being different from the first set of the plurality of switches.

29. The method according to claim 28, wherein: the selectively closing includes selectively closing the first set of the plurality of switches for a first interval; the selectively opening includes selectively opening the second set of the plurality of switches for the first interval; and configuring the DAC circuit in the second configuration further includes: selectively closing a third set of the plurality of switches for a second interval, the third set of switches being different from the first set of the plurality of switches; and selectively opening a fourth set of the plurality of switches for the second interval, the fourth set of switches being different from the second set of the plurality of switches.

30. The method according to claim 24, wherein the plurality of second digital signals include intermediate frequency (IF) digital signals, wherein the DAC circuit includes at least four DACs capable of operating as an IF DAC, and wherein the at least one channel includes at least one real IF channel.

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