A method and system for monitoring finished product of computing and processing module

Abstract

The present invention relates to the technical field of integrated circuit board finished product detection, and more specifically, to a method and system for monitoring finished computing and processing modules. A linear array laser scanner disposed above a finished product conveyor belt is used to scan multiple finished computing and processing modules passing on the finished product conveyor belt in real time, thereby obtaining a spectral pattern corresponding to each finished computing and processing module; local spectral patterns corresponding to multiple chip components are identified in the spectral pattern; and each local spectral pattern is sequentially detected to determine whether there is a planar defect. If so, the damaged surface of the planar defect is evaluated, and the degree of damage to the damaged chip component is evaluated based on the proportion of the damaged surface. The monitoring method described in the present invention generates a spectral pattern representing height information in real time through a linear array laser scanner, combines RGB color thresholds with an image feature extraction algorithm, accurately identifies local areas of multiple chip components, effectively avoids interference caused by the dense arrangement of multiple components, and improves the positioning accuracy and noise resistance of planar defect detection.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit board finished product detection, and in particular to a method and system for monitoring finished product of a computing processing module. Background Art

[0002] With the increasing integration of electronic devices, the production quality inspection of finished computing and processing modules faces higher requirements. Traditional inspection methods rely heavily on manual visual inspection or single-vision technology. For example, conventional machine vision is used to inspect the complete number of chip components on a circuit board. Manual inspection is inefficient and susceptible to subjective factors. Traditional machine vision technology is not sensitive enough to planar defects with small height differences (such as minor scratches and warpage). This makes it difficult to accurately locate local defects, especially in scenarios where multiple chip components are densely arranged. It also makes it difficult to identify products with minor defects (such as chips with slight edge damage but normal functionality). Consequently, products with minor defects are directly judged as unqualified, resulting in a waste of resources. Summary of the Invention

[0003] The purpose of the present invention is to provide a method and system for monitoring finished products of a computing and processing module, so as to improve the above-mentioned problem that it is difficult to accurately locate and analyze local defects based on machine vision.

[0004] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, an embodiment of the present application provides a method for monitoring finished computing and processing modules, the method comprising: using a linear array laser scanner disposed above a finished product conveyor belt to scan multiple finished computing and processing modules passing through the finished product conveyor belt in real time, thereby obtaining a spectral pattern corresponding to each finished computing and processing module product, wherein the color in the spectral pattern is used to characterize the height information of the upper surface of the finished computing and processing module product, wherein the finished computing and processing module product comprises a PCB board and multiple chip components disposed on the PCB board; identifying local spectral patterns corresponding to the multiple chip components in the spectral pattern based on preset multiple RGB color thresholds combined with a color-based image feature extraction algorithm; sequentially detecting whether each local spectral pattern has a planar defect, and if so, evaluating the damaged surface of the planar defect, and evaluating the degree of damage of the damaged chip component based on the proportion of the damaged surface; if the degree of damage is lower than a preset threshold, testing the functional parameters corresponding to the damaged chip component, and determining that the corresponding finished computing and processing module product is a slightly defective product when all the functional parameters are within the preset threshold range.

[0006] Optionally, each local spectral pattern is detected to determine whether a planar defect exists. If so, the damage surface of the planar defect is evaluated, including:

[0007] The color-based image feature extraction algorithm identifies multiple non-planar texture features in the local spectral pattern and eliminates the standard non-planar texture features, thereby obtaining multiple non-planar texture features corresponding to the planar defects, which are recorded as defect texture features.

[0008] Based on the geometric features of defect texture features, multiple defect texture features are divided into stripe defect texture features and block defect texture features;

[0009] Sequentially segmenting the strip defect texture feature according to a preset horizontal or vertical unit length to obtain a plurality of unit strip defect texture features, constructing segmentation lines based on both ends of the unit strip defect texture feature, and then segmenting the unit strip defect texture feature into an upward convex texture curve and / or a downward convex texture curve;

[0010] Calculating a translation amount of the upper convex texture curve and / or the lower convex texture curve in the normal direction of the segmentation line based on the convexity of the upper convex texture curve and / or the lower convex texture curve, and obtaining a unit strip defect texture feature after translation correction based on the translation amount;

[0011] A rectangular surface of unit length is constructed based on the highest point and lowest point of the unit strip defect texture feature after translation correction. Multiple rectangular surfaces of unit length constitute the damage surface corresponding to the strip defect texture feature, where the heights of the upper and bottom sides of the rectangular surface correspond to the highest point and the lowest point respectively.

[0012] Optionally, after the plurality of defect texture features are divided into stripe defect texture features and block defect texture features, the method further includes:

[0013] A virtual defect cavity is constructed based on the color gradient change of the shape defect texture characteristics, and a depth vertical reference line is constructed based on the deepest point in the virtual defect cavity;

[0014] Taking the depth vertical reference line as the rotation axis, multiple first correction points are found in the upper edge curve of the virtual defect cavity according to the preset unit angle, and the cross-sectional magnification coefficient of the virtual defect cavity at the first correction point is calculated based on the horizontal distance from each first correction point to the depth vertical reference line. Based on the corrected cross-sections corresponding to the multiple first correction points, the second virtual defect cavity is reconstructed, and then the damage surface and damage depth corresponding to the block-type defect texture characteristics are obtained.

[0015] Optionally, the damage degree of the damaged chip component is assessed based on the damage surface ratio, including:

[0016] Determining packaging parameters corresponding to the current chip component based on position information of the local spectral pattern in the spectral pattern, wherein the packaging parameters include SMD packaging layer thickness and chip size parameters;

[0017] Construct a high-risk cover layer corresponding to the chip component based on chip size parameters and SMD package layer thickness, and divide the risk area and risk thickness threshold on the chip component surface based on the high-risk cover layer;

[0018] Marking the portion of the damage surface corresponding to the stripe defect texture feature that is located within the risk zone divided on the upper surface as the first damage surface;

[0019] Marking the portion of the damage surface corresponding to the stripe defect texture feature that is not located in the risk zone divided on the upper surface as the second damage surface;

[0020] When the damage depth of the second virtual defect cavity is less than the risk thickness threshold, the simulated volume of the second virtual defect cavity is calculated based on the damage surface and damage depth corresponding to the block-type defect texture feature;

[0021] The damage degree of the damaged chip component is comprehensively evaluated through a weighted algorithm based on the proportion of the first damaged surface in the upper surface of the chip component, the proportion of the second damaged surface in the upper surface of the chip component, and the proportion of the simulated volume in the entire non-high-risk covering layer volume.

[0022] In a second aspect, this embodiment provides a finished product monitoring system for a computing and processing module, the system comprising:

[0023] The first computing module is configured to scan multiple computing and processing module finished products passing on the finished product conveyor belt in real time using a linear array laser scanner disposed above the finished product conveyor belt, thereby obtaining a spectral pattern corresponding to each computing and processing module finished product. The colors in the spectral pattern are used to represent height information of the upper surface of the computing and processing module finished product.

[0024] An identification module is used to identify local spectral patterns corresponding to multiple chip components in the spectral pattern based on multiple preset RGB color thresholds combined with a color-based image feature extraction algorithm;

[0025] The judgment module is used to detect whether there is a planar defect in each local spectral pattern in turn. If so, the damaged surface of the planar defect is evaluated, and the degree of damage of the damaged chip component is evaluated based on the proportion of the damaged surface. If the degree of damage is lower than the preset threshold, the functional parameters corresponding to the damaged chip component are tested, and when the functional parameters are all within the preset threshold range, the corresponding computing and processing module finished product is determined to be a slightly defective product.

[0026] The beneficial effects of the present invention are:

[0027] The present invention uses a linear array laser scanner to generate a spectral pattern representing height information in real time. Combining RGB color thresholds with an image feature extraction algorithm, it accurately identifies local areas of multiple chip components, effectively avoiding interference caused by densely arranged components and improving the positioning accuracy and noise resistance of plane defect detection.

[0028] Secondly, a dual judgment mechanism of damage surface ratio and functional parameter testing is adopted to verify electrical performance while detecting appearance defects, avoiding the misjudgment and scrapping of slightly defective products with intact functions, significantly reducing production costs and resource waste.

[0029] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the embodiments of the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 It is a flow chart of a method for monitoring finished products of a computing and processing module described in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0033] It should be noted that similar reference numerals or letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0034] Embodiment 1:

[0035] like Figure 1As shown, this embodiment provides a method for monitoring finished products of a computing processing module, which includes step S100, step S200, step S300 and step S400.

[0036] Step S100: Scanning multiple finished computing and processing module products passing on the finished product conveyor belt in real time using a linear array laser scanner positioned above the finished product conveyor belt, thereby obtaining a spectral pattern corresponding to each finished computing and processing module product. The colors in the spectral pattern are used to represent height information of the top surface of the finished computing and processing module product. The finished computing and processing module product includes a PCB and multiple chip components disposed on the PCB.

[0037] Step S200: identifying local spectral patterns corresponding to multiple chip components in the spectral pattern based on a plurality of preset RGB color thresholds combined with a color-based image feature extraction algorithm;

[0038] Step S300: Check each local spectral pattern in turn to see if there is a planar defect. If so, evaluate the damage surface of the planar defect and evaluate the damage degree of the damaged chip component based on the damage surface ratio. The specific implementation method is as follows:

[0039] Step S310: Using a color-based image feature extraction algorithm to identify multiple non-planar texture features in the local spectral pattern, and eliminating standard non-planar texture features, multiple non-planar texture features corresponding to planar defects are obtained, which are recorded as defect texture features. When obvious defects appear on the surface of a chip component, they are generally divided into two types: one is a stripe defect corresponding to a crack, and the other is a block defect caused by a small piece of material falling off, which appears as a stripe or block of different color bands in the spectral pattern.

[0040] Step S320: Based on the geometric features of the defect texture features, the multiple defect texture features are divided into stripe defect texture features and block defect texture features. The processing logic of the stripe defect texture features and the block defect texture features are completely different.

[0041] 1. The processing method for stripe defect texture features is:

[0042] Step S330: Segment the strip defect texture feature sequentially according to a preset horizontal or vertical unit length to obtain a plurality of unit strip defect texture features. Segmentation lines are constructed based on the two end points of the unit strip defect texture feature, and the unit strip defect texture feature is further segmented into an upper convex texture curve and / or a lower convex texture curve. The convexity of the upper convex texture curve and / or the lower convex texture curve is subsequently adjusted based on the degree of convexity of the curve, thereby increasing the construction of the damage surface so that the damage surface can better reflect the impact of the strip crack on the chip component.

[0043] Step S340: Calculating the translation amount of the upper convex texture curve and / or the lower convex texture curve in the normal direction of the segmentation line based on the protrusion degree of the upper convex texture curve and / or the lower convex texture curve, and performing a translation operation on the upper convex texture curve and / or the lower convex texture curve based on the translation amount, thereby obtaining a unit strip defect texture feature after translation correction;

[0044] The calculation method for calculating the translation amount of the upper convex texture curve and / or the lower convex texture curve in the normal direction of the segmentation line based on the convexity of the upper convex texture curve and / or the lower convex texture curve may be:

[0045] Represent this curve segment as a discrete sequence of curve points: , N is the total number of curve points, is the coordinate of point i;

[0046] Translation vector calculation formula: ;

[0047] Where T is the translation vector, is the proportionality coefficient, is the curvature of the i-th point; is the normal direction of point i;

[0048] ; is the index of the maximum curvature point, that is, the index of the point with the largest absolute value of curvature; is the first-order derivative of the curve at point i, is the second-order derivative of the curve at point i, To find the parameters that maximize the subsequent expression;

[0049] ;in, is the curvature of the i-th point; is the normal direction of point i, is the first-order derivative of the point with the largest absolute value of curvature, which is used to calculate the curvature and normal direction. is the second-order inverse of the point with the largest absolute value of curvature, for The component in the y-axis direction, for The component in the x-axis direction, Indicates rotating the tangent vector at the point with the largest absolute value of curvature 90° counterclockwise;

[0050] Step S350: Construct a rectangular surface of unit length based on the highest point and lowest point of the unit strip defect texture feature after translation correction. The rectangular surface is the unit damage surface corresponding to the unit strip defect texture feature. Multiple rectangular surfaces of unit length constitute the damage surface corresponding to the strip defect texture feature, wherein the heights of the upper and lower sides of the rectangular surface correspond to the highest point and the lowest point, respectively.

[0051] 2. The processing methods for blocky defect texture features can be:

[0052] Step S360: constructing a virtual defect cavity based on the color gradient change of the shape defect texture feature, and constructing a depth vertical reference line based on the deepest point in the virtual defect cavity, wherein the depth vertical reference line is perpendicular to the upper surface of the chip component;

[0053] Step S370: Using the depth vertical reference line as the rotation axis, find multiple first correction points in the upper edge curve of the virtual defect cavity according to a preset unit angle, calculate the cross-sectional magnification coefficient of the virtual defect cavity at the first correction point based on the horizontal distance from each first correction point to the depth vertical reference line, and reconstruct the second virtual defect cavity based on the corrected cross-sections corresponding to the multiple first correction points, thereby obtaining the damage surface and damage depth corresponding to the block-type defect texture feature.

[0054] Based on the damage evaluation method of the above-mentioned stripe defect texture characteristics and block defect texture characteristics, the comprehensive damage degree evaluation method can be:

[0055] Step S380: determining packaging parameters corresponding to the current chip component based on the position information of the local spectral pattern in the spectral pattern, wherein the packaging parameters include SMD packaging layer thickness and chip size parameters;

[0056] Step S390: construct a high-risk cover layer corresponding to the chip component based on the chip size parameters and the SMD package layer thickness, and divide the high-risk cover layer on the upper surface of the chip component into a risk area and a risk thickness threshold, wherein the risk area is the vertical mapping area of ​​the high-risk cover layer on the upper surface of the chip component, and the risk thickness threshold is the thickness value obtained by subtracting the minimum protective layer thickness from the SMD package layer thickness, wherein the minimum protective layer thickness of the chip is calculated based on the chip size parameters through a preset working condition simulation experiment. These parameters can be written into the detection device through experiments before production;

[0057] Step S3100: Mark the portion of the damage surface corresponding to the stripe defect texture feature that is located within the risk zone divided on the upper surface as a first damage surface;

[0058] Step S3110: Mark the portion of the damage surface corresponding to the stripe defect texture feature that is not located in the risk zone divided on the upper surface as a second damage surface;

[0059] Step S3120: When the damage depth of the second virtual defect cavity is less than the risk thickness threshold, a simulated volume of the second virtual defect cavity is calculated based on the damage surface and damage depth corresponding to the block-type defect texture feature. The second virtual defect cavity is a virtual inverted cone-shaped cavity with a top surface as the damage surface and a depth as the damage depth. The simulated volume is the volume of the inverted cone-shaped cavity. The simulated volume is calculated by bringing the constructed second virtual defect cavity model into AutoCAD Civil 3D for calculation.

[0060] Step S3130: Based on the proportion of the first damaged surface in the upper surface of the chip component, the proportion of the second damaged surface in the upper surface of the chip component, and the proportion of the simulated volume in the entire non-high-risk covering layer volume, a weighted algorithm is used to comprehensively evaluate the damage degree of the damaged chip component. The non-high-risk covering layer is the area in the chip component excluding the high-risk covering layer.

[0061] Step S400: If the damage level is lower than a preset threshold, then the functional parameters corresponding to the damaged chip component are tested, and if all the functional parameters are within the preset threshold range, the corresponding computing processing module finished product is determined to be a slightly defective product;

[0062] If the degree of damage is greater than or equal to the preset threshold, it is directly judged as a defective product. Most of these cracks or defects are concentrated in the risk area. Even if the functional test is passed, there is still a greater risk of failure during later use compared to normal processors.

[0063] Example 2:

[0064] This embodiment provides a finished product monitoring system for computing and processing modules, the system comprising:

[0065] The first computing module is configured to scan multiple computing and processing module finished products passing on the finished product conveyor belt in real time using a linear array laser scanner disposed above the finished product conveyor belt, thereby obtaining a spectral pattern corresponding to each computing and processing module finished product. The colors in the spectral pattern are used to represent height information of the upper surface of the computing and processing module finished product.

[0066] An identification module is used to identify local spectral patterns corresponding to multiple chip components in the spectral pattern based on multiple preset RGB color thresholds combined with a color-based image feature extraction algorithm;

[0067] A determination module is used to sequentially detect whether there is a planar defect in each local spectral pattern. If so, the damage surface of the planar defect is evaluated, and the degree of damage to the damaged chip component is evaluated based on the proportion of the damaged surface;

[0068] If the degree of damage is lower than a preset threshold, the functional parameters corresponding to the damaged chip component are tested, and if the functional parameters are all within the preset threshold range, the corresponding computing processing module finished product is determined to be a slightly defective product.

[0069] It should be noted that, regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0070] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for monitoring finished product of a computing and processing module, characterized in that: The method includes: using a linear array laser scanner disposed above a finished product conveyor belt to scan multiple finished computing and processing module products passing through the finished product conveyor belt in real time, thereby obtaining a spectral pattern corresponding to each finished computing and processing module product, wherein the colors in the spectral pattern are used to represent height information of the upper surface of the finished computing and processing module product, wherein the finished computing and processing module product includes a PCB board and multiple chip components disposed on the PCB board; identifying local spectral patterns corresponding to the multiple chip components in the spectral pattern based on a combination of preset multiple RGB color thresholds and a color-based image feature extraction algorithm; sequentially detecting whether each local spectral pattern has a planar defect; if so, evaluating the damaged surface of the planar defect and evaluating the degree of damage of the damaged chip component based on the proportion of the damaged surface; if the degree of damage is lower than a preset threshold, testing the functional parameters corresponding to the damaged chip component, and determining that the corresponding finished computing and processing module product is a slightly defective product if all the functional parameters are within the preset threshold range; Secondly, each local spectral pattern is detected to see if there is a planar defect. If so, the damage surface of the planar defect is evaluated, including: identifying multiple non-planar texture features in the local spectral pattern based on the color-based image feature extraction algorithm, and eliminating the standard non-planar texture features, thereby obtaining multiple non-planar texture features corresponding to the planar defect, which are recorded as defect texture features; based on the geometric features of the defect texture features, the multiple defect texture features are divided into strip defect texture features and block defect texture features; the strip defect texture features are segmented in turn according to the preset horizontal or vertical unit length to obtain multiple unit strip defect texture features, based on the unit strip defect texture features. A segmentation line is constructed at both ends of the defect texture feature, and then the unit strip defect texture feature is segmented into an upper convex texture curve and / or a lower convex texture curve; the translation amount of the upper convex texture curve and / or the lower convex texture curve in the normal direction of the segmentation line is calculated based on the convexity of the upper convex texture curve and / or the lower convex texture curve, and the unit strip defect texture feature after translation correction is obtained based on the translation amount; a rectangular surface of unit length is constructed based on the highest point and the lowest point of the unit strip defect texture feature after translation correction, and multiple rectangular surfaces of unit length constitute the damage surface corresponding to the strip defect texture feature, wherein the heights of the upper side and the bottom side of the rectangular surface correspond to the highest point and the lowest point respectively.

2. The method for monitoring finished product of computing and processing modules according to claim 1, characterized in that: After dividing multiple defect texture features into strip defect texture features and block defect texture features, the method also includes: constructing a virtual defect cavity based on the color gradient change of the strip defect texture features, and constructing a depth vertical reference line based on the deepest point in the virtual defect cavity; using the depth vertical reference line as the rotation center axis, finding multiple first correction points in the upper edge curve of the virtual defect cavity according to a preset unit angle, and calculating the cross-sectional magnification coefficient of the virtual defect cavity at the first correction point based on the horizontal distance from each first correction point to the depth vertical reference line, and reconstructing a second virtual defect cavity based on the corrected cross-sections corresponding to the multiple first correction points, thereby obtaining the damage surface and damage depth corresponding to the block defect texture features.

3. The method for monitoring finished product of computing and processing modules according to claim 2, characterized in that: The damage degree of a damaged chip component is assessed based on the proportion of a damaged surface, including: determining the packaging parameters corresponding to the current chip component based on the position information of a local spectral pattern in the spectral pattern, the packaging parameters including the thickness of an SMD packaging layer and chip size parameters; constructing a high-risk covering layer corresponding to the chip component based on the chip size parameters and the thickness of the SMD packaging layer, and dividing the risk area and risk thickness threshold on the upper surface of the chip component based on the high-risk covering layer; marking the portion of the damage surface corresponding to the strip defect texture feature that is located within the risk area divided on the upper surface as a first damage surface; marking the portion of the damage surface corresponding to the strip defect texture feature that is not located within the risk area divided on the upper surface as a second damage surface; when the damage depth of a second virtual defect cavity is less than the risk thickness threshold, calculating the simulated volume of the second virtual defect cavity based on the damage surface and damage depth corresponding to the block-type defect texture feature; and comprehensively assessing the damage degree of the damaged chip component through a weighted algorithm based on the proportion of the first damage surface in the upper surface of the chip component, the proportion of the second damage surface in the upper surface of the chip component, and the proportion of the simulated volume in the entire non-high-risk covering layer volume.

4. A finished product monitoring system for a computing and processing module, characterized in that: The system includes: a first computing module, configured to scan multiple computing and processing module finished products passing on a finished product conveyor belt in real time using a linear array laser scanner disposed above the finished product conveyor belt, thereby obtaining a spectral pattern corresponding to each computing and processing module finished product, wherein the colors in the spectral pattern are used to characterize height information of the upper surface of the computing and processing module finished product; an identification module, configured to identify local spectral patterns corresponding to multiple chip components in the spectral pattern based on preset multiple RGB color thresholds in combination with a color-based image feature extraction algorithm; a determination module, configured to sequentially detect whether each local spectral pattern has a planar defect; if so, evaluate the damaged surface of the planar defect and evaluate the degree of damage of the damaged chip component based on the proportion of the damaged surface; if the degree of damage is lower than a preset threshold, test the functional parameters corresponding to the damaged chip component, and determine that the corresponding computing and processing module finished product is a slightly defective product if the functional parameters are all within the preset threshold range.

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