Channel decoding method, device, electronic device and storage medium

Abstract

This application discloses a channel decoding method, apparatus, electronic device, and storage medium. The method comprises: obtaining log-likelihood ratio information to be decoded; obtaining a preset decoding instruction sequence; and decoding the log-likelihood ratio information according to the decoding instruction sequence, outputting decoded bit information. This application can implement automated channel decoding based on the decoding instruction sequence, improving decoding efficiency, accuracy, and flexibility, reducing costs, and reducing hardware resource usage. The application is widely applicable to the field of channel coding and decoding technology.

Description

Technical Field

[0001] The present application relates to the field of channel coding technology, and in particular to a channel decoding method, device, electronic device and storage medium. Background Art

[0002] In the 5G protocol of mobile communication networks, communication systems (such as the Star Flash system) mostly use polarization codes as the coding scheme for control channels. The transmitting device determines the segmentation and number of segments based on parameters associated with the encoding of information bits, encodes the information bits according to the number of check bits, and sends the encoded information bits (polarization code encoded data) to the receiving device.

[0003] Existing solutions usually design and use a dedicated decoding accelerator to decode the encoded information bits after the receiving device receives them. However, the decoding accelerator often has complex algorithms, cannot be changed after the design is completed, has poor flexibility, and has high design costs, occupies a lot of hardware resources, and has low hardware utilization. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a channel decoding method, device, electronic device and storage medium, which can realize automatic log-likelihood ratio information decoding and improve the efficiency and accuracy of decoding.

[0005] On the one hand, an embodiment of the present application provides a channel decoding method, the method comprising the following steps:

[0006] Obtaining log-likelihood ratio information to be decoded;

[0007] Obtaining a preset decoding instruction sequence;

[0008] According to the decoding instruction sequence, the log-likelihood ratio information is decoded and decoded bit information is output.

[0009] In some embodiments, the method further comprises:

[0010] Constructing a soft decision metric graph structure template, wherein the soft decision metric graph structure template includes soft decision metric input information, soft decision metric output information, and decoding processing instruction information;

[0011] According to the soft decision metric graph structure template, a corresponding hard decision metric graph structure template is generated.

[0012] In some embodiments, obtaining the log-likelihood ratio information to be decoded specifically includes:

[0013] Obtaining polar code encoded signals;

[0014] processing the polar code coded signal to generate a soft decision input sequence;

[0015] According to a preset decoding path state and the soft decision metric graph structure template, the soft decision input sequence is decoded to generate a corresponding soft decision metric graph structure, and the soft decision metric graph structure is used as the log-likelihood ratio information.

[0016] In some embodiments, obtaining a preset decoding instruction sequence specifically includes:

[0017] Get the current decoding processing path;

[0018] The decoding instruction sequence is generated according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template.

[0019] In some embodiments, decoding the log-likelihood ratio information according to the decoding instruction sequence and outputting decoded bit information specifically includes:

[0020] Generating a hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template;

[0021] Sequentially acquiring each decoding instruction in the decoding instruction sequence, and determining, based on each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction;

[0022] Reading corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and reading the corresponding target decoding processing instruction according to the decoding processing instruction position;

[0023] Decoding the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction;

[0024] According to the data write position corresponding to each decoding instruction, a first data write position is determined from the soft decision metric graph structure, a second data write position is determined from the hard decision metric graph structure, the soft decision bit information is written to the first data write position, and the hard decision bit information is written to the second data write position.

[0025] In some embodiments, decoding the soft decision input sequence according to the preset decoding path state and the soft decision metric graph structure template to generate the corresponding soft decision metric graph structure specifically includes:

[0026] Decoding the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and outputting corresponding soft decision sequence decoding information;

[0027] Obtaining a data writing location of the soft decision metric input information in the soft decision metric graph structure template;

[0028] The soft decision metric graph structure template is updated according to the soft decision sequence decoding information and the data writing position to generate the soft decision metric graph structure.

[0029] In some embodiments, sequentially acquiring each decoding instruction in the decoding instruction sequence and determining, based on each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction specifically include:

[0030] Obtaining an entry instruction in the decoding instruction sequence as a current decoding instruction;

[0031] Performing instruction parsing on the current decoding instruction to determine a current data reading position, a current decoding processing instruction position, and a current data writing position;

[0032] When the current decoded instruction is the termination instruction in the decoded instruction sequence, stopping instruction parsing;

[0033] When the current decoding instruction is not the termination instruction, the next instruction of the current decoding instruction is obtained as the current decoding instruction, and then the step of performing instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position and the current data writing position is returned.

[0034] On the other hand, an embodiment of the present application provides a channel decoding device, the device comprising:

[0035] The first module is used to obtain log-likelihood ratio information to be decoded;

[0036] The second module is used to obtain a preset decoding instruction sequence;

[0037] The third module is used to decode the log-likelihood ratio information according to the decoding instruction sequence and output decoded bit information.

[0038] On the other hand, an embodiment of the present application provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor implements the channel decoding method described above when executing the computer program.

[0039] On the other hand, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the channel decoding method described above is implemented.

[0040] Embodiments of the present application include at least the following beneficial effects: A channel decoding method, apparatus, electronic device, and storage medium provided herein obtain log-likelihood ratio information to be decoded, obtain a preset decoding instruction sequence, perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence, and output decoded bit information. The present application can implement automated channel decoding based on the decoding instruction sequence, improve decoding efficiency, accuracy, and flexibility, reduce costs, and minimize hardware resource usage. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 This is a flow chart of a channel decoding method provided by an embodiment of the present application;

[0044] Figure 2 This is a schematic diagram of the structure of Polar decoding in an embodiment of the present application;

[0045] Figure 3 is a schematic diagram of the register arrangement in an embodiment of the present application;

[0046] Figure 4 This is a flowchart of step S303 in the embodiment of the present application;

[0047] Figure 5 This is a flowchart of step S103 in the embodiment of the present application;

[0048] Figure 6 This is a schematic diagram of the decoding process in the embodiment of the present application;

[0049] Figure 7 This is another schematic diagram of the decoding process in the embodiment of the present application;

[0050] Figure 8 This is a flowchart of step S502 in an embodiment of the present application;

[0051] Figure 9 1 is a schematic structural diagram of a channel decoding device provided in an embodiment of the present application;

[0052] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0054] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0055] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0057] Before explaining the embodiments of the present application in detail, some of the nouns and terms involved in the embodiments of the present application are first explained. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0058] 1) ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed specifically for a specific application. Unlike general-purpose integrated circuits, ASICs are custom designed to meet the needs of specific applications, typically offering higher performance and lower power consumption.

[0059] 2) RISC-V: RISC-V is an open source instruction set architecture (ISA).

[0060] 3) LLR: Log Likelihood Ratio: In mathematics and communications, LLR is the abbreviation of log likelihood ratio. It is often used in communication algorithms to achieve soft demodulation by calculating the log likelihood ratio.

[0061] In the 5G protocol of mobile communication networks, Polar codes are selected as the coding scheme for control channels. For example, the Polar coding method involved in 3GPP TS38.212 is used for channels PBCH, PDCCH, PUCCH, and PUSCH.

[0062] For the relatively low data throughput control channel (PDCCH), after the receiving device receives the encoded information bits (i.e., the polar code signal) transmitted by the transmitter, most existing solutions rely on designing dedicated decoding accelerators to decode the encoded information bits. However, the algorithms of dedicated decoding accelerators (such as the CASCL series) are complex, and the corresponding ASIC solutions cannot be modified after design, resulting in poor flexibility, high design costs, high hardware resource usage, and low hardware utilization.

[0063] Based on this, the embodiments of the present application propose a channel decoding method, device, electronic device and storage medium, which generate typical operation functions in the polar decoder into RISC-V custom instructions, optimize the register arrangement in the polar decoder, and realize automatic decoding of the polar decoder based on custom instructions and decoding instruction sequences, thereby improving the efficiency and accuracy of decoding.

[0064] Reference Figure 1 , Figure 1 This is an optional flow chart of a channel decoding method provided in an embodiment of the present application. The method may include but is not limited to steps S101 to S103:

[0065] Step S101, obtaining log-likelihood ratio information to be decoded;

[0066] Step S102, obtaining a preset decoding instruction sequence;

[0067] Step S103: Decode the log-likelihood ratio information according to the decoding instruction sequence and output decoded bit information.

[0068] In some embodiments, the above method further includes steps S201 to S202:

[0069] Step S201: construct a soft decision metric graph structure template, where the soft decision metric graph structure template includes soft decision metric input information and soft decision metric output information;

[0070] Step S202: Generate a corresponding hard decision metric graph structure template according to the soft decision metric graph structure template.

[0071] In step S102 of some embodiments, optionally, a current decoding processing path is obtained, and a decoding instruction sequence is generated according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template, and the decoding instruction sequence is stored in a general register.

[0072] Take N=8: codeword length (8 bits), n=3: polarization level as an example, refer to Figure 2 Polar decoding consists of N decoding trees. The essence of the decoding tree is to realize the bit-by-bit decision of the polar code through multi-level LLR merging. Each decoding tree corresponds to the decision process of one bit. The black dotted box represents the first decoding tree. The other decoding trees have similar structures but different input dependencies.

[0073] Taking the bit decision of the first decoding tree as an example, its operation direction is from right to left. The specific steps are as follows:

[0074] 1) Input LLR sequence: The rightmost node receives the LLR values ​​output by 8 channels;

[0075] 2) Recursive LLR calculation:

[0076] Step 1 (rightmost): Initial LLRs come directly from the channel (e.g. );

[0077] Step 2: Merge adjacent LLRs through butterfly operation (e.g.: );

[0078] Step 3: Further merge to obtain the final LLR used to judge u1 (such as );

[0079] 3) Bit decision (white circle on the far left): Based on The sign decision u1: If ≥0, u1 is judged to be 0 (the frozen bit is fixed to 0), if <0, u1 is judged as 1;

[0080] 4) Bit-by-bit advancement: After the judgment of u1 is completed, its value will be used in the LLR calculation of subsequent bits (u2 to u8).

[0081] The complete decoding process (N=8) is:

[0082] Step 1, initialization: receive all channel LLRs;

[0083] Step 2: Decode bit by bit: Execute the following steps for u1 to u8:

[0084] Calculate the LLR of the current bit along the corresponding decoding tree; make a decision based on the frozen bit information; c. Feed the decision value back to the LLR calculation of subsequent bits;

[0085] Step 3: Information output: restore the original information bit sequence.

[0086] Then, according to the decoding process of the polar decoding, that is, the current decoding processing path, combined with the register arrangement structure of the internal registers in the polar decoder, a decoding instruction sequence is generated, wherein the register arrangement structure includes a hard decision metric graph structure template and a soft decision metric graph structure template.

[0087] According to the current decoding processing path, the corresponding hard decision metric graph structure template and soft decision metric graph structure template are generated. For example, referring to Figure 3 The hard decision metric graph structure template is the bit matrix in the internal register, and the soft decision metric graph structure template is the LLR matrix in the internal register. In the LLR matrix, each matrix unit stores the LLR represented by a signed integer, with a quantization bit number of N bits, where N is a positive integer. Its specific value can be set by the user, generally between 4 and 12. The receiver demodulates the polar code coded signal and calculates the log-likelihood ratio (LLR) of each bit to form an LLR matrix. The LLR matrix provides reliability information (soft information) for each bit, which is recursively combined and transmitted by the decoder. In the bit matrix, each matrix unit stores a quantization bit number of 1 bit. The decoder generates a hard decision result bit by bit based on the LLR matrix and the structure of the polar code (such as the frozen bit position). The bit matrix is ​​used to store this hard decision result, including the final decoded bit sequence or the temporary decision value of the intermediate bit.

[0088] In some embodiments, step S101 may include but is not limited to steps S301 to S303:

[0089] Step S301: obtaining a polar code signal;

[0090] Step S302: Process the polar code signal to generate a soft decision input sequence;

[0091] Step S303 : decoding the soft decision input sequence according to the preset decoding path state and the soft decision metric graph structure template, generating a corresponding soft decision metric graph structure, and using the soft decision metric graph structure as log likelihood ratio information.

[0092] In some embodiments, optionally, a polar code coded signal is received and demodulated to obtain soft bit or symbol-level probability information. Based on the soft bit or symbol-level probability information, LLRs are calculated using a channel model, and a corresponding LLR sequence (i.e., the soft decision input sequence) is output. The LLR sequence is input into a decoder for polar code decoding. A corresponding LLR matrix (i.e., the soft decision metric graph structure) is generated based on a preset decoding path state and a soft decision metric graph structure template. The soft decision metric graph structure is used as log-likelihood ratio information to be decoded.

[0093] In some embodiments, reference Figure 4 , Figure 4 This is an optional flowchart of step S303 in the embodiment of the present application. Step S303 may include but is not limited to steps S401 to S403:

[0094] Step S401: Decode the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and output corresponding soft decision sequence decoding information;

[0095] Step S402, obtaining the data writing location of the soft decision metric input information in the soft decision metric graph structure template;

[0096] Step S403: updating the soft decision metric graph structure template according to the soft decision sequence decoding information and the data writing position, and generating a soft decision metric graph structure.

[0097] In some embodiments, the soft decision sequence decoding information (such as ), written into the corresponding data writing position in the soft decision metric graph structure template, completes data filling, and generates the soft decision metric graph structure.

[0098] In some embodiments, reference Figure 5 , Figure 5 This is an optional flowchart of step S103 in the embodiment of the present application. Step S103 may include but is not limited to steps S501 to S505:

[0099] Step S501, generating a hard decision metric graph structure corresponding to a soft decision metric graph structure according to a hard decision metric graph structure template;

[0100] Step S502, sequentially obtaining each decoding instruction in the decoding instruction sequence, and determining, based on each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction;

[0101] Step S503, reading corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and reading the corresponding target decoding processing instruction according to the decoding processing instruction position;

[0102] Step S504: Decoding the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction;

[0103] Step S505: According to the data write positions corresponding to the decoding instructions, a first data write position is determined from the soft decision metric graph structure, and a second data write position is determined from the hard decision metric graph structure. The soft decision bit information is written to the first data write position, and the hard decision bit information is written to the second data write position.

[0104] In some embodiments, the register can optionally execute a load / store instruction to load any content in the register into a general register or a dedicated register in the polar decoder. Specifically, refer to Figure 6 and Figure 7 First, the register executes the load instruction and reads the input data x and y from the LLR matrix according to the input data address, such as Addrx and Addry, and reads the input bit u from the Bit matrix according to the input bit address, such as Addru. Then, the decoder is used to decode the input data x and y, and output the hard decision bit information u_bit and the soft decision bit information u_LLR (such as the soft decision metric output information mentioned above). Finally, the register executes the store instruction and stores the hard decision bit information u_bit to the element corresponding to the input bit address Addru in the Bit matrix according to the input bit address Addru, and stores the soft decision bit information u_LLR to the element corresponding to the write data address Addr_out in the LLR matrix according to the write data address Addr_out.

[0105] In some embodiments, exemplary, the configuration of the decoding instruction is as follows:

[0106] 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7

[0107] idxBit / flagGF / addr_u / addr_a / addr_b / col_in / addr_o / col_out

[0108] Among them, idxBit is the decoded bit, pointing to the logical index of the leftmost column of the Bit matrix, which is used to identify the target bit of the current decoding operation. idxBit corresponds to the original N coded bits (including information bits and frozen bits) and is represented by n bits, where n = log2N. That is, idxBit is an n-bit binary number with a value range of 0 to N-1. For example, if N = 8 (n = 3), then idxBit∈{000,001,...,111} (decimal 0 to 7). The value of idxBit is directly mapped to the row number of the Bit matrix. For example, idxBit=3 points to the leftmost bit of the third row of the Bit matrix.

[0109] flag is the flag bit of the custom instruction (such as custom instruction G and custom instruction F), that is, the flag bit of the target decoding processing instruction, 1 bit;

[0110] addr_u is the address of input bit u (u is defined as the input bit of custom instruction G), which is used to read input bits from the Bit matrix;

[0111] addr_a is the row index of the LLR matrix, which is used to read input data from the LLR matrix;

[0112] addr_b is the row index of the LLR matrix, which is used to read input data from the LLR matrix;

[0113] addr_o is the row index of the LLR matrix, used to write output data;

[0114] col_in is the column index of the LLR matrix, used to read input data;

[0115] col_out is the column index of the LLR matrix, used to write output data.

[0116] In some embodiments, the above-mentioned custom instructions are generated based on the RISC-V instruction set or other instruction sets, and the custom instructions are stored in general registers. The custom instructions are related hardware instructions of the polar decoder. Optionally, the custom instructions include custom instructions G and custom instructions F, etc. Custom instruction F is used to implement nonlinear operations based on signs and minimum absolute values, and custom instruction G is used to implement linear combination operations based on conditional sign flipping.

[0117] The custom instruction F is as follows:

[0118] decF(Lc,Ld)=>La

[0119] Input Lc, 8 bits;

[0120] Input Ld, 8 bits;

[0121] Output La, 8 bits;

[0122] process:

[0123] signC=sign(Lc): Get the sign of Lc (such as +1 or -1);

[0124] signD=sign(Ld): obtain the sign of Ld (such as +1 or -1);

[0125] La=signC*signD*MIN(ABS(Lc),ABS(Ld)): MIN(ABS(Lc),ABS(Ld)) is used to take the smaller of the absolute values ​​of Lc and Ld.

[0126] The custom instruction G is as follows:

[0127] decG(Lc,Ld)=>La;

[0128] Input Lc, 8 bits;

[0129] Input Ld, 8 bits;

[0130] Input u, 1 bit;

[0131] Output Lb, 8bit;

[0132] process:

[0133] If u=0 sign T=1 else sign T= -1;

[0134] Lb=signT*Lc+Ld: Adjust the sign of Lc and add it to Ld.

[0135] In some embodiments, reference Figure 8 , Figure 8 This is an optional flowchart of step S502 in the embodiment of the present application. Step S502 may include but is not limited to steps S601 to S604:

[0136] Step S601, obtaining an entry instruction in a decoding instruction sequence as a current decoding instruction;

[0137] Step S602, performing instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position;

[0138] Step S603, when the current decoding instruction is the termination instruction in the decoding instruction sequence, instruction parsing is stopped;

[0139] Step S604: When the current decoding instruction is not the above-mentioned termination instruction, the next instruction of the current decoding instruction is obtained as the current decoding instruction, and then the process returns to the above-mentioned step S602.

[0140] In some embodiments, the decoded instruction sequence is stored in a dedicated register in the polar decoder. Assuming that the decoded instruction sequence includes instructions 1 to N, instructions 1 to N are executed sequentially. When the current decoded instruction is instruction N, instruction parsing is stopped.

[0141] Reference Figure 9 , Figure 9 : is an optional structural diagram of a channel decoding device provided in an embodiment of the present application. The device is used to implement the above-mentioned channel decoding method. The device may include:

[0142] The first module is used to obtain log-likelihood ratio information to be decoded;

[0143] The second module is used to obtain a preset decoding instruction sequence;

[0144] The third module is used to decode the log-likelihood ratio information according to the decoding instruction sequence and output the decoded bit information.

[0145] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0146] The present application also provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor implements the channel decoding method when executing the computer program. The electronic device can be any smart terminal including a tablet computer.

[0147] It can be understood that the contents of the above method embodiments are applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0148] See also Figure 10 , Figure 10 The hardware structure of an electronic device according to another embodiment is shown. The electronic device includes:

[0149] The processor 901 can be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0150] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called by the processor 901 to execute the channel decoding method of the embodiments of the present application.

[0151] Input / output interface 903, used to implement information input and output;

[0152] Communication interface 904, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0153] Bus 905 , which transmits information between various components of the device (e.g., processor 901 , memory 902 , input / output interface 903 , and communication interface 904 );

[0154] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0155] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned channel decoding method is implemented.

[0156] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiment, the functions specifically implemented by the present storage medium embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0157] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0158] The embodiments of the present application provide a channel decoding method, device, electronic device, and storage medium. These methods obtain log-likelihood ratio information to be decoded, obtain a preset decoding instruction sequence, decode the log-likelihood ratio information according to the decoding instruction sequence, and output decoded bit information. These methods can implement automated channel decoding based on the decoding instruction sequence, thereby improving decoding efficiency, accuracy, and flexibility, reducing costs, and reducing hardware resource usage.

[0159] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0160] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0161] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0162] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0163] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0164] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0166] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0167] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0168] It should be appreciated that embodiments of the present invention may be implemented or practiced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner according to the methods and drawings described in the specific embodiments. Each program may be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program may be implemented in assembly or machine language. In any case, the language may be a compiled or interpreted language. In addition, the program may be run on a programmed application-specific integrated circuit for this purpose.

[0169] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0170] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A channel decoding method, characterized in that: The method comprises the following steps: Obtaining log-likelihood ratio information to be decoded; Obtaining a preset decoding instruction sequence; Decoding the log-likelihood ratio information according to the decoding instruction sequence and outputting decoded bit information; The method further comprises: Constructing a soft decision metric graph structure template, wherein the soft decision metric graph structure template includes soft decision metric input information, soft decision metric output information, and decoding processing instruction information; Generating a corresponding hard decision metric graph structure template according to the soft decision metric graph structure template; The decoding process of the log-likelihood ratio information according to the decoding instruction sequence and outputting decoded bit information specifically includes: Generating a hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template; Sequentially acquiring each decoding instruction in the decoding instruction sequence, and determining, based on each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction; Reading corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and reading the corresponding target decoding processing instruction according to the decoding processing instruction position; Decoding the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction; According to the data write position corresponding to each decoding instruction, a first data write position is determined from the soft decision metric graph structure, a second data write position is determined from the hard decision metric graph structure, the soft decision bit information is written to the first data write position, and the hard decision bit information is written to the second data write position.

2. The channel decoding method according to claim 1, wherein: The obtaining of the log-likelihood ratio information to be decoded specifically includes: Obtaining polar code encoded signals; processing the polar code coded signal to generate a soft decision input sequence; According to a preset decoding path state and the soft decision metric graph structure template, the soft decision input sequence is decoded to generate a corresponding soft decision metric graph structure, and the soft decision metric graph structure is used as the log-likelihood ratio information.

3. The channel decoding method according to claim 1, wherein: The step of obtaining a preset decoding instruction sequence specifically includes: Get the current decoding processing path; The decoding instruction sequence is generated according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template.

4. The channel decoding method according to claim 2, wherein: The step of decoding the soft decision input sequence according to the preset decoding path state and the soft decision metric graph structure template to generate a corresponding soft decision metric graph structure specifically includes: Decoding the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and outputting corresponding soft decision sequence decoding information; Obtaining a data writing location of the soft decision metric input information in the soft decision metric graph structure template; The soft decision metric graph structure template is updated according to the soft decision sequence decoding information and the data writing position to generate the soft decision metric graph structure.

5. The channel decoding method according to claim 1, wherein: Sequentially acquiring each decoding instruction in the decoding instruction sequence, and determining, according to each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction, specifically includes: Obtaining an entry instruction in the decoding instruction sequence as a current decoding instruction; Performing instruction parsing on the current decoding instruction to determine a current data reading position, a current decoding processing instruction position, and a current data writing position; When the current decoded instruction is the termination instruction in the decoded instruction sequence, stopping instruction parsing; When the current decoding instruction is not the termination instruction, the next instruction of the current decoding instruction is obtained as the current decoding instruction, and then the step of performing instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position and the current data writing position is returned.

6. A channel decoding device, characterized in that: The device comprises: The first module is used to obtain log-likelihood ratio information to be decoded; The second module is used to obtain a preset decoding instruction sequence; A third module is configured to decode the log-likelihood ratio information according to the decoding instruction sequence and output decoded bit information; wherein the decoding instruction sequence is configured to decode the log-likelihood ratio information according to the decoding instruction sequence and output decoded bit information, specifically comprising: Generate a hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template; Sequentially acquiring each decoding instruction in the decoding instruction sequence, and determining, based on each decoding instruction, a data reading position, a decoding processing instruction position, and a data writing position corresponding to each decoding instruction; Reading corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and reading the corresponding target decoding processing instruction according to the decoding processing instruction position; Decoding the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction; Determining a first data write location from the soft decision metric graph structure and a second data write location from the hard decision metric graph structure according to the data write location corresponding to each decoding instruction, writing the soft decision bit information to the first data write location and writing the hard decision bit information to the second data write location; The device further comprises: Constructing the soft decision metric graph structure template, wherein the soft decision metric graph structure template includes soft decision metric input information, soft decision metric output information and decoding processing instruction information; According to the soft decision metric graph structure template, the corresponding hard decision metric graph structure template is generated.

7. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the channel decoding method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the channel decoding method according to any one of claims 1 to 5 is implemented.

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