Ultrafast FN tunneling flash memory device based on two-dimensional material and preparation method thereof
The 2D semiconductor-based fast FN tunneling flash memory addresses the speed and retention challenges of traditional flash memory by employing a novel structure and interface engineering, achieving nanosecond-level programming and erasing with long-term non-volatility.
Patent Information
- Application Number
- CN202510281072.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-07-15
AI Technical Summary
Traditional flash memory devices are slow to program, making it difficult to have both fast programming speed and non-volatile features, and cannot meet the needs of high-speed on-chip storage in the integrated memory architecture.
The ultrafast FN tunneling flash memory device structure based on two-dimensional semiconductor materials is adopted. By optimizing the storage stack design and interface engineering, the ultra-thin interface of the two-dimensional material forms an auxiliary barrier to achieve ultrafast charge storage.
It realizes the non-volatile characteristics of nanosecond erase speed and can withstand millions of erase cycles, breaking through the bottleneck of traditional flash memory speed and adapting to the needs of high-performance non-volatile memory technology.
Smart Images
Figure CN120321948A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to a FN tunneling flash memory device and a method for manufacturing the same. Background Art
[0002] With the advent of the era of artificial intelligence and big data, the limitations of traditional charge storage technologies have become increasingly prominent, gradually becoming a bottleneck in the development of information technology. Dynamic random access memory (DRAM) realizes nanosecond-level high-speed reading and writing through the charge storage mechanism of capacitors, but its volatility leads to a sharp increase in refresh power consumption, making it difficult to meet the low-power requirements; while flash memory realizes non-volatile storage by capturing charges, but is limited by the millisecond-level erase / write speed and limited cycle life, making it difficult to meet the requirements of the in-memory computing architecture for high-speed on-chip storage.
[0003] On the other hand, two-dimensional semiconductor materials are layered semiconductor materials composed of a single layer or a few atomic layers (such as transition metal chalcogenides), with high carrier mobility at the atomic layer thickness, and at the same time, the absence of dangling bonds on the surface reduces interface defects. These characteristics give them significant advantages in electronic devices: the ultra-thin structure can break through the size reduction limit of traditional materials, and the high mobility and low-power characteristics can improve the device speed and energy efficiency.
[0004] It is worth noting that two-dimensional materials show unique advantages in the field of non-volatile memories. As a typical non-volatile memory, silicon-based flash memory devices are limited by the efficiency of charge tunneling and cannot have both fast programming speed and non-volatile characteristics at the same time. The perfect lattice interface and natural ultra-thin interface of two-dimensional materials provide a new direction for breaking through the programming speed of semiconductor flash memories. Summary of the Invention
[0005] The purpose of the present invention is to provide an ultra-fast FN tunneling flash memory device based on two-dimensional semiconductor materials and a method for manufacturing the same, aiming at the bottleneck of the slow programming speed of traditional flash memories, and providing a new technical path for high-performance storage.
[0006] The ultra-fast FN tunneling flash memory device based on two-dimensional semiconductor materials provided by the present invention has a structure as Figure 1 shown, including: a substrate 1; a gate 2 located in the middle of the substrate; a blocking layer 3 covering the gate 2 and the substrate 1; a floating gate 4 on the blocking layer 3; a tunneling layer 5 covering the floating gate 4 and the blocking layer 3; a two-dimensional channel 6 on the tunneling layer 5; a source electrode 7 and a drain electrode 8.
[0007] Among them: as Figure 2 shown in the top view structure, the floating gate 4 needs to be completely included in the coverage of the gate 2; the two-dimensional channel 6 needs to be completely included in the coverage of the floating gate 4; the source electrode 7 and the drain electrode 8 need to partially overlap with the two-dimensional channel material 6.
[0008] Optionally, the substrate of the flash memory device can be a rigid substrate such as a silicon wafer, sapphire, mica, etc., or a flexible substrate such as polyimide;
[0009] Optionally, the gate material is selected from metals such as Pt, Au, Cr, Sb, Bi, Ti, Pd, etc.
[0010] Optionally, the materials of the blocking layer and the tunneling layer are selected from dielectric materials such as HfO x , AlO x , ZrO X , hBN, etc. The thickness of the blocking layer is 10 - 50 nm.
[0011] Optionally, the floating gate material is selected from metals such as Pt, Au, etc., or a conductive material such as two-dimensional semiconductor graphene. The thickness of the floating gate is 0.5 - 3 nm.
[0012] Optionally, the two-dimensional channel material is selected from two-dimensional semiconductor materials such as MoS2, WSe2, WS2, BP, InSe, MoTe2, etc.
[0013] Optionally, the source and drain materials are selected from metals such as Pt, Au, Cr, Sb, Bi, Ti, Pd, etc.
[0014] The present invention also provides a method for manufacturing the above-mentioned ultrafast FN tunneling flash memory device based on two-dimensional semiconductor materials, and its flow chart is as Figure 4 shown, and the specific steps are as follows:
[0015] Step 1: Pattern the gate pattern of the flash memory device on the initial substrate, deposit the gate material and perform a lift-off process to obtain a metal gate. The patterning techniques include, but are not limited to, photolithography techniques such as ultraviolet lithography, laser direct writing, electron beam lithography, etc., and the deposition techniques include, but are not limited to, techniques such as electron beam evaporation, thermal evaporation, physical vapor deposition, etc.;
[0016] Step 2: Deposit the blocking layer dielectric material by techniques such as atomic layer deposition;
[0017] Preferably, the thickness of the blocking dielectric is 10 - 50 nm;
[0018] Step 3: If a metal material is selected as the floating gate material, pattern the floating gate on the blocking layer material, deposit the floating gate material and perform a lift-off process to obtain the floating gate. The specific manufacturing process is the same as that of the metal gate manufacturing process. If a two-dimensional conductor material such as graphene is selected, the floating gate is formed by a transfer method;
[0019] Preferably, the thickness of the floating gate is 0.5 - 3 nm;
[0020] Step 4: Deposit the tunneling layer dielectric material by techniques such as atomic layer deposition. If it is a two-dimensional dielectric material, the dielectric layer can be directly transferred to form;
[0021] Preferably, the thickness of the blocking layer medium is 5-20 nm;
[0022] Step 5: Transfer two-dimensional materials as channel materials. The two-dimensional materials used can be obtained by preparation methods such as mechanical exfoliation or chemical vapor deposition, and the two-dimensional materials used can be monolayer or few-layer materials;
[0023] Step 6: Fabricate the source and drain electrodes, and the fabrication process is similar to that of the metal gate fabrication process.
[0024] In the preparation method of the present invention, it further includes:
[0025] (1) Storage stack design:
[0026] For the blocking layer, floating gate and tunneling layer, optimize their thickness ratios and dielectric constants to achieve the best capacitance matching and auxiliary potential barriers, thereby improving the tunneling efficiency. For example, reducing the thickness of the tunneling layer can improve the tunneling efficiency, but will reduce the retention characteristics; the effect of the blocking layer thickness is opposite.
[0027] (2) Ultra-clean interface engineering:
[0028] In Step 5, by means of mixed gas annealing or high-temperature annealing, remove the organic residues introduced during the preparation process.
[0029] In Steps 1 and 3, use oxygen plasma cleaning to clean the surfaces of the gate and floating gate to form a better dielectric interface. Combining atomic-level precision characterization techniques such as atomic force microscopy and scanning electron microscopy, ensure the cleanliness and flatness of the interface.
[0030] (3) Source-drain contact design:
[0031] For the energy band structures of different two-dimensional materials, design flash memory devices with different transport polarities, which can adapt to different application scenarios. Taking WSe2 as an example, its valence band top is about 5.2 eV and its conduction band bottom is about 3.5 eV. Selecting low work function metals such as Bi and Sb stacks can achieve N-type contacts, selecting high work function metals such as Pt and Pd can achieve P-type contacts, and selecting metals with intermediate work functions such as Cr can achieve bipolar contacts.
[0032] The present invention utilizes the auxiliary potential barrier formed by the ultra-thin interface of two-dimensional materials to achieve ultrafast charge storage, Figure 3 showing the energy band and ultrafast mechanism during device programming. Figure 3 In the figure, region 1 represents the drain end, region 2 represents the two-dimensional semiconductor material, region 3 represents the tunneling layer medium, and region 4 represents the floating gate. When a positive programming voltage is applied to the device gate ( Figure 3(a), a double - triangular tunneling barrier will be formed; when a larger programming voltage is continuously applied, the energy - band slope will continue to increase ( Figure 3 (b)). At this time, after the high - energy lucky electrons tunnel through a small triangular barrier, they can be stored in the floating gate without encountering any barrier, so a larger tunneling current can be generated, reducing the programming speed.
[0033] Through the energy - band engineering and interface engineering of two - dimensional materials, the present invention significantly improves the programming efficiency of the memory, realizes non - volatile characteristics for 10 years at the nanosecond - level erase - write speed, and can withstand one million erase - write cycles. The invention effectively breaks through the bottleneck of the traditional flash memory speed and provides an innovative solution for the development of high - performance non - volatile storage technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 It is a side - view structural diagram of an ultrafast FN tunneling flash memory device made of two - dimensional semiconductor materials.
[0035] Figure 2 It is a top - view structural diagram of an ultrafast FN tunneling flash memory device made of two - dimensional semiconductor materials.
[0036] Figure 3 It is an ultrafast mechanism diagram of an ultrafast FN tunneling flash memory device made of two - dimensional semiconductor materials.
[0037] Figure 4 It is a flowchart of the preparation method of an ultrafast FN tunneling flash memory device made of two - dimensional semiconductor materials. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0038] The present invention will be further introduced below through embodiments in combination with the drawings.
[0039] In the following description, the orientation or positional relationship indicated by terms such as "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation.
[0040] In addition, regarding many details, such as the structure, materials, dimensions, processing technology, etc. of the device, so that those of ordinary skill in the art can understand, the present invention can also be implemented without following these specific details. Unless otherwise specified, each part of the device can be composed of materials known to those skilled in the art, or materials with similar functions developed in the future can be used.
[0041] The preparation method of an ultrafast FN tunneling flash memory device made of two - dimensional semiconductor materials, the process is as Figure 4 shown, and the specific steps are as follows:
[0042] (1) On a P-type highly doped silicon substrate with 300 nm of SiO2 grown, the bottom gate electrode was patterned using electron beam lithography, and a positive photoresist pattern was formed by development. Then, a thin Ti / Au metal layer (3 nm / 15 nm) was deposited by electron beam evaporation, and the photoresist was removed in an acetone solution to form the gate electrode;
[0043] (2) After the gate electrode was treated with oxygen plasma (50 W, 20 s), a high-κ dielectric HfO2 thin film was grown at 250 °C by atomic layer deposition, with a deposition thickness of 20 nm, as the blocking layer dielectric;
[0044] (3) The floating gate electrode was defined by electron beam lithography patterning, and a positive photoresist pattern was formed by development. 1 nm of Pt was deposited by electron beam evaporation, and the photoresist was removed in an acetone solution to form the floating gate electrode;
[0045] (4) After the floating gate electrode was treated with oxygen plasma (50 W, 20 s), a high-κ dielectric HfO2 thin film was grown at 250 °C by atomic layer deposition, with a deposition thickness of 8 nm, as the tunneling layer dielectric;
[0046] (5) Monolayer MoS2 was obtained by mechanical exfoliation from bulk materials. The monolayer MoS2 thin film was dry-transferred onto the floating gate using PDMS and annealed in a N2 atmosphere at 200 °C for 2 h. The channel region was defined by electron beam lithography patterning, and a negative photoresist pattern was formed by development. Excess thin film was etched by reactive ion etching (O2, 30 W, 20 s). The photoresist was removed with 1-methyl-2-pyrrolidone to form the two-dimensional material channel;
[0047] (6) Finally, the source and drain were patterned using electron beam lithography, and a positive photoresist pattern was formed by development. Then, a 5 nm / 30 nm Cr / Au stack was deposited by electron beam evaporation, and the photoresist was removed in an acetone solution to form the source and drain electrodes.
[0048] The specific programming and erasing operation methods of the ultrafast FN tunneling flash memory device prepared in the above embodiments are as follows:
[0049] For the programming operation, the source and drain are grounded, and a nanosecond-level positive pulse is applied through the gate. Electrons in the channel are injected into the floating gate through the tunneling layer. The electrons in the floating gate cause the threshold of the device to shift to the right, thus achieving nanosecond-level programming; for the erasing operation, the source and drain are grounded, and a nanosecond-level negative pulse is applied through the gate. The electrons in the floating gate return to the channel through the tunneling layer. The loss of electrons in the floating gate causes the threshold of the device to shift to the left, thus achieving nanosecond-level erasing. After testing, the device can maintain non-volatile characteristics for 10 years at a nanosecond-level erase / write speed and can withstand one million erase / write cycles.
Claims
1. An ultrafast FN tunneling flash memory device based on two-dimensional materials, characterized in that, Comprising: A substrate; A gate located at the middle part of the substrate; A blocking layer covering the gate and the substrate; A floating gate on the blocking layer; A tunneling layer covering the floating gate and the blocking layer; A two-dimensional channel on the tunneling layer; A source and a drain; wherein, the floating gate is completely included in the coverage of the gate; the two-dimensional channel is completely included in the coverage of the floating gate; the source and the drain partially overlap with the two-dimensional channel material.
2. The ultrafast FN tunneling flash memory device according to claim 1, characterized in that, The substrate material is a rigid silicon wafer, sapphire or mica, or a flexible polyimide.
3. The ultrafast FN tunneling flash memory device according to claim 1, wherein The gate material is selected from Pt, Au, Cr, Sb, Bi, Ti, Pd.
4. The ultrafast FN tunneling flash memory device according to claim 1, characterized in that The barrier layer and the tunneling layer materials are selected from HfO x , AlO x , ZrO X , hBN; the thickness of the barrier layer is 10 - 50 nm.
5. The ultrafast FN tunneling flash memory device according to claim 1, characterized in that The floating gate material is selected from the metal Pt, Au, or the two-dimensional conductor material graphene; the thickness of the floating gate is 0.5 - 3 nm.
6. The ultrafast FN tunneling flash memory device according to claim 1, wherein The two-dimensional channel material is selected from MoS2, WSe2, WS2, BP, InSe, MoTe2.
7. The ultrafast FN tunneling flash memory device according to claim 1, characterized in that, The source and drain materials are selected from Pt, Au, Cr, Sb, Bi, Ti, Pd.
8. The preparation method of the ultra-fast FN tunneling flash memory device according to any one of claims 1-7, characterized in that, The specific steps are as follows: Step 1: Pattern the gate pattern of the flash memory device on the substrate, deposit the gate material and perform a lift-off process to obtain a metal gate; Step 2: Deposit a blocking layer dielectric material by atomic layer deposition technology; Step 3: If a metal material is selected as the floating gate material, pattern the floating gate on the blocking layer material, deposit the floating gate material and perform a lift-off process to obtain the floating gate, and the specific preparation process is the same as the metal gate preparation process; if a two-dimensional conductor material is selected as the floating gate material, the floating gate is formed by a transfer method; Step 4: Deposit a tunneling layer dielectric material by atomic layer deposition technology; if it is a two-dimensional dielectric material, directly transfer to form a dielectric layer; Step 5: Transfer a two-dimensional material as the channel material, and the two-dimensional material used is prepared by mechanical exfoliation or chemical vapor deposition, and the two-dimensional material used can be a single layer or several layers of materials; Step 6: Prepare the source and the drain.
9. The method for preparing the ultrafast FN tunneling flash memory device according to claim 8, wherein, Also including: Memory stack design: For the said blocking layer, floating gate and tunneling layer, optimize their thickness ratio and dielectric constant to achieve the best capacitance matching and auxiliary potential barrier, so as to improve the tunneling efficiency; Ultra-clean interface engineering: In Step 5, eliminate the organic residues introduced during the preparation process by annealing with a mixed gas or high-temperature annealing; In Step 1 and Step 3, use oxygen plasma cleaning to clean the surfaces of the gate and the floating gate to form a more excellent dielectric interface; combined with atomic-level precision characterization techniques, including atomic force microscopy and scanning electron microscopy, ensure the cleanliness and flatness of the interface; Source-drain contact design: For the energy band structures of different two-dimensional materials, design flash memory devices with different transport polarities to adapt to different application scenarios; including: for WSe2, its valence band top is about 5.2 eV and its conduction band bottom is about 3.5 eV. Selecting a metal Bi or Sb stack with a low work function can achieve an N-type contact, selecting metals Pt, Pd with a high work function can achieve a P-type contact, and selecting Cr with a work function in the middle can achieve a bipolar contact.