Display panel and manufacturing method thereof

Abstract

The invention relates to a display panel and a manufacturing method thereof. The display panel of the present invention may include: a base layer; a pixel definition film disposed on the base layer and having a light emitting opening portion; a partition wall disposed on the pixel defining film and having a partition wall opening portion overlapping the light emitting opening portion; and a light-emitting element including an anode, a light-emitting pattern, and a cathode in contact with the partition wall, the light-emitting element being disposed within the light-emitting opening and the partition wall opening. The partition wall may include: a first partition wall layer disposed on the pixel definition film; and a second partition wall layer disposed on the first partition wall layer and having an inverted cone shape.

Description

Technical Field

[0001] The present invention relates to a display panel and a method of manufacturing the display panel, and more particularly, to a display panel with improved display quality. Background Art

[0002] Display devices such as televisions, monitors, smart phones, and tablet computers that provide images to users include a display panel for displaying images. As display panels, various display panels are being developed, such as a liquid crystal display panel, an organic light emitting display panel, an electro wetting display panel, and an electrophoretic display panel.

[0003] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated for each light emitting region, and the cathode may supply a common voltage to each light emitting region. Summary of the Invention

[0004] An object of the present invention is to provide a display panel and a method of manufacturing the same, in which display quality is improved in a display panel in which a light emitting element is formed without using a metal mask.

[0005] A display panel according to an embodiment of the present invention may include: a base layer; a pixel defining film disposed on the base layer and having a light emitting opening; a partition disposed on the pixel defining film and having a partition opening overlapping the light emitting opening; and a light emitting element including an anode, a light emitting pattern, and a cathode in contact with the partition, and disposed in the light emitting opening and the partition opening. The partition may include: a first partition layer disposed on the pixel defining film; and a second partition layer disposed on the first partition layer and having an inverted cone shape.

[0006] The second partition layer may include a tip portion protruding inward compared to the first partition layer.

[0007] The second partition layer may include: a lower surface protruding inward compared to a first inner surface of the first partition layer; a second inner surface extending in a direction away from the base layer from the lower surface; and an upper surface extending in a direction parallel to the lower surface from the second inner surface, wherein an angle formed by the lower surface and the second inner surface may be an obtuse angle.

[0008] The region of the anode exposed through the light-emitting opening can be defined as a light-emitting region, and the second inner surface can be closer to the center of the light-emitting region than the first inner surface.

[0009] The length of the upper surface of the second partition layer in one direction can be greater than the length of the lower surface in the one direction, and the one direction can be perpendicular to the thickness direction of the base layer.

[0010] The display panel may further include: a lower encapsulation inorganic pattern covering the light-emitting element, wherein the lower encapsulation inorganic pattern can be in overall contact with the second inner surface of the second partition layer.

[0011] The display panel may further include: an encapsulation organic film covering the lower encapsulation inorganic pattern.

[0012] The second partition layer may include a plurality of sub-layers.

[0013] The etching rate of the sub-layer close to the first partition layer can be greater than the etching rate of the sub-layer close to the encapsulation organic film.

[0014] The length of the sub-layer close to the first partition layer in one direction can be less than the length of the sub-layer close to the encapsulation organic film in the one direction, and the one direction can be perpendicular to the thickness direction of the base layer.

[0015] The second partition layer may include an inorganic substance.

[0016] The density of the second partition layer can decrease as it approaches the first partition layer from the encapsulation organic film.

[0017] A method of manufacturing a display panel according to an embodiment of the present invention may include the following steps: providing a preliminary display panel including a base layer and a pixel definition film disposed on the base layer; forming a first preliminary partition layer on the preliminary display panel; forming a second preliminary partition layer on the first preliminary partition layer; forming a partition having a partition opening and a part having an inverted cone shape by etching the first preliminary partition layer and the second preliminary partition layer; forming a light-emitting opening overlapping the partition opening by etching the pixel definition film; and forming a light-emitting element in the light-emitting opening and the partition opening.

[0018] The step of forming the partition wall having the partition wall opening and a part of which has an inverted cone shape by etching the first preliminary partition wall layer and the second preliminary partition wall layer may include the step of forming a first partition wall layer and a second partition wall layer, wherein the length of the upper surface of the second partition wall layer in one direction may be greater than the length of the lower surface of the second partition wall layer in the one direction, and the one direction may be perpendicular to the thickness direction of the base layer.

[0019] The step of forming the second preliminary partition wall layer on the first preliminary partition wall layer may include the following steps: depositing a first sub-layer on the first preliminary partition wall layer; depositing a second sub-layer on the first sub-layer; and depositing a third sub-layer on the second sub-layer, wherein the etching rate of the first sub-layer may be greater than the etching rate of the second sub-layer, and the etching rate of the second sub-layer may be greater than the etching rate of the third sub-layer.

[0020] The step of forming the partition wall having the partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer may include the following steps: forming a preliminary partition wall opening by dry-etching the first preliminary partition wall layer and the second preliminary partition wall layer; and forming a first partition wall layer and a second partition wall layer having an inverted cone shape by wet-etching the first preliminary partition wall layer and the second preliminary partition wall layer.

[0021] The step of forming the second preliminary partition wall layer on the first preliminary partition wall layer may include the following steps: depositing an inorganic substance at a first speed; and depositing an inorganic substance at a second speed, wherein the first speed may be greater than the second speed.

[0022] The density of the second preliminary partition wall layer may increase as it is farther away from the first preliminary partition wall layer.

[0023] The step of forming the partition wall having the partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer may include the following steps: forming a second partition wall layer having an inverted cone shape by dry-etching the first preliminary partition wall layer and the second preliminary partition wall layer; and forming a first partition wall layer by wet-etching the first preliminary partition wall layer.

[0024] The partition wall opening may include: a first region defined by a first inner surface of the first partition wall layer; and a second region defined by a second inner surface of the second partition wall layer, wherein the length of the first region in a direction perpendicular to the base layer may be greater than the length of the second region in a direction perpendicular to the base layer.

[0025] As described above, as the second partition layer has an inverted cone shape, the foreign matter input path flowing between the lower encapsulation inorganic pattern and the partition can become longer, and the contact area between the lower encapsulation inorganic pattern and the partition can increase. Accordingly, the phenomenon of moisture inflow through the foreign matter between the lower encapsulation inorganic pattern and the partition can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel caused by foreign matter can be reduced or eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a is a perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0028] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0029] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0030] Figure 4 is a plan view magnifying a part of a display area of a display panel according to an embodiment of the present invention.

[0031] Figure 5 is along Figure 3 a cross-sectional view taken along the I-I' cutting line of

[0032] Figure 6a is a magnified view of a region corresponding to the AA' region of Figure 5

[0033] Figure 6b is a magnified view of a region corresponding to the AA' region of Figure 5

[0034] Figures 7a to 7j is a cross-sectional view showing some steps in a method of manufacturing a display panel according to an embodiment of the present invention.

[0035] Figures 8a to 8c is a cross-sectional view showing some steps in a method of manufacturing a display panel according to an embodiment of the present invention.

[0036] Figures 9a to 9c is a cross-sectional view showing some steps in a method of manufacturing a display panel according to an embodiment of the present invention.

[0037] DESCRIPTION OF REFERENCE NUMERALS DETAILED DESCRIPTION​​

[0038] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is "above" another component, "connected" to another component, or "combined" with another component, it means that it can be directly arranged above the other component or directly connected / combined with the other component, or a third component can also be arranged between them.

[0039] The same reference numerals refer to the same components. Also, in the drawings, for effective illustration of the technical content, the thickness, ratio, and size of the components are exaggerated. "And / or" includes all combinations of more than one of the related components that can be defined.

[0040] Terms such as "first", "second", etc. can be used to describe various components, but the components should not be limited by these terms. These terms are only for the purpose of distinguishing one component from another. For example, without departing from the scope of the claims of the present invention, the first component can be named the second component, and similarly, the second component can also be named the first component. Singular expressions include plural expressions as long as they do not clearly indicate different meanings in the context.

[0041] Also, terms such as "below", "lower side", "above", "upper side", etc. are used to describe the relative relationship of the components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0042] Terms such as "comprising" or "having" should be understood as specifying the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, rather than precluding the presence or additional possibility of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

[0043] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. Also, terms that are the same as those defined in a commonly used dictionary should be understood as having a meaning consistent with the meaning in the context of the related art. Here, unless explicitly defined, they should not be interpreted as overly ideal or overly formal meanings.

[0044] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0045] Figure 1a is a perspective view of a display device DD according to an embodiment of the present invention, Figure 1bExploded perspective view of a display device DD according to an embodiment of the present invention.

[0046] In one embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an outdoor advertising board. Also, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, and a camera. However, this is exemplary, and as long as it does not deviate from the concept of the present invention, it may also be used as other display devices. In Figure 1a and Figure 1b exemplarily shows a case where the display device DD is a smart phone.

[0047] Referring to Figure 1a and Figure 1b , the display device DD may display an image IM on a display surface FS parallel to each of a first direction DR1 and a second direction DR2 facing a third direction DR3. The image IM may include a moving image or a still image. In Figure 1a as an example of the image IM, a clock window and icons are shown. The display surface FS for displaying the image IM may correspond to the front surface of the display device DD.

[0048] In the present embodiment, based on the direction of the displayed image IM, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined. The front surface and the rear surface may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. Additionally, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be converted to another direction. In this specification, "on a plane" may mean a situation when observed in the third direction DR3.

[0049] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form the appearance of the display device DD.

[0050] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define the display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a border area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or more.

[0051] The border area BZA is an area with a relatively lower light transmittance than the transmissive area TA. The border area BZA can define the shape of the transmissive area TA. The border area BZA can be adjacent to the transmissive area TA and can surround the transmissive area TA. However, this is shown by way of example, and the border area BZA of the window WP can be omitted. The window WP can include at least one functional layer such as an anti-fingerprint layer, a hard coat, and an anti-reflection layer, but is not limited to a specific embodiment.

[0052] The display module DM can be disposed below the window WP. The display module DM can be configured to substantially generate an image IM. The image IM generated by the display module DM can be displayed on the display surface IS of the display module DM and can be visible to the user from the outside through the transmissive area TA.

[0053] The display module DM can include a display area DA and a non-display area NDA. The display area DA can be an area activated according to an electrical signal. The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an area covered by the border area BZA and can be invisible from the outside.

[0054] The housing HAU can be coupled to the window WP. The housing HAU can be coupled to the window WP to provide a predetermined internal space. The display module DM can be housed in the internal space.

[0055] The housing HAU can include a material with relatively high rigidity. For example, the housing HAU can include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing HAU can stably protect the components of the display device DD housed in the internal space from the impact of the outside.

[0056] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0057] Refer to Figure 2 and the display module DM can include a display panel DP and an input sensor INS. Although not shown separately, a display device DD according to an embodiment of the present invention (refer to Figure 1a ) can also include a protection component disposed on the lower surface of the display panel DP or an anti-reflection component and / or a window component disposed on the upper surface of the input sensor INS.

[0058] The display panel DP can be a light-emitting display panel. However, this is exemplary and not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel can include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0059] The display panel DP can include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS can be directly disposed on the thin film encapsulation layer TFE. In this specification, "A is directly disposed on B" means that no adhesive layer is disposed between the A structure and the B structure.

[0060] The base layer BL can include at least one plastic film. The base layer BL, as a flexible substrate, can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc. The display area DA and the non-display area NDA described in Figure 1b can be similarly defined on the base layer BL.

[0061] The circuit element layer DP-CL can include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, driving circuits of pixels, etc.

[0062] The display element layer DP-OLED can include partition walls and light-emitting elements. The light-emitting elements can include anodes, intermediate layers, and cathodes.

[0063] The thin film encapsulation layer TFE can include multiple thin films. Some of the thin films can be disposed to improve optical efficiency, and some of the thin films can be disposed to protect the organic light-emitting diodes.

[0064] The input sensor INS obtains coordinate information of an external input. The input sensor INS can have a multi-layer structure. The input sensor INS can include a single-layer or multi-layer conductive layer. And, the input sensor INS can include a single-layer or multi-layer insulating layer. The input sensor INS can sense an external input in a capacitive manner. However, this is exemplary and not particularly limited thereto. For example, in one embodiment, the input sensor INS can also sense an external input in an electromagnetic induction manner or a pressure sensing manner. Additionally, in another embodiment of the present invention, the input sensor INS can be omitted.

[0065] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0066] Referring toFigure 3 In a display panel DP, a display area DA and a non-display area NDA around the display area DA can be defined. The display panel DP can include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP can include a driving circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA can be distinguished according to the presence or absence of the arrangement of the pixels PX. Pixels PX can be arranged in the display area DA. The driving circuit GDC and the pad portion PLD can be arranged in the non-display area NDA.

[0067] The pixels PX can be arranged in a first direction DR1 and a second direction DR2. The pixels PX can include a plurality of pixel rows extending along the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending along the second direction DR2 and arranged in the first direction DR1.

[0068] The signal lines SGL can include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL can be connected to a corresponding pixel in the pixels PX, and each of the data lines DL can be connected to a corresponding pixel in the pixels PX. The power line PL can be electrically connected to the pixels PX. The control signal line CSL can be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0069] The driving circuit GDC can include a gate driving circuit. The gate driving circuit can generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit can also output other control signals to the pixel driving circuit.

[0070] The pad portion PLD can be a portion to which a flexible circuit board is connected. The pad portion PLD can include pixel pads D-PD, and the pixel pads D-PD can be pads for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD can be connected to a corresponding signal line in the signal lines SGL. The pixel pads D-PD can be connected to corresponding pixels PX through the signal lines SGL. And, one of the pixel pads D-PD can be connected to the driving circuit GDC.

[0071] And, the pad portion PLD can further include input pads. The input pads can be pads for connecting the flexible circuit board to an input sensor INS (refer to Figure 2 ). However, it is not limited thereto, and the input pads can be arranged on the input sensor INS (refer to Figure 2 ), so that they can be connected to a circuit board separately separated from the pixel pads D-PD. Or, the input sensor INS (refer to Figure 2 ) can be omitted, and the input pads can also be not included.

[0072] Figure 4 is a plan view magnifying a part of a display area DA of a display panel DP according to an embodiment of the present invention (refer to Figure 2 ). Figure 4 shows a plane of a display module DM (refer to Figure 1b ) observed from a display surface IS (refer to Figure 1b ) of the display module DM, and shows an arrangement of light-emitting regions PXA-R, PXA-G, and PXA-B.

[0073] Refer to Figure 4 , the display area DA may include a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and a peripheral region NPXA surrounding the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively correspond to regions that emit light provided from light-emitting elements. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be distinguished according to colors of light emitted to the outside of the display module DM (refer to Figure 2 ).

[0074] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively provide light of a first color, light of a second color, and light of a third color having different colors from each other. For example, the light of the first color may be red light, the light of the second color may be green light, and the light of the third color may be blue light. However, examples of the light of the first color, the light of the second color, and the light of the third color are not necessarily limited to the above examples.

[0075] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be defined as a region where an upper surface of an anode is exposed by a light-emitting opening portion described later. The peripheral region NPXA may set boundaries of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, and may prevent color mixing between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0076] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be provided in plural, and may have a predetermined arrangement pattern within the display area DA and be repeatedly arranged. For example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plural, and a plurality of "first groups" and a plurality of "second groups" may be alternately arranged with each other along the second direction DR2.

[0077] One second light-emitting region PXA-G may be arranged to be separated from one first light-emitting region PXA-R or one third light-emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as the direction between the first direction DR1 and the second direction DR2.

[0078] In addition, Figure 4 is a diagram exemplarily showing the arrangement pattern of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, but is not limited thereto, and may be arranged in various patterns. In one embodiment, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a Figure 4 pentile arrangement pattern as shown. Or, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may also have a stripe arrangement pattern or a diamond pixel ® arrangement pattern. ®

[0079] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have various shapes on a plane. For example, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have shapes such as a polygon, a circle, or an ellipse. Figure 4 Exemplarily shown are the first light-emitting region PXA-R and the third light-emitting region PXA-B having a quadrilateral shape (or, a diamond shape) on a plane, and the second light-emitting region PXA-G having an octagonal shape.

[0080] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have the same shape as each other on a plane, or may have at least partially different shapes from each other. Figure 4Exemplarily, a first light-emitting region PXA-R and a third light-emitting region PXA-B having the same shape as each other on a plane and a second light-emitting region PXA-G having a shape different from that of the first light-emitting region PXA-R and the third light-emitting region PXA-B are shown.

[0081] At least a part of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have different areas from each other on a plane. In one embodiment, the area of the first light-emitting region PXA-R that emits red light may be larger than the area of the second light-emitting region PXA-G that emits green light and smaller than the area of the third light-emitting region PXA-B that emits blue light. However, the size relationship of the areas among the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B according to the emission color is not limited to this, and the size relationship of the areas among the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may vary according to the design of the display module DM (refer to Figure 2 ). And, not limited thereto, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may also have the same area as each other on a plane.

[0082] In addition, the shapes, areas, arrangements, etc. of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B of the display module DM (refer to Figure 2 ) of the present invention may be variously designed according to the color of the emitted light or the size and composition of the display module DM (refer to Figure 2 ), and are not limited to Figure 4 the illustrated embodiments.

[0083] Figure 5 is a cross-sectional view taken along the I-I' cutting line of Figure 3 . When explaining Figure 5 , the description with reference to Figure 2 and the description of the same reference numerals are omitted. Figure 5 An enlarged view shows a light-emitting region PXA within the display area DA (refer to Figure 4 ), and the light-emitting region PXA of Figure 5 may correspond to one of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0084] Referring to Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0085] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by means such as coating and deposition. Then, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed.

[0086] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0087] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the adhesion between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0088] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Only a part of the semiconductor pattern is exemplarily shown herein, and the semiconductor pattern may also be disposed in a plurality of light-emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 5 ). The semiconductor pattern may be arranged in a specific rule throughout the plurality of light-emitting regions PXA-R, PXA-G, PXA-B. The semiconductor pattern has different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant. Figure 4 The conductivity of the first region is greater than that of the second region, and the first region substantially functions as an electrode or a signal line. The second region may substantially correspond to the active region (or, channel region) of the transistor. In other words, a part of the semiconductor pattern may be the active region of the transistor, another part may be the source region or the drain region of the transistor, and yet another part may be the conductive region.

[0089] The source region S, the active region A, and the drain region D of the transistor TR1 may be formed by the semiconductor pattern.

[0090] Figure 5 Figure 5Part of a signal transmission region SCL formed of a semiconductor pattern is shown. Although not shown separately, the signal transmission region SCL may be connected to the drain region D of the transistor TR1 in a plane.

[0091] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be disposed on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be inorganic layers or organic layers.

[0092] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source region S, the active region A, the drain region D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate region G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate region G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0093] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a first contact hole CNT-1 penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0094] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0095] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light-emitting element ED, a sacrificial pattern SP, a pixel definition film PDL, and a partition wall PW.

[0096] The light-emitting element ED may include an anode AE (or a first electrode), a light-emitting pattern EP, and a cathode CE (or a second electrode). The light-emitting element ED may be disposed in a light-emitting opening OP-E and a partition wall opening OP-P described later.

[0097] The anode AE can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined by penetrating the fifth insulating layer 50. Therefore, the anode AE can be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus can be electrically connected to the corresponding circuit element. The anode AE can include a single-layer or multi-layer structure. The anode AE can include multiple layers containing ITO and Ag. For example, the anode AE can include a layer containing ITO (hereinafter referred to as the lower ITO layer), a layer containing Ag disposed on the lower ITO layer (hereinafter referred to as the Ag layer), and a layer containing ITO disposed on the Ag layer (hereinafter referred to as the upper ITO layer).

[0098] The sacrificial pattern SP can be disposed between the anode AE and the pixel definition film PDL. The sacrificial pattern SP can be defined with (or have) a sacrificial opening OP-S that exposes a part of the upper surface of the anode AE. The sacrificial opening OP-S can overlap with a light-emitting opening OP-E described later.

[0099] The pixel definition film PDL can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light-emitting opening OP-E can be defined in the pixel definition film PDL. The light-emitting opening OP-E can correspond to the anode AE, and the pixel definition film PDL can expose at least a part of the anode AE through the light-emitting opening OP-E.

[0100] Moreover, the light-emitting opening OP-E can correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE can be separated from the pixel definition film PDL with the sacrificial pattern SP in the cross section, whereby damage to the anode AE can be protected during the formation process of the light-emitting opening OP-E.

[0101] In the plane, the area of the light-emitting opening OP-E can be smaller than the area of the sacrificial opening OP-S. That is, the inner surface of the pixel definition film PDL defining the light-emitting opening OP-E can be closer to the center of the anode AE than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, it is not limited thereto, and the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S can also be substantially aligned with the inner surface of the pixel definition film PDL defining the light-emitting opening OP-E. At this time, the light-emitting region PXA can also be regarded as the region of the anode AE exposed in the corresponding sacrificial opening OP-S.

[0102] The pixel definition film PDL can include an inorganic insulating substance. For example, it can include silicon nitride (SiN x, or silicon nitride). The pixel definition layer PDL can be disposed between the anode AE and the partition wall PW, thereby blocking the electrical connection between the anode AE and the partition wall PW from each other.

[0103] The light-emitting pattern EP can be disposed on the anode AE. The light-emitting pattern EP can include a light-emitting layer containing a light-emitting substance. The light-emitting pattern EP can also include a hole injection layer (HIL: Hole Injection Layer) and a hole transport layer (HTL: Hole Transport Layer) disposed between the anode AE and the light-emitting layer, and can also include an electron transport layer (ETL: Electron Transport Layer) and an electron injection layer (EIL: Electron Injection Layer) disposed on the light-emitting layer. The light-emitting pattern EP can be referred to as an "organic layer" or an "intermediate layer".

[0104] The light-emitting pattern EP can be patterned by the tip portion defined in the partition wall PW. The detailed content will be described later in the description of the manufacturing method of the display panel. The light-emitting pattern EP can be disposed inside the sacrificial opening OP-S and the light-emitting opening OP-E. However, this is shown exemplarily, and the light-emitting pattern EP can be disposed inside at least one of the sacrificial opening OP-S, the light-emitting opening OP-E, and the partition wall opening OP-P. The light-emitting area PXA can be defined as the area where the upper surface of the anode AE is exposed by the light-emitting opening OP-E.

[0105] The cathode CE can be disposed on the light-emitting pattern EP. The cathode CE can be patterned by the tip portion defined in the partition wall PW. At least a part of the cathode CE can be disposed in the partition wall opening OP-P. In Figure 5 the case where the cathode CE is disposed in the light-emitting opening OP-E and the partition wall opening OP-P is shown exemplarily, but it is not limited thereto. For example, the cathode CE can be disposed only in the partition wall opening OP-P.

[0106] The cathode CE can be in contact with the partition wall PW. For example, the cathode CE can extend along the first inner surface S-L1 of the first partition wall layer L1, and the end of the cathode CE can be in contact with the first partition wall layer L1. In Figure 5 the case where the cathode CE is in contact with the first inner surface S-L1 of the first partition wall layer L1 and the inner surface of the pixel definition layer PDL is shown exemplarily, but it is not limited thereto. For example, the cathode CE can be formed to be in contact with only the first inner surface S-L1 of the first partition wall layer L1.

[0107] The cathode CE can have electrical conductivity. As long as it has electrical conductivity, the cathode CE can be formed using a variety of materials such as metals, transparent conductive oxides (TCO: Transparent Conductive Oxide), or conductive polymer materials. For example, the cathode CE can include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or their compounds.

[0108] The partition wall PW can be disposed on the pixel defining film PDL. A partition wall opening OP-P can be defined in the partition wall PW. The partition wall opening OP-P can overlap with the light emitting opening OP-E and can expose at least a part of the anode AE.

[0109] The partition wall PW can include a plurality of layers stacked in sequence. For example, the partition wall PW can include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 can be disposed on the pixel defining film PDL, and the second partition wall layer L2 can be disposed on the first partition wall layer L1. As Figure 5 shown, the thickness of the first partition wall layer L1 can be greater than the thickness of the second partition wall layer L2, but it is not limited thereto.

[0110] Each of the first partition wall layer L1 and the second partition wall layer L2 can include a conductive material. For example, the conductive material can include metals, transparent conductive oxides (TCO: Transparent Conductive Oxide), or a combination thereof. For example, the metals can include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or alloys. The transparent conductive oxides can include indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO: Indium Gallium Zinc Oxide), or aluminum zinc oxide.

[0111] The partition PW may have an undercut shape in cross-section. At least one of the multiple layers of the partition PW may be recessed compared to the other layers, whereby the partition PW may include a pointed end portion. For example, the first partition layer L1 may have an undercut shape with respect to the second partition layer L2. Based on the light-emitting region PXA, the first partition layer L1 may be recessed outward with respect to the second partition layer L2. The second partition layer L2 may include a pointed end portion that protrudes toward the light-emitting region PXA compared to the first partition layer L1. That is, the second inner surface S-L2 of the second partition layer L2 may be closer to the center of the light-emitting region PXA than the first inner surface S-L1 of the first partition layer L1.

[0112] The second partition layer L2 may include a lower surface B-L2, a second inner surface S-L2, and an upper surface U-L2. The lower surface B-L2 of the second partition layer L2 may protrude more inward compared to the first inner surface S-L1 of the first partition layer L1. The second inner surface S-L2 may extend in a direction away from the base layer BL from the lower surface B-L2. The upper surface U-L2 may extend in a direction parallel to the lower surface B-L2 from the second inner surface S-L2. The second partition layer L2 may have an inverted cone shape. The angle formed by the lower surface B-L2 and the second inner surface S-L2 of the second partition layer L2 may be an obtuse angle. The length of the upper surface U-L2 of the second partition layer L2 in one direction may be greater than the length of the lower surface B-L2 in one direction. At this time, one direction may be perpendicular to the thickness direction of the base layer BL. For example, one direction may correspond to the first direction DR1 or the second direction DR2.

[0113] The partition PW may receive a driving voltage. Accordingly, the cathode CE may be electrically connected to the partition PW to receive the driving voltage.

[0114] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0115] The lower encapsulation inorganic pattern LIL may correspond to (or overlap with) the light-emitting opening OP-E. The lower encapsulation inorganic pattern LIL may be disposed on the light-emitting element ED to cover the light-emitting element ED. A part of the lower encapsulation inorganic pattern LIL may be formed within the partition opening OP-P, and another part of the lower encapsulation inorganic pattern LIL may be formed on the partition PW. The lower encapsulation inorganic pattern LIL may be in overall contact with the second inner surface S-L2 of the second partition layer L2.

[0116] The encapsulation organic film OL can be disposed on the lower encapsulation inorganic pattern LIL to cover the lower encapsulation inorganic pattern LIL. The encapsulation organic film OL can provide a flat upper surface. The upper encapsulation inorganic film UIL can be disposed on the encapsulation organic film OL. The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL can protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL can protect the display element layer DP-OLED from foreign substances such as dust.

[0117] According to the present invention, a plurality of light-emitting patterns EP can be patterned and deposited in pixel units by defining the tip portions of the partition walls PW. That is, the light-emitting patterns EP can be formed together using an aperture mask, but can be easily divided in pixel units by the partition walls PW.

[0118] On the contrary, in the case of patterning the light-emitting pattern EP using a fine metal mask (FMM: Fine Metal Mask), in order to support the fine metal mask, it is necessary to provide a support partition protruding from the conductive partition wall. And, since the fine metal mask is separated from the base surface for patterning by the height of the partition wall and the partition, there may be limitations in achieving high resolution. And, since the fine metal mask contacts the partition, after the patterning process of the light-emitting pattern EP, foreign substances may remain on the partition, or the partition may be damaged by the pressing of the fine metal mask. Accordingly, a defective display panel may be formed.

[0119] According to the present embodiment, by including the partition walls PW, physical separation between the light-emitting elements ED can be easily achieved. Accordingly, current leakage or driving errors, etc. between adjacent light-emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 4 ) can be prevented, and each light-emitting element ED can achieve independent driving.

[0120] In particular, by patterning the light-emitting pattern EP without a mask in contact with the internal structure within the display area DA (refer to Figure 1b ), a display panel DP with a reduced defect rate and improved process reliability can be provided. Since patterning can be achieved even without providing a separate support partition protruding from the partition wall PW, the areas of the light-emitting regions PXA-R, PXA-G, PXA-B can be miniaturized, and thus a display panel DP that can easily achieve high resolution can be provided.

[0121] And, in the case of manufacturing a large-area display panel DP, since the manufacturing of a large-area mask is omitted, the process cost can be reduced, and since it is not affected by defects that may occur in the large-area mask, a display panel DP with improved process reliability can be provided.

[0122] Figure 6a is the enlarged view of the region corresponding to the AA' region of Figure 5 .

[0123] Referring to Figure 5 and Figure 6a , the partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. In an embodiment of the present invention, the second partition wall layer L2 may include a plurality of sub-layers L21, L22, L23. For example, the second partition wall layer L2 may include a first sub-layer L21, a second sub-layer L22, and a third sub-layer L23. Three sub-layers L21, L22, L23 are exemplarily shown in Figure 6a , but the number of sub-layers is not limited thereto.

[0124] The etching rate of the sub-layer close to the first partition wall layer L1 may be greater than that of the sub-layer close to the encapsulation organic film OL. That is, the etching rate of the first sub-layer L21 may be greater than that of the second sub-layer L22, and the etching rate of the second sub-layer L22 may be greater than that of the third sub-layer L23. For example, the first sub-layer L21 may include tantalum (Ta), the second sub-layer L22 may include niobium (Nb), and the third sub-layer L23 may include titanium (Ti).

[0125] In the process of forming the partition wall PW, the sub-layer with a higher etching rate close to the first partition wall layer L1 may be etched more than the sub-layer with a lower etching rate close to the encapsulation organic film OL. As a result, the length of the sub-layer close to the first partition wall layer L1 in one direction may be smaller than that of the sub-layer close to the encapsulation organic film OL in one direction. At this time, one direction may be perpendicular to the thickness direction of the base layer BL. For example, one direction may correspond to the first direction DR1 or the second direction DR2. That is, the second partition wall layer L2 may have an inverted cone shape.

[0126] Figure 6b is the enlarged view of the region corresponding to the AA' region of Figure 5 .

[0127] Referring to Figure 5 and Figure 6b , the partition wall PWa may include a first partition wall layer L1 and a second partition wall layer L2a. In an embodiment of the present invention, the second partition wall layer L2a may include an inorganic substance. For example, the second partition wall layer L2a may include silicon nitride (SiN x, or silicon nitride). The density of the second partition layer L2a can decrease as it approaches the first partition layer L1 from the encapsulation organic film OL. In the process of forming the partition PWa, a part of the second partition layer L2a with a smaller density near the first partition layer L1 can be etched more than another part of the second partition layer L2a with a larger density near the encapsulation organic film OL. As a result, the length of a part of the second partition layer L2a near the first partition layer L1 in one direction can be smaller than the length of another part of the second partition layer L2a near the encapsulation organic film OL in the same direction. At this time, the one direction can be perpendicular to the thickness direction of the base layer BL. For example, the one direction can correspond to the first direction DR1 or the second direction DR2. That is, the second partition layer L2a can have an inverted cone shape.

[0128] Refer to Figures 5 to 6b , since the second partition layer L2a has an inverted cone shape, the foreign object input path flowing into the space between the lower encapsulation inorganic pattern LIL and the partition PWa can become longer, and the contact area between the lower encapsulation inorganic pattern LIL and the partition PWa can increase. Therefore, the phenomenon of moisture flowing in through the foreign object between the lower encapsulation inorganic pattern LIL and the partition PWa can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel DP caused by foreign objects can be reduced or eliminated.

[0129] Figures 7a to 7j is a cross-sectional view showing some steps in the manufacturing method of a display panel according to an embodiment of the present invention. When explaining Figures 7a to 7j , the same / similar reference numerals are used to describe the same / similar components as those described with reference to Figures 1a to 6b , and repeated descriptions are omitted.

[0130] The manufacturing method of a display panel according to an embodiment of the present invention may include the following steps: providing a preliminary display panel including a base layer and a pixel defining film disposed on the base layer; forming a first preliminary partition layer on the preliminary display panel; forming a second preliminary partition layer on the first preliminary partition layer; forming a partition having a partition opening and a part having an inverted cone shape by etching the first preliminary partition layer and the second preliminary partition layer; forming a light emitting opening overlapping the partition opening by etching the pixel defining film; and forming a light emitting element in the light emitting opening and the partition opening.

[0131] Hereinafter, through Figures 7a to 7j , a method of forming one light emitting element ED and the lower encapsulation inorganic pattern LIL, the encapsulation organic film OL, and the upper encapsulation inorganic film UIL covering the light emitting element ED will be described. Through Figures 7a to 7jThe formed display panel DP can correspond to Figure 5 the display panel DP.

[0132] Referring to Figure 7a , the method for manufacturing a display panel according to the present invention may include a step of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, an anode AE, a preliminary sacrificial pattern SP-I, and a pixel definition film PDL.

[0133] The circuit element layer DP-CL may be formed by a conventional manufacturing process of circuit elements, and the specific manufacturing process is as follows: an insulating layer, a semiconductor layer, and a conductive layer are formed by coating, deposition, etc., and the insulating layer, semiconductor layer, and conductive layer are selectively patterned by photolithography and etching processes to form a semiconductor pattern, a conductive pattern, signal lines, etc.

[0134] The anode AE and the preliminary sacrificial pattern SP-I may be formed by the same patterning process. The pixel definition film PDL may be formed to cover the anode AE and the preliminary sacrificial pattern SP-I on the base layer BL.

[0135] Referring to Figure 7b , the method for manufacturing a display panel according to the present invention may include a step of forming a first preliminary partition layer L1-I on the preliminary display panel DP-I (refer to Figure 7a ). The first preliminary partition layer L1-I may be formed on the pixel definition film PDL by a deposition process of a conductive material. The first preliminary partition layer L1-I may include a metal, a transparent conductive oxide (TCO: Transparent Conductive Oxide), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO: Indium Gallium Zinc Oxide), or aluminum zinc oxide.

[0136] Referring to Figure 7c, the manufacturing method of the display panel of the present invention may include the step of forming a second preliminary partition layer L2-I on the first preliminary partition layer L1-I. The second preliminary partition layer L2-I can be formed on the first preliminary partition layer L1-I through a deposition process of a conductive material. The second preliminary partition layer L2-I may include a metal, a transparent conductive oxide (TCO: Transparent Conductive Oxide), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO: IndiumGallium Zinc Oxide), or aluminum zinc oxide.

[0137] Referring to Figure 7d , the manufacturing method of the display panel of the present invention may include the step of forming a first photoresist layer PR1. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the second preliminary partition layer L2-I and then patterning the preliminary photoresist layer using a photolithography mask. Through the patterning process, a photolithography opening OP-PR can be formed in the first photoresist layer PR1. The photolithography opening OP-PR can overlap with the anode AE.

[0138] Then, the manufacturing method of the display panel of the present invention may include the step of forming a partition wall PW having a partition wall opening OP-P and a part having an inverted cone shape by etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I (referring to Figure 7c ). The step of forming the partition wall PW may include the step of forming a first partition layer L1 and a second partition layer L2. The second partition layer L2 of the present invention may have an inverted cone shape. The length of the upper surface U-L2 (referring to Figure 5 ) of the second partition layer L2 in one direction may be greater than the length of the lower surface B-L2 (referring to Figure 5 ) in one direction. At this time, one direction may be perpendicular to the thickness direction of the base layer BL. For example, one direction may correspond to the first direction DR1 or the second direction DR2. The detailed content will be described later in Figures 8a to 9c .

[0139] After that, referring to Figure 7e, the manufacturing method of the display panel of the present invention may include a step of forming a light-emitting opening OP-E overlapping with the partition opening OP-P by etching a pixel definition layer PDL.

[0140] In the step of etching the pixel definition layer PDL, the first photoresist layer PR1 and the partition PW (for example, the second partition layer L2) can be used as a mask to perform dry etching on the pixel definition layer PDL. The portion of the pixel definition layer PDL that does not overlap with the first photoresist layer PR1 and the partition PW can be etched and removed. As a result, a light-emitting opening OP-E overlapping with the partition opening OP-P can be formed in the pixel definition layer PDL.

[0141] Moreover, the manufacturing method of the display panel of the present invention may include a step of forming a sacrificial pattern SP having a sacrificial opening OP-S overlapping with the light-emitting opening OP-E by etching a preliminary sacrificial pattern SP-I (refer to Figure 7d ).

[0142] In the step of etching the preliminary sacrificial pattern SP-I, the first photoresist layer PR1 and the partition PW (for example, the second partition layer L2) can be used as a mask to perform wet etching on the preliminary sacrificial pattern SP-I. The portion of the preliminary sacrificial pattern SP-I that does not overlap with the first photoresist layer PR1 and the partition PW can be etched and removed. As a result, the sacrificial pattern SP can be formed from the preliminary sacrificial pattern SP-I. A sacrificial opening OP-S can be formed in the sacrificial pattern SP.

[0143] The etching process of the sacrificial pattern SP can be performed in an environment where the etching selectivity ratio between the sacrificial pattern SP and the anode AE is high, thereby preventing the anode AE from being etched together. That is, by arranging the sacrificial pattern SP with an etching rate higher than that of the anode AE between the pixel definition layer PDL and the anode AE, the anode AE can be prevented from being damaged by being etched together during the etching process.

[0144] After that, referring to Figure 7f , the manufacturing method of the display panel of the present invention may include a step of forming a light-emitting element ED in the light-emitting opening OP-E and the partition opening OP-P after removing the first photoresist layer PR1 (refer to Figure 7e ). The step of forming the light-emitting element ED may include a step of forming a light-emitting pattern EP and a step of forming a cathode CE.

[0145] The step of forming the light-emitting pattern EP may include a deposition process of a light-emitting layer. For example, the step of forming the light-emitting pattern EP may include a step of performing thermal evaporation on the light-emitting layer. The light-emitting layer may be formed at the tip of the partition wall PW so as to be deposited on the partition wall opening OP-P and the partition wall PW. The light-emitting layer formed in the partition wall opening OP-P may form the light-emitting pattern EP, and the light-emitting layer formed on the partition wall PW may include a first dummy layer D1. That is, the light-emitting pattern EP may be formed to overlap the partition wall opening OP-P on the anode AE.

[0146] The first dummy layer D1 formed together in the step of forming the light-emitting pattern EP may include an organic substance. For example, the first dummy layer D1 may include the same substance as the light-emitting pattern EP. The first dummy layer D1 and the light-emitting pattern EP may be formed simultaneously by one process and may be formed separately from the light-emitting pattern EP by the undercut shape of the partition wall PW.

[0147] The step of forming the cathode CE may include a deposition process of a cathode layer. For example, the step of forming the cathode CE may include a step of performing sputtering on the cathode layer. The cathode layer may be formed at the tip of the partition wall PW so as to be deposited inside the partition wall opening OP-P and on the partition wall PW. The cathode layer formed in the partition wall opening OP-P may form the cathode CE, and the cathode layer formed on the partition wall PW may form a second dummy layer D2. That is, the cathode CE may be formed to overlap the partition wall opening OP-P on the light-emitting pattern EP. And, the cathode CE may be formed to contact the first inner surface S-L1 of the first partition layer L1 (refer to Figure 5 ) and extend along the first inner surface S-L1 of the first partition layer L1.

[0148] The second dummy layer D2 formed together in the step of forming the cathode CE may include a conductive substance. For example, the second dummy layer D2 may include the same substance as the cathode CE. The second dummy layer D2 and the cathode CE may be formed simultaneously by one process and may be formed separately from the cathode CE by the undercut shape of the partition wall PW.

[0149] The anode AE, the light-emitting pattern EP, and the cathode CE may be stacked in sequence along the third direction DR3. The anode AE, the light-emitting pattern EP, and the cathode CE may form a light-emitting element ED.

[0150] Refer to Figures 7g to 7h , the method of manufacturing a display panel according to the present invention may include a step of forming a lower encapsulation inorganic pattern LIL.

[0151] First, refer to Figure 7g, the step of forming the lower encapsulation inorganic pattern LIL may include the step of depositing a lower encapsulation inorganic layer LIL-I. In one embodiment, the lower encapsulation inorganic layer LIL-I may be formed by a chemical vapor deposition (CVD: Chemical Vapor Deposition) process. The lower encapsulation inorganic layer LIL-I may be formed to cover the cathode CE and the partition wall PW. A part of the lower encapsulation inorganic layer LIL-I may fill the partition wall opening OP-P.

[0152] After that, the method for manufacturing a display panel of the present invention may include the step of forming a second photoresist layer PR2. In the step of forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by patterning a preliminary photoresist layer using a photomask after the preliminary photoresist layer is formed. Through the patterning process, the second photoresist layer PR2 may be formed in a pattern form corresponding to the light-emitting element ED.

[0153] Refer to Figure 7h , the step of forming the lower encapsulation inorganic pattern LIL may include the step of removing the portion of the lower encapsulation inorganic layer LIL-I (refer to Figure 7g ) that does not overlap with the light-emitting element ED.

[0154] In the step of removing the portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light-emitting element ED, the second photoresist layer PR2 may be used as a mask to perform dry etching on the lower encapsulation inorganic layer LIL-I. The portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the second photoresist layer PR2 may be removed, and the remaining portion of the lower encapsulation inorganic layer LIL-I that is not etched may be formed into the lower encapsulation inorganic pattern LIL.

[0155] Refer to Figure 7i , the method for manufacturing a display panel of the present invention may include the step of removing the dummy layers D1, D2 (refer to Figure 7i ) after removing the second photoresist layer PR2 (refer to Figure 7h ). The second dummy layer D2 in the dummy layers D1, D2 may be removed by wet etching, and the first dummy layer D1 in the dummy layers D1, D2 may be removed using a stripper.

[0156] After that, refer to Figure 7j, the method for manufacturing a display panel according to the present invention may include the step of completing the display panel DP by forming a packaging organic film OL and an upper packaging inorganic film UIL. The packaging organic film OL may be formed by coating an organic material by an inkjet method, but is not limited thereto. The packaging organic film OL provides a flattened upper surface. Thereafter, the upper packaging inorganic film UIL may be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0157] Figures 8a to 8c is a cross-sectional view showing a part of the steps in the method for manufacturing a display panel according to an embodiment of the present invention. In the description Figures 8a to 8c when, for the components that are the same / similar as those Figures 1a to 7j described with reference to Figures 8a to 8c The process in Figure 7c and Figure 7d corresponds to the process of Figures 8a to 8c The display panel DP formed by the process of Figure 6a corresponds to the display panel DP of

[0158] Referring to Figure 7c and Figure 8a , the method for manufacturing a display panel according to an embodiment may include the step of forming a second preliminary partition layer L2-I on a first preliminary partition layer L1-I. The step of forming the second preliminary partition layer L2-I on the first preliminary partition layer L1-I may include the following steps: depositing a first sub-layer L21 on the first preliminary partition layer L1-I; depositing a second sub-layer L22 on the first sub-layer L21; and depositing a third sub-layer L23 on the second sub-layer L22. The etching rate of the first sub-layer L21 may be greater than the etching rate of the second sub-layer L22, and the etching rate of the second sub-layer L22 may be greater than the etching rate of the third sub-layer L23. For example, the first sub-layer L21 may include tantalum (Ta), the second sub-layer L22 may include niobium (Nb), and the third sub-layer L23 may include titanium (Ti).

[0159] Referring to Figure 7d and Figure 8b , the step of forming a partition PW (refer to Figure 8c ) having a partition opening OP-P (refer to Figure 8c ) by etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I may include the step of forming a preliminary partition opening OP-PI by dry-etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I.

[0160] In the step of forming the preliminary partition opening OP-PI, the first photoresist layer PR1 can be used as a mask to perform dry etching on the first preliminary partition layer L1-I and the second preliminary partition layer L2-I. The portions of the first preliminary partition layer L1-I and the second preliminary partition layer L2-I that do not overlap with the first photoresist layer PR1 can be etched and removed. For example, the preliminary partition opening OP-PI can be formed in the portion that overlaps with the photolithography opening OP-PR and is removed. The dry etching process can be performed in an etching environment where the etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I is substantially the same. Accordingly, the inner surfaces of the first preliminary partition layer L1-I and the second preliminary partition layer L2-I that define the preliminary partition opening OP-PI can be substantially aligned.

[0161] After that, referring to Figure 7d and Figure 8c , the step of forming the partition PW having the partition opening OP-P by etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I (refer to Figure 8b ) can include the step of forming the first partition layer L1 and the second partition layer L2 having an inverted cone shape by wet etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I.

[0162] In the step of wet etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I, the first photoresist layer PR1 can be used as a mask to perform wet etching on the first preliminary partition layer L1-I and the second preliminary partition layer L2-I. Accordingly, the first partition layer L1 that is recessed outward and the second partition layer L2 having an inverted cone shape can be formed, and the partition opening OP-P can be formed.

[0163] The first sub-layer L21 with a larger etching rate can be etched more than the second sub-layer L22 and the third sub-layer L23 with relatively smaller etching rates, and the third sub-layer L23 with a smaller etching rate can be etched less than the first sub-layer L21 and the second sub-layer L22 with relatively larger etching rates. As a result, the length of the sub-layer in one direction can decrease as it approaches the first partition layer L1. That is, the second partition layer L2 can have an inverted cone shape.

[0164] Moreover, the wet etching process in the present invention can be carried out in an environment with a high etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I. Accordingly, the inner surface of the partition wall PW defining the partition opening OP-P can have an undercut shape in cross-section. Specifically, since the etching rate of the first preliminary partition layer L1-I with respect to the etching solution is greater than that of the second preliminary partition layer L2-I, the first preliminary partition layer L1-I can be mainly etched. Accordingly, the first inner surface S-L1 of the first partition layer L1 (refer to Figure 5 ), can be formed to be more recessed outward than the second inner surface S-L2 of the second partition layer L2 (refer to Figure 5 ). By the portion of the second partition layer L2 that protrudes inward more than the first partition layer L1, a tip portion can be formed in the partition wall PW.

[0165] The partition opening OP-P can include a first region A1 defined by the first inner surface S-L1 of the first partition layer L1 and a second region A2 defined by the second inner surface S-L2 of the second partition layer L2, and the length of the first region A1 in the direction perpendicular to the base layer BL can be greater than the length of the second region A2 in the direction perpendicular to the base layer BL.

[0166] Figures 9a to 9c is a cross-sectional view showing some steps in the method of manufacturing a display panel according to an embodiment of the present invention. In the description Figures 9a to 9c , the same / similar reference numerals are used to describe the same / similar components as those described with reference to Figures 1a to 7j , and repeated descriptions are omitted. Figures 9a to 9c The process in Figure 7c and Figure 7d , and the display panel DP formed by the process in Figures 9a to 9c corresponds to the display panel DP in Figure 6b .

[0167] Refer to Figure 7c and Figure 9a, The manufacturing method of a display panel according to an embodiment may include the step of forming a second preliminary partition layer L2a-I on a first preliminary partition layer L1-I. The step of forming the second preliminary partition layer L2a-I on the first preliminary partition layer L1-I may include the following steps: depositing an inorganic material at a first speed; and depositing the inorganic material at a second speed. The first speed may be greater than the second speed. That is, the deposition apparatus may deposit the inorganic material on the first preliminary partition layer L1-I while gradually reducing the speed. As a result, the density of the second preliminary partition layer L2a-I may increase as it is farther away from the first preliminary partition layer L1-I. As a result, the second preliminary partition layer L2a-I may include an inorganic material. For example, the second preliminary partition layer L2a-I may include silicon nitride (SiN x , or silicon nitride).

[0168] Referring to Figure 7d and Figure 9b , the step of forming a partition PWa having a partition opening OP-Pa (refer to Figure 9a ) by etching the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I (refer to Figure 9c ) may include the step of forming a second partition layer L2a having an inverted cone shape by dry etching the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I. Figure 9c )

[0169] In the step of forming the second partition layer L2a, the first photoresist layer PR1 may be used as a mask to dry-etch the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I. The portions of the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I that do not overlap with the first photoresist layer PR1 may be etched and removed. And, a portion of the second partition layer L2a that is closer to the first partition layer L1 and has a smaller density may be etched more than another portion of the second partition layer L2a that has a relatively larger density. As a result, the length of the second partition layer L2a in one direction may decrease as it is closer to the first partition layer L1. That is, the second partition layer L2a may have an inverted cone shape.

[0170] After that, referring to Figure 7d and Figure 9c , the step of forming a partition PWa having a partition opening OP-Pa by etching the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I (refer to Figure 9a ) may include the step of forming a first partition layer L1 by wet etching the first preliminary partition layer L1-I.

[0171] In the step of wet etching the first preliminary partition layer L1-I, the first photoresist layer PR1 can be used as a mask to perform wet etching on the first preliminary partition layer L1-I. Accordingly, a first partition layer L1 with a recess toward the outside can be formed, and a partition opening OP-P can be formed.

[0172] The wet etching process in the present invention can be carried out in an environment with a high etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2a-I. Accordingly, the inner surface of the partition PWa defining the partition opening OP-Pa can have an undercut shape in cross-section. Specifically, since the etching rate of the first preliminary partition layer L1-I with respect to the etching solution is greater than the etching rate of the second preliminary partition layer L2a-I, the first preliminary partition layer L1-I can be mainly etched. Accordingly, the first inner surface S-L1 of the first partition layer L1 (refer to Figure 5 ) can be formed to be more recessed toward the outside than the second inner surface S-L2 of the second partition layer L2a (refer to Figure 5 ). By the portion of the second partition layer L2a that protrudes more than the first partition layer L1, a tip portion can be formed in the partition PWa.

[0173] The partition opening OP-Pa can include a first region A1a defined by the first inner surface S-L1 of the first partition layer L1 and a second region A2a defined by the second inner surface S-L2 of the second partition layer L2a, and the length of the first region A1a in the direction perpendicular to the base layer BL can be greater than the length of the second region A2a in the direction perpendicular to the base layer BL.

[0174] As mentioned above, although the present invention has been described with reference to the preferred embodiments, those skilled in the art or those with ordinary knowledge in the technical field can understand that various modifications and changes can be made to the present invention without departing from the spirit of the present invention described in the claims and the technical field. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display panel, comprising: A base layer; A pixel definition film disposed on the base layer and having a light-emitting opening; Partition walls disposed on the pixel definition film and having partition wall openings overlapping with the light-emitting opening; And A light-emitting element including an anode, a light-emitting pattern, and a cathode in contact with the partition walls, and disposed within the light-emitting opening and the partition wall opening, Wherein, the partition walls include: a first partition wall layer disposed on the pixel definition film; and a second partition wall layer disposed on the first partition wall layer and having an inverted cone shape.

2. The display panel according to claim 1, wherein, The second partition wall layer includes a tip portion protruding inward compared to the first partition wall layer.

3. The display panel according to claim 1, wherein, The second partition wall layer includes: A lower surface protruding inward compared to a first inner surface of the first partition wall layer; A second inner surface extending in a direction away from the base layer from the lower surface; and An upper surface extending in a direction parallel to the lower surface from the second inner surface, Wherein, an angle formed by the lower surface and the second inner surface is an obtuse angle.

4. The display panel according to claim 3, wherein, An area of the anode exposed through the light-emitting opening is defined as a light-emitting area, The second inner surface is closer to the center of the light-emitting area than the first inner surface.

5. The display panel according to claim 3, wherein, A length of the upper surface of the second partition wall layer in a direction is greater than a length of the lower surface of the second partition wall layer in the direction, and the direction is perpendicular to a thickness direction of the base layer.

6. The display panel according to claim 3, further comprising: A lower encapsulation inorganic pattern covering the light-emitting element, Wherein, the lower encapsulation inorganic pattern is in overall contact with the second inner surface of the second partition wall layer.

7. The display panel according to claim 6, further comprising: An encapsulation organic film covering the lower encapsulation inorganic pattern.

8. The display panel according to claim 7, wherein, The second partition wall layer includes a plurality of sub-layers.

9. The display panel according to claim 8, wherein, An etching rate of a sub-layer close to the first partition wall layer is greater than an etching rate of a sub-layer close to the encapsulation organic film.

10. The display panel according to claim 8, wherein, A length of a sub-layer close to the first partition wall layer in a direction is less than a length of a sub-layer close to the encapsulation organic film in the direction, The direction is perpendicular to a thickness direction of the base layer.

11. The display panel according to claim 7, wherein, The second partition wall layer includes an inorganic substance.

12. The display panel according to claim 11, wherein, Further comprising: A density of the second partition wall layer decreases as it approaches the first partition wall layer from the encapsulation organic film.

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