Circuit board defect detection method and system based on multi-band impedance matching

Abstract

The invention discloses a circuit board defect detection method and system based on multi-band impedance matching, and relates to the technical field of circuit board quality inspection, and the method comprises the steps: determining corresponding test bias voltages of a reconfigurable impedance matching network at a plurality of test frequency points according to a band bias voltage relation table; for each test frequency point, test bias voltage matched with the test frequency point is applied to each adjustable element, and a radio frequency signal is injected into the circuit board to be tested, so that a corresponding reflection coefficient is acquired through a test probe; based on the multi-frequency sparse dictionary and a compressed sensing algorithm, reconstructing a three-dimensional scattering image in the circuit board; and calculating negative logarithm likelihood distribution corresponding to the three-dimensional scattering image, and respectively solving a hierarchy anomaly score of the corresponding circuit physical layer by combining the spatial information of each circuit physical layer so as to screen at least one abnormal circuit physical layer. Therefore, signal feature reconstruction is used for replacing high-precision physical imaging, and hierarchical space identification of circuit board defects is realized.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit board quality inspection, and in particular, to a method and system for detecting printed circuit board defects based on multi-band impedance matching. Background Art

[0002] With the large-scale deployment of 5G, millimeter-wave radar, and in-vehicle millimeter-wave communication terminals, printed circuit boards (PCBs) have developed towards high-density interconnect (HDI), multi-layer blind buried vias, and fine line widths and pitches, greatly improving the radio frequency, power supply, and signal integrity performance on the board. However, it also brings severe challenges to the detection of hidden defects on PCBs (such as micro-via cracks, dielectric layer peeling, conductor interlayer short circuits, etc.).

[0003] Currently, the commonly used PCB defect detection methods mainly include automated optical inspection (AOI), X-ray inspection (AXI), and in-circuit test (ICT). However, when faced with hidden PCB defects, there are often detection blind spots and it is difficult to accurately reflect the changes in electrical performance.

[0004] Specifically, AOI identifies surface solder joint defects or component misalignment through image comparison, but is powerless against hidden defects such as internal layer short circuits and micro-cracks; although AXI can penetrate multi-layer structures, its equipment cost is high, and it is difficult to distinguish signal integrity defects caused by small impedance mismatches; ICT verifies circuit connectivity and component parameters by probing test points, but it relies on pre-designed test points, cannot cover high-density interconnect areas (such as the bottom of BGA packages), and the probing contact pressure may damage the precision circuit.

[0005] In recent years, some studies have tried to indirectly detect defects by analyzing the impedance characteristics of printed circuit boards. For example, injecting a single-band signal into the printed circuit board and measuring the reflection coefficient, and judging whether there is an open circuit or a short circuit through impedance mismatch. However, the impedance response of a single frequency is only sensitive to specific types of defects (such as low frequencies being sensitive to macroscopic defects and high frequencies being sensitive to microscopic defects), and it is difficult to meet the detection requirements of multiple types of defects. Summary of the Invention

[0006] This application provides a method, system, storage medium, computer program product, and electronic device for detecting printed circuit board defects based on multi-band impedance matching, so as to at least solve the problem of insufficient ability to identify hidden defects in the detection of high-density interconnect and multi-layer structure printed circuit boards in the current related technologies.

[0007] In a first aspect, an embodiment of the present application provides a method for detecting circuit board defects based on multi-band impedance matching, including: determining corresponding test bias voltages of a reconfigurable impedance matching network at multiple test frequencies according to a frequency band bias voltage relationship table; the reconfigurable impedance matching network includes a plurality of adjustable elements and is coupled to a test probe, and the frequency band bias voltage relationship table includes the relationship between a plurality of pre-calibrated frequencies and bias voltages for a defect-free circuit board; for each of the test frequencies, applying a test bias voltage matching the test frequency to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network at the corresponding test frequency and the circuit board under test, and injecting a radio frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe; analyzing the reflection coefficients corresponding to each of the test frequencies based on a multi-frequency sparse dictionary and a compressive sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board; calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtaining the hierarchical anomaly scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0008] In a second aspect, an embodiment of the present application provides a system for detecting circuit board defects based on multi-band impedance matching, including: a reconstruction bias determination unit for determining corresponding test bias voltages of a reconfigurable impedance matching network at multiple test frequencies according to a frequency band bias voltage relationship table; the reconfigurable impedance matching network includes a plurality of adjustable elements and is coupled to a test probe, and the frequency band bias voltage relationship table includes the relationship between a plurality of pre-calibrated frequencies and bias voltages for a defect-free circuit board; a bias impedance matching unit for, for each of the test frequencies, applying a test bias voltage matching the test frequency to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network at the corresponding test frequency and the circuit board under test, and injecting a radio frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe; a three-dimensional scattering reconstruction unit for analyzing the reflection coefficients corresponding to each of the test frequencies based on a multi-frequency sparse dictionary and a compressive sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board; an abnormal layer identification unit for calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtaining the hierarchical anomaly scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0009] In a third aspect, an electronic device is provided, which includes: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of the present application.

[0010] In a fourth aspect, an embodiment of the present application provides a storage medium, on which a computer program is stored, characterized in that when the program is executed by a processor, it implements the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of the present application.

[0011] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of the present application.

[0012] By means of a circuit board defect detection method and system based on multi-band impedance matching provided by the present application, the following technical effects can be at least achieved:

[0013] (1) By applying bias voltages matching them at three or more test frequency points of low, medium, and high frequencies respectively, the high sensitivity response of low-frequency signals to macroscopic defects such as large open circuits and dielectric layer peeling can be utilized, and the sensitive capture of high-frequency signals to microscopic discontinuities such as via micro-cracks and different-layer short circuits can be utilized. Compared with single-frequency detection, the compatibility is greatly enhanced. In addition, by combining a multi-frequency sparse dictionary with a compressive sensing algorithm, high-fidelity reconstruction of the signal characteristics of multiple types of defects is realized without increasing the number of measurement points, and the detection blind area caused by frequency bias can be effectively avoided.

[0014] (2) By setting a reconfigurable impedance matching network, and the reconfigurable impedance matching network can dynamically adjust reactance elements according to the pre-calibrated "frequency point - bias voltage" relationship, so that the measured PCB is in the best impedance matching state at each frequency point. Thereby, the injection efficiency of radio frequency signals and the signal-to-noise ratio of reflection coefficient measurement are significantly improved, so that stable and distinguishable reflection signals can be obtained even in high-density interconnection or the bottom area of BGA, and the measurement error introduced by mismatch is greatly suppressed.

[0015] (3) Based on the set of reflection coefficients at each frequency point and the multi-frequency sparse reconstruction algorithm, directly reconstruct the three-dimensional scattering distribution image inside the PCB, which helps to quantitatively identify the specific geometric shape of the defect, breaking through the limitation of traditional two-dimensional projection detection for deep defects. In addition, by calculating the negative log-likelihood distribution of the three-dimensional scattering image and combining the spatial information of each physical layer, an anomaly score can be output for each layer (copper foil, dielectric layer, blind via layer, etc.), realizing high-precision diagnosis of the detection system and targeted maintenance suggestions for the PCB production line in terms of spatial identification of the layer where the defect is located.

[0016] Through this technical solution, using signal feature reconstruction instead of high-precision physical imaging effectively reduces the dependence on high-end imaging equipment. At the same time, the testing process is non-contact, avoiding mechanical damage to the circuit structure, and has good automation capabilities, being suitable for on-line detection on the circuit board production line. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 FIG. shows a flowchart of an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of the present application;

[0019] Figure 2 FIG. shows a schematic structural connection diagram of an example of a reconfigurable impedance matching network according to an embodiment of the present application;

[0020] Figure 3 FIG. shows an operation flowchart of an example of generating a frequency band offset voltage relationship table according to an embodiment of the present application;

[0021] Figure 4 FIG. shows a flowchart of an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of the present application;

[0022] Figure 5 FIG. shows an effect schematic diagram of an example of a circuit board defect type according to an embodiment of the present application;

[0023] Figure 6 FIG. shows a schematic structural block diagram of an example of a circuit board defect detection system based on multi-band impedance matching according to an embodiment of the present application;

[0024] Figure 7 FIG. is a schematic structural diagram of an embodiment of an electronic device of the present application. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0026] It should be noted that since the conductive path and dielectric material of the PCB determine its impedance characteristics at different frequencies, any defects in the manufacturing process (such as poor soldering, cracks, open circuits, short circuits, uneven dielectric layer thickness, etc.) may cause local impedance changes. Therefore, by accurately measuring the impedance of the circuit board through impedance detection technology, it is possible to effectively determine whether there are structural or electrical abnormalities.

[0027] Currently, the common impedance detection technologies are TDR (Time Domain Reflectometry) and TFDR (Transform-domain / Frequency-domain Reflectometry), which are widely used to detect faults and defects in high-frequency transmission lines including PCBs.

[0028] However, TDR / TFDR belongs to single-frequency detection technologies. The detection system usually injects electromagnetic pulses into the PCB in a fixed frequency band of 1 GHz to 5 GHz and judges the abnormalities of the transmission line and via by measuring the pulse reflection waveform. However, this single-frequency pulse signal faces a "resolution-penetration" conflict in practical applications: Although the high-frequency band pulse has a short rising edge and can achieve high-resolution imaging of sub-millimeter or even micron-level cracks, the high-frequency signal attenuates extremely severely in multi-layer HDI boards, resulting in attenuation of the reflected echo amplitude and a decrease in the signal-to-noise ratio; on the contrary, although the low-frequency band pulse has low attenuation and deep penetration and can cover hidden defects such as inner layer delamination and voids, its resolution ability is insufficient and it is difficult to detect micro-via cracks and fine dielectric delamination. On the other hand, the impedance matching network of the TDR / TFDR detection system mostly uses a fixed LC device combination or a manually pluggable matching module and cannot be dynamically optimized online according to different board types and different test frequency bands.

[0029] It should be understood that the purpose of the above description of the current related technologies is only to facilitate the public to better understand the inventive spirit and motivation of the present application and is not regarded as a limitation of the present application. In addition, the technical solutions described in the above current related technologies are not prior art and may also be unpublished technical solutions, such as those under research or in the laboratory stage.

[0030] In the technical solution of this application, for the processing of the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved, etc., it complies with the provisions of relevant laws and regulations and does not violate public order and good customs.

[0031] Figure 1 The flowchart of an example of the circuit board defect detection method based on multi-band impedance matching according to an embodiment of this application is shown.

[0032] Regarding the execution subject of the method of the embodiment of this application, it can be any controller or processor with computing or processing capabilities. Specifically, it can be implemented by the PCB online quality inspection system platform. Through the organic integration of multi-frequency impedance matching, sparse reconstruction, and hierarchical quantitative analysis, it not only makes up for the blind spots of the AOI / AXI / ICT methods in detecting hidden defects, but also provides a high-precision and low-cost PCB online quality inspection solution for high-density interconnect and multi-layer blind buried via boards.

[0033] In some examples, it can be integrated and configured in an electronic device or terminal in a software, hardware, or software-hardware combination manner, and the types of terminals or electronic devices can be diverse, such as mobile phones, tablets, or desktop computers, etc.

[0034] As Figure 1 As shown, in step S110, according to the frequency band bias voltage relationship table, the corresponding test bias voltages of the reconfigurable impedance matching network at multiple test frequency points are determined.

[0035] Here, the reconfigurable impedance matching network includes multiple adjustable elements and is coupled to the test probe, and the frequency band bias voltage relationship table includes the relationship between multiple pre-calibrated frequency points and bias voltages for a defect-free circuit board. In some embodiments, the frequency band bias voltage relationship table can be completed in the system pre-calibration stage, and its purpose is to record the bias voltages required for impedance matching corresponding to different radio frequency test frequency points in the defect-free state of the circuit board to be tested. Regarding the acquisition method of the frequency band bias voltage relationship table, it can be diverse. For example, it can be provided by a third-party manufacturer, or it can also be pre-calibrated according to the defect-free circuit board samples to be tested, and no restrictions should be made here temporarily.

[0036] Exemplarily, in the system pre-calibration stage, at multiple preset radio frequency frequency points, by adjusting the bias voltages of the adjustable elements (such as voltage-controlled capacitors, varactor diodes, microelectromechanical switches, etc.), the control voltages at the minimum value of the best reflection coefficient are collected, and then the optimal matching bias voltages obtained at each frequency point are stored in the relationship table to form the frequency band bias voltage relationship table.

[0037] Thus, by pre-calibrating and forming a high-precision bias voltage-frequency mapping relationship, fast and accurate impedance matching settings are achieved. At the same time, the adjustable components are linked with the test frequency to be adjusted, improving the adaptability of the system in multi-frequency detection.

[0038] In step S120, for each test frequency point, by applying a test bias voltage matching the test frequency point to each adjustable component, impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency point is achieved, and a radio frequency signal is injected into the circuit board under test to collect the corresponding reflection coefficient through the test probe.

[0039] Here, the system applies voltages to multiple adjustable components respectively according to the obtained bias voltage values of the matching, so that the equivalent input impedance of the entire impedance matching network is conjugate-matched with the port impedance of the circuit board under test at this frequency point, ensuring that the test energy can be injected into the circuit board under test to the maximum extent. After completing the impedance matching, the system injects a radio frequency signal of the corresponding test frequency point into the circuit board under test. At the same time, the signal reflected from inside the circuit board is collected through the vector network analysis module or the reflection coefficient detection module and stored as a complex reflection coefficient. The amplitude and phase of the reflection coefficient contain the electromagnetic response characteristics of the circuit board under test at this frequency.

[0040] In some embodiments, the MCU can index the optimal bias vector corresponding to the current frequency point f i from the EEPROM and convert it into an analog voltage signal through a multi-channel DAC, outputting it to the bias amplification module to amplify the DAC output to the working range of the adjustable components (PIN diodes or variable capacitors). Finally, each amplified bias passes through a low-leakage multi-channel switching array and is added to the corresponding components of the matching network respectively.

[0041] In addition, a Vector Network Analyzer (VNA) is provided in the system, which is configured with a radio frequency signal source and a vector receiver to be responsible for outputting a continuous wave at f i . The MCU controls through SPI to quickly switch the radio frequency path from the VNA to the test probe. The probe end of the test probe integrates a directional coupler. One path injects the signal into the PCB, and the other path couples the reflected signal to the vector receiver. The vector receiver measures the reflection coefficient and outputs a complex value Γ(f i ) = |Γ|e j∠Γ . Thus, through accurate impedance matching at multiple frequency points, high-energy injection and low reflection are ensured, the response sensitivity of the system to different structural defects is improved, and rich characteristic information is provided through multi-point frequency domain response recording.

[0042] Figure 2Shows a schematic structural connection diagram of an example of a reconfigurable impedance matching network according to an embodiment of the present application.

[0043] The reconfigurable impedance matching network includes a plurality of tunable elements coupled to test probes. In some examples, the tunable elements are PIN diode arrays, and each PIN diode realizes a radio frequency conduction state or a cut-off state by applying a forward or reverse bias current. The PIN diode arrays are integrated in series or in parallel in the main signal path or the bypass branch of the reconfigurable impedance matching network. By testing the bias voltage, the conduction combination of different PIN diodes in the PIN diode array is controlled to change the equivalent inductance and / or equivalent capacitance of the corresponding branch, so as to realize the impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency points.

[0044] As Figure 2 shown, the reconfigurable impedance matching network includes a series PIN diode array composed of D1, D2, and D3 and a parallel PIN diode array composed of D4 and D5.

[0045] In this embodiment, the test probe is connected to the input end of the RF channel, and this channel includes a plurality of PIN diodes (such as D1, D2, D3) connected in series in sequence for constructing the main signal transmission path. Each PIN diode can control its conduction state in the radio frequency signal band according to the applied bias voltage. Exemplarily, when a forward bias current is applied, the PIN diode enters a low-resistance conduction state, and when a reverse bias or no bias is applied, the diode presents a high-resistance cut-off state.

[0046] In addition, through the PIN diodes of multiple parallel branches (such as D4 and D5), these parallel branches are grounded and used as a bypass tuning network, which is mainly used to adjust the local impedance characteristics near this node to form a controllable resonance or impedance compensation behavior. Thus, through the combination of series diodes and parallel diodes, the series branch mainly controls the high-pass characteristic of the network, and the parallel branch mainly controls the low-pass characteristic. The two cooperate to achieve broadband flat impedance matching, enabling the matching network to maintain low reflection throughout the test frequency band, realizing a radio frequency path with "dynamically programmable impedance characteristics", and being able to selectively conduct some PIN diodes according to the test requirements of different frequency points to adjust the equivalent impedance parameters (including inductance and capacitance characteristics) of the signal path.

[0047] In step S130, based on the multi-frequency sparse dictionary and the compressive sensing algorithm, the reflection coefficients corresponding to each test frequency point are analyzed to reconstruct the three-dimensional scattering image inside the circuit board.

[0048] Here, based on the multi-frequency point reflection coefficient data, by adopting sparse signal processing and inverse imaging technology, the internal structure of the circuit board is modeled and visually reconstructed.

[0049] In some embodiments, first, the multi-frequency reflection coefficient is mapped into the scattering model of the spatial structure to construct an inverse problem that associates the frequency-domain observables with the spatial scattering distribution. Then, using a pre-trained or pre-constructed multi-frequency sparse dictionary, the scattering distribution is represented as a superposition of a set of sparse basis functions, thus transforming the high-dimensional reconstruction problem into a sparse coefficient solution. Based on the compressive sensing theory, by minimizing the observation error and the sparse regularization term, the corresponding sparse scattering coefficients are recovered. Finally, the obtained sparse coefficients are mapped back to the three-dimensional spatial domain to obtain the electromagnetic scattering intensity distribution map of the circuit board at each physical layer, forming a three-dimensional visual image of the internal structure. Thus, the scattering image not only reflects the structural geometry but also implies the field distribution anomalies caused by electromagnetic parameters (such as dielectric constant changes, conductor gaps, etc.), which can significantly enhance the ability to perceive non-structural defects.

[0050] In step S140, calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtain the layer-level anomaly scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0051] In some embodiments, the three-dimensional scattering image is spatially stratified and divided into several partitions corresponding to the physical structure of the circuit board (such as signal layer, ground layer, power supply layer, dielectric layer, etc.). Probability modeling is performed on the scattering intensity distribution within each layer, and its negative log-likelihood distribution relative to the defect-free sample is calculated to measure the deviation degree between this region and the normal sample. According to the probability deviation degree of each layer, calculate its corresponding layer-level anomaly score, which reflects the possibility of defects in this layer. Perform threshold discrimination or sorting on the anomaly scores to screen out one or more physical layers with the most abnormal characteristics. Finally, output the physical layer regions suspected of having defects and their positions in the three-dimensional space for manual re-inspection or automatically generate repair suggestions for the PCB production line.

[0052] Thus, using the probability statistical method to evaluate the scattering anomaly degree of different physical layers, realizing the spatial positioning and layer identification of defects, can effectively distinguish the defect responses in different physical structures and reduce the misjudgment risk of surface layer covering deep layer defects.

[0053] Figure 3 The operation flowchart showing an example of generating a frequency band offset voltage relationship table according to an embodiment of the present application is shown.

[0054] As Figure 3 shown, in step S310, obtain a preset frequency point set and an initial offset voltage vector.

[0055] It should be noted that in the multi - band impedance matching detection framework, it is necessary to cover the key frequency bands of the PCB that may affect the signal, and a series of typical communication or test frequencies (such as 0.7 GHz, 2 GHz, 5 GHz, 9 GHz, etc.) can be selected to form a set of preset frequency points. Each frequency point corresponds to a scenario where the interaction between electromagnetic waves and the PCB medium and copper foil structure is the most sensitive.

[0056] In addition, in order to achieve high - quality impedance matching at these frequency points, it is necessary to systematically explore the bias voltages of the tunable elements (such as PIN diodes or variable capacitor arrays) to construct an initial bias grid and cover the entire bias range on this grid.

[0057]

[0058]

[0059]

[0060] In the formula, represents the set of preset frequency points, f M represents the M - th preset frequency point, M represents the total number of preset frequency points, represents the initial bias voltage vector of the i - th preset frequency point; N represents the number of tunable elements in the reconfigurable impedance matching network, corresponding to the dimension of the bias voltage vector; V min and V max respectively represent the lower limit and upper limit of the bias voltage of each tunable element, △v represents the voltage step; L bias represents the total number of segments that divide the voltage range [V min ,V max equally, which is used to construct a discrete set of candidate voltage values.

[0061] It should be noted that the set of preset frequency points can cover multiple sampling frequency points with the dual characteristics of low - frequency penetration and high - frequency resolution, and the value of M can be set to 4 or more to extend to more frequency points. In addition, [V min ,V max depends on the specific device specifications. For example, the forward bias of a PIN diode can be selected from 0 - 20 V, and the grid length L bias can be set to 5 - 10 to balance the search granularity and measurement cost. Here, through a comprehensive initial bias voltage vector coverage, it is ensured that there is a feasible starting bias at each key frequency point.

[0062] In step S320, for each preset frequency point, a two - stage combined optimization is performed based on the defect - free circuit board to obtain the corresponding optimal bias voltage.

[0063] More specifically, the cost function is defined as:

[0064] J i (b) = w1|Γ(f i ; b)| 2 + w2(VSWR(f i ; b) - 1) 2 , Equation (4)

[0065]

[0066] where J i (b) represents the comprehensive cost function calculated for the bias voltage vector b at the i-th preset frequency point f i ; w1 and w2 respectively represent the weight coefficient of the reflection coefficient magnitude term and the weight coefficient of the voltage standing wave ratio deviation term, and Γ(f i ; b) represents the complex reflection coefficient measured at the test probe when the frequency is f i and the bias voltage vector b is applied, |Γ| represents the magnitude of the reflection coefficient, and VSWR(f i ; b) represents the voltage standing wave ratio measured at the test probe when the frequency is f i and the bias voltage vector b is applied.

[0067] Here, by designing the comprehensive cost function, two major objectives of "minimizing the reflection amplitude" and "flattening the input impedance" are comprehensively considered. On the one hand, a small amplitude means that the matching network can couple more RF energy into the PCB, improving the final signal strength; on the other hand, the voltage standing wave ratio being as close to 1 as possible means that the input impedance is smooth and the mismatch is minimized within a certain bandwidth, which is crucial for the stability of subsequent multi-band measurements. By weighting the two with w1 and w2, the matching optimization is transformed into a single-objective numerical minimization problem. It should be understood that w1 and w2 can be preset, for example, set after comparing the effects of pure minimum reflection and the flattest voltage standing wave on the detection sensitivity and imaging quality in offline experiments, and can also be treated equally (each accounting for 50%), or adjusted appropriately according to the PCB material and test objectives.

[0068] In the first stage, according to the Gaussian process surrogate model to fit the cost function, use the initial bias voltage vector to initialize the training set, perform bias voltage sampling iteration with the EI (Expected Improvement) function, and solve the approximate optimal bias matrix through Bayesian optimization.

[0069] Exemplarily, the EI function is expressed by the following formula:[[]]

[0070]

[0071] where EI(b) is the acquisition function used to select the next bias voltage vector in Bayesian optimization, and is used to measure the expected cost improvement on the candidate b; is the expectation operator, representing the expectation of the improved value under the Gaussian process surrogate model; J i,min represents the minimum cost value observed in the current training set.

[0072] For the t-th iteration, perform the following operations:

[0073] Maximize the EI function value from the current Gaussian process surrogate model to select the bias voltage vector b (t) ,

[0074] Inject the frequency point frequency f through a vector network analyzer i , and measure the complex reflection coefficient and voltage standing wave ratio under the bias voltage vector b (t) to iteratively calculate the corresponding J i (b (t) ),

[0075] Add (b (t) , J i (b (t) )) to the training set to update the Gaussian process surrogate model;

[0076] Repeat the iteration T1 times to obtain the approximate optimal bias voltage vector

[0077] Here, in the global search of the first stage, by using Bayesian Optimization (BO) to efficiently explore the bias space, a Gaussian Process surrogate model is established for the cost function. Under the condition of ensuring a limited number of measurements, the "exploration" and "exploitation" are balanced through the acquisition function (Expected Improvement, EI) to quickly find the low-value area of the cost function. Thus, compared with the grid full scan, the BO algorithm can generally lock the candidate optimal area within 15 iterations (i.e., T1 can take the value of 15) of measurement, greatly improving the efficiency. In addition, the surrogate model can also utilize historical information in subsequent iterations to form a comprehensive understanding of the bias space and reduce repeated measurements.

[0078] In the second stage, the central difference method is used to solve the approximate gradient of each bias component in the approximate optimal bias voltage vector.

[0079] It should be noted that the candidate biases obtained through the BO iteration in the first stage are often close to the optimal within the global range, but local fine-tuning is still required to obtain a more accurate extreme value. Here, in the second stage, through the central difference numerical gradient estimation and combined with the gradient descent iteration, the numerical accuracy can be improved with fewer additional measurement times.

[0080]

[0081] In the formula, represents the partial derivative of the cost function with respect to the j-th bias component b in j , γ represents the small voltage perturbation used for numerical differentiation; e j is the j-th unit vector in the N-dimensional space, indicating that only the bias component b j is perturbed;

[0082] The approximate optimal bias voltage vector is iteratively updated according to the gradient descent step size:

[0083]

[0084] In the formula, b (t) represents the bias voltage vector in the t-th gradient iteration, η represents the gradient descent step size, represents the gradient vector used to guide the update direction;

[0085] If two consecutive iterations satisfy |J i (b (t+1) ) - J i (b (t) )| < δ, then let where δ represents the convergence threshold, represents the optimal bias voltage vector at the i-th frequency point.

[0086] Here, in the second stage, by using central difference to slightly increase or decrease the voltage of each component bias, the difference in the measured cost function is used to approximate the partial derivative, and the numerical minimization error of the cost function can be further reduced to 10 -4 orders of magnitude by local fine-tuning, improving the matching quality. In addition, the blindness of global search is avoided through the gradient strategy, reducing the influence of jitter and measurement noise.

[0087] The optimal bias voltage vectors of each frequency point are successively loaded into the matching network, and the voltage standing wave ratio under the action of the corresponding frequency point is measured respectively. If there are frequency points in the measured voltage standing wave ratios that exceed the preset voltage standing wave ratio threshold, it is confirmed that this frequency point does not meet the flatness requirement and the second stage of this frequency point is rolled back for local fine-tuning.

[0088] If the voltage standing wave ratios of all measured frequency points do not exceed the preset voltage standing wave ratio threshold, the optimal bias voltages corresponding to each frequency point are output.

[0089] It should be noted that the optimal bias at a single frequency does not necessarily guarantee smooth matching across frequency bands. Therefore, it is necessary to perform an overall verification on the matching status of all frequency points. By separately loading the optimal bias of each frequency point and measuring the standing wave ratio, combined with the fine spectrum scanning of adjacent frequency bands, it can be ensured that the matching performance across the entire bandwidth meets the preset indicators.

[0090] Exemplarily, the standing wave ratio threshold is set to 1.6, and if it exceeds this value, it is considered uneven; detailed measurements are carried out at intervals of 0.02 GHz at the frequency band boundaries of ±0.1 GHz, and potential spikes are captured through fine spectrum scanning; if a problem is found, only fine-tuning needs to be re-executed for this frequency point or local interval, and only local rollback is required to avoid overall re-running, thereby ensuring the reliability of the entire frequency band and realizing that there will be no information loss or artifacts during multi-band reflection measurement.

[0091] In step S330, according to each preset frequency point and the corresponding optimal bias voltage, a frequency band bias voltage relationship table is generated.

[0092] Here, after completing the optimal bias calibration and verification of all frequency points, these results are stored in a structured table format to form a frequency band bias voltage relationship table, for example, stored in the EEPROM of the MCU in the form of JSON, binary index, or simple array. During online detection, only by quickly indexing the bias vector corresponding to the frequency point, the matching network can be immediately configured. For example, the MCU reads the bias corresponding to the frequency point, drives the DAC and amplifier circuits and checks for calibration, thereby eliminating the need for re-calibration and greatly shortening the detection preparation time.

[0093] In production line applications, for the same PCB model, only one offline calibration is required using a healthy board of the corresponding model, and it can be used for online detection of hundreds or thousands of boards. In addition, loading the bias and driving the matching network only takes hundreds of microseconds to several milliseconds, meeting the requirements of the production line beat.

[0094] Regarding the reconstruction details of the three-dimensional scattering image in step S130, in some examples of the embodiments of the present application, during the multi-frequency grid scanning process, the complex reflection coefficients measured by the probe at each frequency point and each spatial position are samples of the internal scattering field of the PCB. In order to organize these discrete samples into a form suitable for mathematical processing, in the order of "frequency point first, position second", the reflection values at each frequency point L samp for M spatial positions are arranged into a vector y with a length of M·L samp .

[0095] Specifically, the complex reflection coefficient Γ(x i , y k , y k ), f k , y k , f i ) measured by the test probe at each frequency point f samp and at the k-th spatial sampling point (x samp ) is arranged according to the measurement sequence number m = (i - 1)L

[0096] Here, the probe moves along a pre-planned grid path on the PCB surface. At each grid point (x k , y k ), the system automatically switches to the current frequency point and records and caches a complex reflection coefficient once. Through a strict one-to-one mapping, it is ensured that the m=(i - 1)L samp +k-th term in the vector y exactly corresponds to the frequency point f i and the position (x k , y k ). The reflection coefficient is stored in complex form (amplitude and phase each occupy floating-point numbers), and double-precision floating-point can be used to meet the numerical stability of high-frequency phase unwrapping. At the same time, the MCU synchronously controls bias switching, probe positioning, and VNA measurement to ensure that the time sequence between all elements in y is accurately recorded.

[0097] Then, the interior of the circuit board is discretized into U voxels. Let the center coordinates of the q-th voxel be r q , and the position of the test probe is to construct the measurement matrix Φ.

[0098] It should be noted that the measurement matrix Φ is used to describe the physical mapping relationship of "internal scattered field → external measurement" - it is a bridge between the three-dimensional voxel space and the measurement vector space. Under the near-field metasurface probe coupling, each voxel will produce a certain amount of scattering contribution to each measurement, and this contribution can be regarded as the product of the voxel scattering intensity and a coupling coefficient. Arranging the coupling coefficients of all voxels and all measurement points into the matrix Φ can accurately express the entire measurement process in a linear algebra model.

[0099] Specifically, the elements in the measurement matrix are expressed by the following formula:

[0100]

[0101] In the formula, Φ m,q is the element in the m-th row and q-th column of the measurement matrix Φ, representing the linear coupling coefficient of the q-th voxel to the m-th measurement; The electromagnetic Green's function of the q-th voxel from the voxel center r i to the probe position q at the frequency point f ; E inc (f i , r q ) represents the incident field intensity excited by the test probe at the frequency point f i towards the voxel r q , and △V represents the volume of each voxel.

[0102] Regarding the description of Equation (9), according to the dielectric properties and multi-layer structure of the PCB, the Green's function can be pre-calculated using the analytical theory or numerical methods of layered media and stored as a look-up table. This function includes the amplitude and phase changes brought about by the refraction, reflection, and absorption of electromagnetic waves at different dielectric interfaces. In addition, the incident field E inc considers the probe radiation pattern and near-field effects, and can be described using a near-field antenna model or pre-calibrated electric field distribution data to ensure that the product of the Green's function and the incident field can accurately represent the primary voxel excitation. The voxel volume △V can be set according to the spatial resolution or the three-dimensional grid size to maintain the physical consistency of the scattering integral.

[0103] By ensuring the Green's function and the incident field model, Φ is highly consistent with the coupling relationship in the real PCB environment, avoiding the reconstruction deviation caused by the "black box" approximation. Moreover, high-quality Φ enables subsequent optimization to correctly distinguish the small differences between voxels, improving the resolution and positioning accuracy of three-dimensional imaging.

[0104] Furthermore, let x = Dα, where D is a multi-frequency sparse dictionary obtained by training multi-frequency scattering samples collected offline on healthy and defective boards using the K-SVD algorithm. Each column is a dictionary atom to sparsely represent the scattering characteristics of various defective voxels; α is the sparse representation coefficient of the three-dimensional scattering field under the dictionary D, and only a few elements are non-zero, corresponding to the sparse distribution of defective voxels.

[0105] It should be noted that the internal defect distribution of the PCB is often highly sparse. Most voxels are homogeneous dielectric regions, and only a few voxels point to cracks, bubbles, or delamination interfaces. By learning a set of "atoms" from a large number of templates - these atoms represent the spatial and spectral patterns of typical defect scattering, any complex set of defective voxels can be reconstructed with extremely few sparse coefficients. Through the above compressive sensing recovery method, even if the number of measurement points is much smaller than the number of voxels, the defect field can be stably reconstructed. Thus, with the multi-frequency sparse dictionary, the sparse parameters are only dozens of dimensions, while the original number of voxels may be tens of thousands, greatly reducing the dimension of the optimization problem. In addition, the multi-frequency sparse dictionary contains various defect modes and can automatically adapt to unknown forms of cracks, bubbles, or delamination.

[0106] Regarding the construction details of the multi-frequency sparse dictionary, in some examples of the embodiments of the present application, first, it is necessary to collect healthy board samples and defective board samples simultaneously. Specifically, the healthy board samples can be the normal scattering characteristics collected through healthy PCBs, and the defective board samples can be the scattering characteristics collected through defective circuit boards with various typical defects (such as micro-via cracks, interlayer delamination, dielectric voids, etc.).

[0107] Specifically, on each sample board, a refined grid scan is performed one by one on the preset frequency point set using the optimized matching network and probe grid path. The horizontal and vertical step sizes are set according to the PCB detail requirements (e.g., 0.5 mm or finer). At each grid point (x k , y k ), the reflection coefficient Γ(x k , y k , f i ) is collected. For healthy boards, only "defect blank" confirmation is required; for defective boards, the internal defect positions and morphologies of each board are three-dimensionally labeled using a micro X-ray or OCM (optical confocal microscope) to obtain voxel-level ground truth corresponding one-to-one to the scattering measurement.

[0108] Then, training is performed using the above training samples with the K-SVD dictionary, and the relevant details of K-SVD dictionary training in the current related technologies can be referred to.

[0109] In some examples of the embodiments of the present application, cross-frequency joint training can be used. Specifically, the first K principal vectors are taken from the sample matrix using data principal component analysis (PCA) and are alternately iterated. Exemplarily, in each alternate iteration, for each training vector x (s) , the orthogonal matching pursuit (OMP) algorithm is used to solve for the sparse coefficients under the current dictionary D (t) . Then, for each dictionary atom d k (the k-th column), the set of samples that used this atom in the sparse representation is extracted, the residual matrix is calculated and singular value decomposition (SVD) is performed. All frequency point samples are concatenated and a large dictionary D is trained at once to capture cross-frequency coupled atoms. Dictionaries D i are trained for each frequency point respectively, and then they are combined into a joint dictionary through block diagonal or principal component. When the change in the Frobenius norm before and after dictionary update is lower than the threshold, or the number of iterations reaches the upper limit (e.g., 100 times), the training is terminated and the final dictionary D is output.

[0110] Thus, the sparse dictionary obtained through offline training can accurately reconstruct the multi-frequency scattering characteristics of any defective voxel with a small number of atoms, greatly reducing the dimension and computational amount of online sparse solution. In addition, through cross-frequency joint training, the dictionary atoms can simultaneously encode low-frequency penetration and high-frequency resolution characteristics, improving the expression ability for mixed defects (such as via cracks accompanied by dielectric voids). Thus, the multi-frequency sparse dictionary constructed in this way can not only accurately reproduce the scattering characteristics of various defective voxels, but also achieve efficient reconstruction with a small number of online measurements.

[0111] The optimal sparse coefficient α * is obtained by solving the compressive sensing optimization objective function to reconstruct the three-dimensional scattering image inside the circuit board

[0112] Specifically, the optimization objective function of compressive sensing is expressed by the following formula:

[0113]

[0114] In the formula, represents the l2 least squares term; μ‖α‖1 represents the l1 sparse regularization term, and the weight μ>0 controls the sparsity degree; represents the total variation regularization term, is the gradient operator calculated for the three-dimensional reconstruction voxel vector x, and the sum of its moduli is used to suppress noise blocks and artifacts in the reconstruction, and λ TV is the control weight; represents the spectral smoothing regularization term, W is the spectral operator for smoothing the reconstruction result in the frequency dimension, and λ FS >0 controls the spectral consistency to ensure the continuity of the reconstructed voxels at different frequency points in the frequency domain.

[0115] Regarding the explanation of formula (10), μ is selected according to the measurement SNR (slightly increase μ at low SNR), and λ TV can be adjusted according to the spatial resolution requirement, and λ FS can be finely adjusted according to the spectral smoothness requirement.

[0116] It should be noted that the core of compressive sensing lies in "a small number of measurements + sparse prior → accurate recovery", but a single l1 constraint cannot suppress spatial artifacts and is also difficult to ensure multi-frequency consistency. Therefore, an l2 data fitting term is introduced into the objective function to ensure that the reconstructed value is consistent with the true measurement; an l1 sparse term is introduced to strengthen the prior sparsity; a total variation regularization term is introduced to suppress spatial noise blocks and enhance the continuity of the reconstructed body; a spectral smoothing regularization term is introduced to ensure that the same voxel is smooth at different frequency points and avoid contradictions between frequency points.

[0117] Here, the optimization problem is split into four parts: data fitting, sparse threshold, TV (Total Variation) sub-problem, and spectral sub-problem. The Lagrange multipliers are alternately solved and updated, and the iteration continues until the error converges. Thus, after eliminating high-frequency noise blocks through TV regularization, the reconstruction error of defective voxels is more concentrated and the anomaly detection is more accurate; through spectral smoothing regularization, the reconstructed voxels form a consistent scattering intensity curve in the entire frequency band, which is convenient for subsequent multi-frequency fusion and model determination. In addition, data fitting and threshold operation can be fully parallelized on the GPU to accelerate matrix multiplication and element-level processing, meeting the time efficiency requirements of on-line inspection on the production line.

[0118] Regarding the details of screening abnormal circuit physical layers in step S140, in some examples of the embodiments of the present application, the three-dimensional scattering images obtained by on-line reconstruction and arranged according to the voxel index q = 1,..., U Encoder network of the input variational autoencoder:

[0119]

[0120] where Q φ (·) represents the encoder distribution, z represents the latent variable vector, μ φ and respectively represent the latent variable mean vector and the latent variable variance vector, and the latent variable prior is set to a standard normal

[0121] It should be noted that the original three-dimensional scattering image has many dimensions and contains complex noise, hardware artifacts, and process differences. It is almost impossible to measure "anomaly" directly in the high-dimensional space. The latent distribution (parameterized as the mean and variance vectors) learned by the encoder condenses the main variation patterns of normal data, removes most of the noise and redundant features, making the subsequent calculation of the probability density and anomaly measurement feasible.

[0122] More specifically, in an unsupervised anomaly detection framework, a "normal data model" (i.e., only using healthy plate data for unsupervised training) is used to perform probability evaluation on the three-dimensional scattering field obtained by online reconstruction. Specifically, VAE (variational autoencoder) is used to map the high-dimensional input to a low-dimensional latent space distribution through an encoder network to realize the expression of the probability structure of the "normal scattering image".

[0123] Assuming that the output likelihood of the decoder, that is, each voxel is independent given the latent variable, then it satisfies:

[0124]

[0125] where represents the decoder conditional likelihood, defined by the network parameter set θ, and is used to evaluate the probability of the reconstructed value given the latent variable z.

[0126] Define the negative log-likelihood of each voxel q as its reconstruction negative log-marginal likelihood:

[0127]

[0128] where NLL q represents the negative log-likelihood value of the q-th voxel, represents the mathematical expectation under the encoder distribution KL(·) is the KL divergence between the encoder output distribution and the standard normal prior, and its value is evenly distributed to all voxels to ensure the consistency of NLL aggregation.

[0129] It should be noted that the negative value of ELBO (Evidence Lower BOund), that is, the negative log-likelihood (NLL), intuitively measures the "degree of unexpectedness" of a reconstructed image or a local part of an image under a given "normal data model". To locate anomalies, the overall NLL is decomposed into each voxel, which is achieved by assuming conditional independence between voxels. Although it is an approximate assumption in this embodiment, it is fine enough in the multi-frequency scattering field because real defects are often confined to a few voxels, and the NLL (Negative Log-Likelihood) peak under the assumption of independence can still well highlight the abnormal area.

[0130] The NLL of all voxels q is recombined into a three-dimensional NLL volume map {NLL(q) | q = 1…U} of the same size as ...

[0131] According to the physical layer index ζ(q) ∈ {1,…,H} corresponding to each voxel q in the PCB design, the voxel set is divided into layer sets Ω ζ = {q | ζ(q) = ζ}, where Ω ζ represents the voxel index set of the ζ-th layer; ζ(q) is the physical layer mapping function, which means specifying the voxel index q to the corresponding physical layer number; H represents the total number of physical layers of the circuit board.

[0132] Take the maximum of the negative log-likelihood values of all voxels in the ζ-th layer:

[0133]

[0134] In the formula, S ζ represents the layer-level anomaly score of the ζ-th layer.

[0135] It should be noted that in PCB detection, the most dangerous defects are often micro-cracks or blind buried hole delaminations with extremely small sizes but great impacts. Such point-like anomalies may only occupy one or two voxels, and the in-layer mean value will dilute this tiny peak, while the maximum value aggregation ensures that any high peak can trigger an alarm, thus avoiding missed detections.

[0136] Here, by using layer-level maximum value aggregation to capture the peak NLL, rather than averaging or energy statistics, it is ensured that the tiny anomalies of a small number of voxels can be located in the first time, greatly improving the detection rate of micro-vias cracks (width < 50μm) and tiny interlayer delaminations (area < 0.1mm 2 ). And these are often ignored in traditional single-frequency TDR or X-ray detections.

[0137] Compare S ζ with the layer anomaly threshold T statistically obtained offline on the healthy board for the ζ-th layerζ Compare and select

[0138] ζ * ={ζ|S ζ >T ζ}} , Equation (15)

[0139] Output the set ζ of layer indices corresponding to the detected abnormal circuit physical layer * .

[0140] Here, in order to distinguish between "high values caused by occasional measurement noise" and "high values caused by real defects", we have pre-offline conducted a large number of NLL statistics on healthy boards to obtain the maximum NLL distribution intervals of each layer in the normal state, so as to set the safety threshold. During online operation, as long as the peak value exceeds this threshold, it is determined that the layer is abnormal. Thus, combined with the statistical threshold of the healthy board, occasional noise spikes are removed, and then the regions are clustered through hierarchical alarms to avoid misjudgment of single-point artifacts.

[0141] Through the embodiments of the present application, by fusing the voxel-level NLL and hierarchical aggregation dual outputs, it is possible to accurately locate the position of a single abnormal voxel and quickly locate the corresponding circuit physical layer.

[0142] Figure 4 Shows a flowchart of an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of the present application.

[0143] As Figure 4 shown, in step S410, according to the frequency band bias voltage relationship table, determine the corresponding test bias voltages of the reconfigurable impedance matching network at multiple test frequency points.

[0144] In step S420, for each test frequency point, apply a test bias voltage matching the test frequency point to each adjustable element to achieve impedance matching between the reconfigurable impedance matching network at the corresponding test frequency point and the circuit board under test, and inject a radio frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe.

[0145] In step S430, analyze the reflection coefficients corresponding to each test frequency point based on the multi-frequency sparse dictionary and the compressive sensing algorithm to reconstruct the three-dimensional scattering image inside the circuit board.

[0146] In step S440, calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtain the hierarchical anomaly scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0147] Regarding the implementation details of steps S410 - S440, reference can be made to the description in the above text in combination with other embodiments, and details will not be elaborated here.

[0148] In step S450, for each abnormal circuit physical layer, at least one abnormal voxel point whose negative log-likelihood value exceeds the layer abnormal threshold is extracted from the abnormal circuit physical layer according to a preset voxel sliding window, and the corresponding local abnormal voxel clustering is obtained through pixel clustering.

[0149] It should be noted that internal defects of circuit boards usually exhibit characteristics of "local aggregation" or "connected components". For example, micro vias cracks often aggregate in a certain area and are manifested as continuous small high-abnormality points; while blind buried via delamination may present continuous multi-layer high-abnormality points in the vertical structure direction. Therefore, relying solely on a single voxel point for defect judgment will lack spatial coherence and structural integrity.

[0150] Here, through a preset three-dimensional sliding window, scanning is performed within the abnormal layer, and abnormal voxel points with NLL exceeding the threshold T ζ are extracted first, avoiding directly clustering all voxels in the entire layer, and using the spatial adjacency relationship between voxels, the above abnormal voxels are divided into several local clusters, and each cluster corresponds to a possible defect area.

[0151] Specifically, by moving the sliding window voxel by voxel within the range of the abnormal circuit physical layer, a local voxel subset is extracted each time, and it is statistically determined whether there is a region where the negative log-likelihood value continuously exceeds the preset layer abnormal threshold. Once it is found that the negative log-likelihood value of at least one voxel is greater than the set threshold, it is considered that there is a potential abnormal response area in the sliding window.

[0152] Thus, by introducing a sliding window local anomaly detection and voxel clustering mechanism, the spatial positioning and separation of internal microstructural defects of circuit boards are realized, supporting hierarchical tracking and comparison of defect areas, and contributing to the realization of multi-layer defect penetrability analysis.

[0153] In step S460, according to the local voxel clustering corresponding to each abnormal circuit physical layer, the circuit board defect type for the circuit board to be tested is output, and the circuit board defect type includes at least one of the following: micro via crack, interlayer delamination, blind buried via delamination, or dielectric layer void.

[0154] In some embodiments, rule pattern matching or a trained classification model (such as SVM, decision tree, or lightweight neural network) can be introduced to perform multi-class classification judgment by fusing multiple feature dimensions. More specifically, the feature dimensions of the model can be diverse and can be formulated according to the structural hierarchical position and voxel clustering morphology.

[0155] Exemplarily, in terms of the structural hierarchical position, different types of defects tend to concentrate on specific circuit structure layers. Specifically, micro-via cracks concentrate near the metal vias that penetrate multiple upper and lower layers, generally spanning signal layers and ground layers. Interlayer delamination and dielectric layer voids mostly occur in the dielectric layer, usually without metal conductors, with weak reflected response signals but strong structural continuity. Blind buried via peeling concentrates at the junction of the wiring layer and the blind via, showing a flaky distribution along the Z-axis direction and usually being limited between two layers.

[0156] On the other hand, the voxel clustering morphology can reflect the uniqueness of the spatial morphology of different defects. For example, crack-like defects often appear as linear or small dot-like bands with high connectivity; peeling-like defects are flaky, large in volume but thin in thickness; void-like defects are blocky or irregular in shape, dense in the middle and with blurred boundaries. Thus, specific classification of circuit board defects can be carried out through the morphological clustering morphology.

[0157] Through the embodiments of the present application, by using a sliding window + clustering, potential abnormal voxels can be spontaneously "clustered" in three-dimensional space, greatly improving the defect location accuracy, making the crack clusters and void clusters clearly separated, and enabling automatic switching of the determination logic for corresponding defects according to the geometric shape of the clusters.

[0158] Figure 5 The schematic diagram of the effect of an example of the circuit board defect type according to the embodiments of the present application is shown.

[0159] As Figure 5 shown, micro-via cracks refer to visible cross-crack lines at the edge of multi-layer connected vias. Specifically, micro-vias refer to blind vias or buried vias with a diameter usually between 50μm - 150μm that only penetrate several layers in a high-density interconnect (HDI) board. Due to their extremely thin wall copper, thermal cycling, and mechanical stress concentration, micro-cracks along the copper foil - resin interface are extremely likely to occur during reflow soldering or thermal cycling tests. The width of these cracks is often less than 50μm, the length is between 100μm - 1mm, and the distribution is irregular, which not only affects the continuity of the conductance path in the hole but also causes local impedance mutation or signal reflection in high-frequency signal transmission. Traditional optical and X-ray detections are difficult to discover such cracks online. In the embodiments of the present invention, through high-frequency (≥5GHz) near-field scattering imaging and depth anomaly detection, highly sensitive positioning of sub-50μm cracks can be achieved.

[0160] Interlayer delamination refers to the obvious peeling voids appearing between the intermediate layers. Specifically, in the lamination process of a multi-layer PCB, it is formed by laminating multiple copper foils with prepreg or epoxy glass cloth. If the lamination temperature, pressure, curing curve, or material ratio is improper, or the internal stress of the board is too large, the bonding interface between two layers will be separated - namely "inner layer delamination". This defect cannot be directly seen with the naked eye and often accompanies a sudden increase in the dielectric constant and dielectric loss, affecting the transmission of high-frequency signals.

[0161] Blind / buried via delamination refers to the appearance of a flaky delamination area at the top or bottom of a blind via (only penetrating part of the layers). Blind vias or buried vias are via structures that only penetrate part of the layers, and good bonding is also required between the copper walls around them and the substrate. When in the lamination or subsequent thermal cycle, due to the mismatch of the coefficient of thermal expansion and the concentration of high and low temperature stresses, and tiny cracks appear at the resin interface between the copper wall and the adjacent layer, "blind / buried layer delamination" will occur. This defect will cause electrical open circuits or impedance mutations at the via wall and is extremely difficult to detect quickly online by traditional AOI or X-ray.

[0162] Dielectric layer voids refer to the visible circular or irregular voids in the middle of a single dielectric layer. It is a common material defect in the manufacturing of multi-layer PCBs, which means that during the lamination process, the prepreg or epoxy glass cloth layer fails to be fully infiltrated, cured insufficiently, or the internal volatile gases are not discharged in time, resulting in cavities with a diameter > 100μm and irregular shapes in the internal resin layer of the substrate. These voids locally reduce the dielectric constant and increase the dielectric loss, and are likely to cause phase distortion and signal attenuation in high-frequency signals. Since the voids are covered by the copper layer and are hidden in location, both AOI and flying probe tests are difficult to detect. Through the compressive sensing imaging combining low-frequency penetration (0.7 - 2GHz) and high-frequency resolution (5 - 9GHz) in the embodiments of the present application, the internal void distribution can be captured at the three-dimensional voxel level, achieving high-precision positioning within 0.5mm.

[0163] In some examples of the embodiments of the present application, the clustering morphological features corresponding to each local voxel clustering are extracted, and the clustering morphological features include at least one of the following: the number of voxels, the axial range, the volume-surface area ratio, and the shape factor. Furthermore, each clustering morphological feature is matched according to a predefined defect type feature pattern library, so as to output the circuit board defect type for the circuit board to be tested.

[0164] Here, a set of geometric morphological features is calculated for each cluster, including the number of voxels used to highlight the defect size, the axial range used to reflect the extension of the cluster in the x, y, and z directions, the volume-surface area ratio used to distinguish spherical voids from thin sheet cracks, and the shape factor used to describe the elongated or flattened distribution. Finally, the cluster feature vector is matched with the feature patterns of predefined various defects to obtain the final identification of the circuit board defect type.

[0165] Exemplarily, for micro via cracks, a large length / width ratio, a small axial thickness, and the cluster center close to the via position are required; for interlayer delamination, a large width / thickness ratio and a large area distribution of the cluster along the layer plane are required; for blind / buried via peeling, the cluster is required to be circular or semi-circular and geometrically coincident with the blind / buried via position; for dielectric layer voids, a high volume-surface area ratio and a near-spherical distribution are required. In addition, a hard threshold rule or a lightweight classification model (such as a decision tree) can be used to determine the best matching type. Finally, all clusters and their matching results are summarized, and the most representative defect type or multiple parallel defects are output, marking the corresponding abnormal layer and approximate spatial position, so that engineers can clearly see the shape and position of the defects, facilitating targeted maintenance of the PCB production line.

[0166] In some embodiments, for each cluster the feature vector f is calculated separately n :

[0167] 1. Number of voxels N n :

[0168]

[0169] 2. Axial range:

[0170] The maximum-minimum difference along the x, y, and z directions:

[0171]

[0172] Similarly, Δy and Δz are calculated.

[0173] 3. Principal component analysis (PCA)

[0174] For the coordinate matrix of the cluster calculate the covariance and obtain the eigenvalues λ1 ≥ λ2 ≥ λ3, the length width thickness

[0175] 4. Shape factor

[0176] Elongation: L / W;

[0177] Flatness: W / T;

[0178] Sphericity:

[0179] 5. Volume–surface area ratio

[0180] Voxel volume: V n = N n ×ΔV;

[0181] Surface area approximation: estimated from the number of three-dimensional boundary voxels, or convex hull surface area;

[0182] Ratio: V n / S n , differentiating spheres from flakes.

[0183] Based on the above features f n Match with the defect type feature pattern library to identify and locate the corresponding circuit board defect type.

[0184] Table 1. Defect type feature pattern library

[0185]

[0186]

[0187] In the embodiments of the present application, by performing rule matching between the clustering morphological features and the defect type feature pattern library, the type determination of a single cluster can be efficiently completed, and at the same time, the detection of point defects (cracks, voids) and surface defects (interlayer delamination) is supported, and the determination logic can be automatically switched according to the geometric shape of the cluster without manual intervention.

[0188] It should be noted that for the foregoing method embodiments, for simplicity of description, they are all expressed as a combination of a series of actions. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application. In the above embodiments, each embodiment is described with emphasis. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0189] Figure 6 Shows a structural block diagram of an example of a circuit board defect detection system based on multi-band impedance matching according to an embodiment of the present application.

[0190] As Figure 6As shown in the figure, the circuit board defect detection system 600 based on multi-band impedance matching includes a reconstruction bias determination unit 610, a bias impedance matching unit 620, a three-dimensional scattering reconstruction unit 630, and an abnormal layer identification unit 640.

[0191] The reconstruction bias determination unit 610 is configured to determine the corresponding test bias voltages of the reconfigurable impedance matching network at multiple test frequency points according to the frequency band bias voltage relationship table; the reconfigurable impedance matching network includes a plurality of adjustable elements and is coupled to the test probe, and the frequency band bias voltage relationship table includes the relationships between a plurality of pre-calibrated frequency points and bias voltages for a circuit board without defects.

[0192] The bias impedance matching unit 620 is configured to, for each of the test frequency points, apply a test bias voltage matching the test frequency point to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network at the corresponding test frequency point and the circuit board under test, and inject a radio frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe.

[0193] The three-dimensional scattering reconstruction unit 630 is configured to analyze the reflection coefficients corresponding to each of the test frequency points based on a multi-frequency sparse dictionary and a compressive sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board.

[0194] The abnormal layer identification unit 640 is configured to calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtain the hierarchical abnormal scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0195] In some embodiments, the present application provides a non-volatile computer-readable storage medium storing one or more programs including execution instructions that can be read and executed by an electronic device (including but not limited to a computer, a server, or a network device, etc.) to perform the steps of any one of the above-mentioned circuit board defect detection methods based on multi-band impedance matching of the present application.

[0196] In some embodiments, the present application further provides a computer program product including a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the steps of any one of the above-mentioned circuit board defect detection methods based on multi-band impedance matching.

[0197] In some embodiments, the embodiments of the present application further provide an electronic device, which includes: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the steps of the circuit board defect detection method based on multi-band impedance matching.

[0198] Figure 7 FIG. is a schematic hardware structure diagram of an electronic device for executing the circuit board defect detection method based on multi-band impedance matching provided by another embodiment of the present application. As Figure 7 shown, the device includes:

[0199] One or more processors 710 and a memory 720. Figure 7 Here, one processor 710 is taken as an example.

[0200] The device for executing the circuit board defect detection method based on multi-band impedance matching may further include: an input device 730 and an output device 740.

[0201] The processor 710, the memory 720, the input device 730, and the output device 740 may be connected through a bus or other means. Figure 7 Here, the connection through a bus is taken as an example.

[0202] The memory 720, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the circuit board defect detection method based on multi-band impedance matching in the embodiments of the present application. The processor 710 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 720, that is, implements the circuit board defect detection method based on multi-band impedance matching in the above method embodiments.

[0203] The memory 720 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 720 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 720 may optionally include a memory remotely provided relative to the processor 710, and these remote memories may be connected to the electronic device through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0204] The input device 730 can receive input digital or character information and generate signals related to user settings and function control of the electronic device. The output device 740 may include a display device such as a display screen.

[0205] The one or more modules are stored in the memory 720 and, when executed by the one or more processors 710, perform the method for detecting circuit board defects based on multi-band impedance matching in any of the above method embodiments.

[0206] The above product can execute the method provided in the embodiments of the present application and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided in the embodiments of the present application.

[0207] The electronic device in the embodiments of the present application exists in various forms, including but not limited to:

[0208] (1) Mobile communication devices: Such devices are characterized by having mobile communication functions and mainly aim to provide voice and data communication. Such terminals include: smart phones, multimedia phones, functional phones, and low-end phones, etc.

[0209] (2) Ultra-mobile personal computer devices: Such devices belong to the category of personal computers, have computing and processing functions, and generally also have the characteristic of mobile Internet access. Such terminals include: PDA, MID, and UMPC devices, etc.

[0210] (3) Portable entertainment devices: Such devices can display and play multimedia content. Such devices include: audio and video players, handheld game consoles, e-books, and smart toys and portable vehicle navigation devices.

[0211] (4) Other airborne electronic devices with data interaction functions, such as in-vehicle device installed on a vehicle.

[0212] The device embodiments described above are merely illustrative, where the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution in this embodiment.

[0213] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution or the part that contributes to the related technology can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0214] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board defect detection method based on multi - band impedance matching, comprising: Determine the corresponding test bias voltages of the reconfigurable impedance matching network at multiple test frequencies according to the frequency - band bias voltage relation table; The reconfigurable impedance matching network includes multiple adjustable elements and is coupled to the test probe, and the frequency - band bias voltage relation table includes the relationships between multiple frequencies and bias voltages pre - calibrated for a defect - free circuit board; For each of the test frequencies, apply a test bias voltage matching the test frequency to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network at the corresponding test frequency and the circuit board under test, and inject a radio - frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe; Analyze the reflection coefficients corresponding to each of the test frequencies based on a multi - frequency sparse dictionary and a compressive sensing algorithm to reconstruct the three - dimensional scattering image inside the circuit board; Calculate the negative log - likelihood distribution corresponding to the three - dimensional scattering image, and respectively obtain the hierarchical anomaly scores of the corresponding circuit physical layers by combining the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

2. The method according to claim 1, wherein After screening at least one abnormal circuit physical layer, the method further includes: For each of the abnormal circuit physical layers, extract at least one abnormal voxel point whose negative log - likelihood value exceeds the layer anomaly threshold from the abnormal circuit physical layer according to a preset voxel sliding window, and obtain the corresponding local abnormal voxel clustering through pixel clustering; According to the local voxel clustering corresponding to each of the abnormal circuit physical layers, output the circuit board defect types for the circuit board under test, and the circuit board defect types include at least one of the following: micro - via crack, inter - layer delamination, blind - buried via peeling, or dielectric layer void.

3. The method according to claim 1, wherein Regarding the generation of the frequency - band bias voltage relation table, it includes: Obtain a preset frequency set and an initial bias voltage vector: In the formula, represents a set of preset frequency points, and f M represents the Mth preset frequency point, where M represents the total number of preset frequency points. represents the initial bias voltage vector of the ith preset frequency point; N represents the number of adjustable elements in the reconfigurable impedance matching network, corresponding to the dimension of the bias voltage vector; V min and V max respectively represent the lower limit and upper limit of the bias voltage of each path of adjustable elements, and △v represents the voltage step; L bias represents the total number of segments obtained by equally dividing the voltage range [V min , V max , which is used to construct a discrete set of candidate voltage values. For each preset frequency, perform the following two - stage combined optimization on a defect - free circuit board to obtain the corresponding optimal bias voltage, specifically including: Define the cost function as: J i (b) = w1|Γ(f i ; b)| 2 + w2(VSWR(f i ; b) - 1) 2 , where J i (b) represents the comprehensive cost function calculated for the bias voltage vector b at the i-th preset frequency point f i . w1 and w2 respectively represent the weight coefficient of the reflection coefficient magnitude term and the weight coefficient of the voltage standing wave ratio deviation term. Γ(f i ; b) represents the complex reflection coefficient measured at the test probe when the frequency is f i and the bias voltage vector b is applied. |Γ| represents the magnitude of the reflection coefficient, and VSWR(f i ; b) represents the voltage standing wave ratio measured at the test probe when the frequency is f i and the bias voltage vector b is applied. In the first stage, fit the cost function according to the Gaussian process surrogate model, initialize the training set with the initial bias voltage vector, perform bias voltage sampling iteration with the EI function, and solve the approximate optimal bias matrix through Bayesian optimization; The EI function is expressed by the following formula: where \(EI(b)\) is the acquisition function used to select the next bias voltage vector in Bayesian optimization, which measures the expected cost improvement over candidate \(b\); is the expectation operator, denoting taking the expectation of the improvement value under the Gaussian process surrogate model; \(J\) i,min represents the minimum cost value observed in the current training set; For the t - th iteration, perform the following operations: Maximize the EI function value from the current Gaussian process surrogate model to select the bias voltage vector b (t) , Inject the frequency point frequency f through a vector network analyzer i and measure the complex reflection coefficient and voltage standing wave ratio at the bias voltage vector b (t) to iteratively calculate the corresponding J i (b (t) ), Add (b (t) , J i (b (t) )) to the training set to update the Gaussian process surrogate model; Iterate repeatedly T1 times to obtain an approximately optimal bias voltage vector In the second stage, use the central difference method to solve the approximate gradient of each bias component in the approximate optimal bias voltage vector; In the formula, represents the partial derivative of the cost function with respect to the j-th bias component b j in, and γ represents the small voltage perturbation amount for numerical differentiation; e j is the j-th unit vector in the N-dimensional space, indicating that only the bias component b j is perturbed; Iteratively update the approximate optimal bias voltage vector according to the gradient descent step size; where b (t) represents the bias voltage vector in the t-th gradient iteration, η represents the gradient descent step size, represents the gradient vector for guiding the update direction; If two consecutive iterations satisfy |J i (b (t+1) ) - J i (b (t) )| < δ, then let where δ represents the convergence threshold, represents the optimal bias voltage vector at the i-th frequency point; Load each optimal bias voltage vector into the matching network in sequence, and respectively measure the voltage standing - wave ratio under the action of the corresponding frequency. If there is a frequency in the measured voltage standing - wave ratios that exceeds the preset voltage standing - wave ratio threshold, confirm that this frequency does not meet the flatness requirement and roll back to the second stage of this frequency for local fine - tuning; If the voltage standing - wave ratios of all measured frequencies do not exceed the preset voltage standing - wave ratio threshold, output the optimal bias voltages corresponding to each frequency to generate the frequency - band bias voltage relation table.

4. The method according to claim 1, wherein The adjustable element is a PIN diode array. Each PIN diode can achieve a radio frequency conduction state or a cut-off state by applying a forward or reverse bias current. The PIN diode array is integrated in the main signal path or the bypass branch of the reconfigurable impedance matching network in series or parallel form. By testing the bias voltage, the conduction combination of different PIN diodes in the PIN diode array is controlled to change the equivalent inductance and / or equivalent capacitance of the corresponding branch, so as to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency points.

5. The method according to claim 3, wherein, Analyzing the reflection coefficients corresponding to each of the test frequency points based on the multi-frequency sparse dictionary and the compressive sensing algorithm to reconstruct the three-dimensional scattering image inside the circuit board, including: Measure the complex reflection coefficient Γ(x i ,y k ,f k ) at each frequency point f of the test probe k at the k-th spatial sampling point (x k ,y i ), and arrange it according to the measurement sequence number m=(i - 1)L samp +k to generate a measurement vector y; where L samp represents the total number of spatial sampling points at a single test frequency point; Discretize the interior of the circuit board into U individual voxels, and let the center coordinates of the q-th voxel be r q , the position of the test probe is Construct the measurement matrix Φ; the elements in the measurement matrix are expressed by the following formula: where, Φ m,q is the element at the m-th row and q-th column of the measurement matrix Φ, representing the linear coupling coefficient of the q-th voxel to the m-th measurement; The q-th voxel at the frequency point f i The electromagnetic Green's function from the voxel center r q to the probe position ; E inc (f i , r q ) represents the intensity of the incident field excited by the test probe at the frequency point f i towards the voxel r q ; △V represents the volume of each voxel. Let \(x = D\alpha\), where \(D\) is a multi-frequency sparse dictionary obtained by training with the K-SVD algorithm from multi-frequency scattering samples collected offline on healthy boards and defective boards. Each column is a dictionary atom, which sparsely represents the scattering characteristics of various defective voxels; \(\alpha\) is the sparse representation coefficient of the three-dimensional scattering field under the dictionary \(D\), and only a few elements are non-zero, corresponding to the sparse distribution of defective voxels. The optimal sparse coefficient α is obtained by solving the compressive sensing optimization objective function * to reconstruct the three-dimensional scattering image inside the circuit board wherein, the compressive sensing optimization objective function is expressed by the following formula: In the formula, represents the l2 least squares term; μ‖α‖1 represents the l1 sparse regularization term, and the weight μ>0 controls the sparsity level; represents the total variation regularization term, is the gradient operator calculated for the 3D reconstruction voxel vector x, and the sum of its magnitudes is used to suppress noise blocks and artifacts in the reconstruction, and λ TV is the control weight; represents the spectral smoothing regularization term, W is the spectral operator for smoothing the reconstruction result in the frequency dimension, and λ FS >0 controls the spectral consistency to ensure the continuity of the reconstructed voxels at different frequency points in the frequency domain.

6. The method according to claim 2, wherein Calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and respectively obtaining the hierarchical anomaly scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer, including: The three-dimensional scattering image obtained by online reconstruction and arranged according to the voxel index q = 1, …, U is input into the encoder network of the variational autoencoder: where Q φ (·) represents the encoder distribution, z represents the latent variable vector, μ φ and respectively represent the latent variable mean vector and the latent variable variance vector, and the latent variable prior is set to a standard normal Assuming that the output likelihood of the decoder, that is, each voxel is independent of each other under the given latent variable, then it satisfies: wherein, represents the decoder conditional likelihood, defined by the set of network parameters θ, for evaluating the probability of the reconstructed value given the latent variable z; Defining the negative log-likelihood of each voxel \(q\) as its reconstructed negative log marginal likelihood: where NLL q represents the negative log-likelihood value of the q-th voxel, represents the mathematical expectation under the encoder distribution The value of KL(·), which is the KL divergence between the encoder output distribution and the standard normal prior, is evenly distributed to all voxels to ensure the consistency of NLL aggregation; The NLL of all voxels q is reorganized into a three-dimensional NLL volume map of the same size as {NLL(q) | q = 1...U}; According to the physical layer index ζ(q) ∈ {1, …, H} corresponding to each voxel q in the PCB design, the voxel set is partitioned into layer sets Ω ζ = {q | ζ(q) = ζ}, Ω ζ represents the voxel index set of the ζ-th layer; ζ(q) is the physical layer mapping function, which means assigning the voxel index q to the corresponding physical layer number; H represents the total number of physical layers of the circuit board; Taking the maximum of the negative log-likelihood values of all voxels in the \(\zeta\)-th layer: Where S ζ represents the hierarchical anomaly score of the ζ-th layer; Compare S ζ with the layer anomaly threshold T obtained by offline statistics on the health board for the ζ layer ζ and take ζ * = {ζ | S ζ > T ζ}, Output the set ζ of layer indices corresponding to the detected abnormal circuit physical layer * .

7. The method according to claim 6, wherein, Outputting the circuit board defect type for the circuit board under test according to the clustering of local voxels corresponding to each of the abnormal circuit physical layers, including: Extracting the clustering morphological features corresponding to each local voxel clustering; the clustering morphological features include at least one of the following: the number of voxels, the axial range, the volume-surface area ratio, and the shape factor; Matching each of the clustering morphological features according to a predefined defect type feature pattern library, so as to output the circuit board defect type for the circuit board under test.

8. A circuit board defect detection system based on multi-band impedance matching, including: A reconstruction bias determination unit for determining the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequency points according to a frequency band bias voltage relationship table; the reconfigurable impedance matching network includes a plurality of adjustable elements and is coupled to a test probe, and the frequency band bias voltage relationship table includes the relationship between a plurality of pre-calibrated frequency points and bias voltages for a defect-free circuit board. A bias impedance matching unit for, for each of the test frequency points, achieving impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency point by applying a test bias voltage matching the test frequency point to each of the adjustable elements, and injecting a radio frequency signal into the circuit board under test to collect the corresponding reflection coefficient through the test probe. A three-dimensional scattering reconstruction unit for analyzing the reflection coefficients corresponding to each of the test frequency points based on a multi-frequency sparse dictionary and a compressive sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board; An abnormal layer identification unit for calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image and separately obtaining the hierarchical abnormal scores of the corresponding circuit physical layers in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

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