Vernier caliper type pulse laser ranging system and method

Abstract

The invention discloses a vernier caliper type pulse laser ranging system and method, and belongs to the technical field of laser ranging. The vernier caliper type pulse laser ranging system comprises a control and calculation unit, a pulse generation unit, a dual-channel synchronous pulse counting unit, an LD driving unit and a photoelectric detection unit; the control and calculation unit is used for sending a trigger signal, driving the pulse generation unit to generate pulses and starting the dual-channel synchronous pulse counting unit to count and time, a first pulse output by the pulse generation unit is input into the dual-channel synchronous pulse counting unit, and a second pulse is input into the LD driving unit to emit pulse laser; after being reflected by an object, the signal is received by the photoelectric detection unit and is converted into an electric pulse signal to be input into the dual-channel synchronous pulse counting unit, and the dual-channel synchronous pulse counting unit performs synchronous counting and time difference measurement on the received two paths of pulse signals and transmits data back to the control and calculation unit for distance calculation. The system and the method have the advantages of simple structure, low cost, easiness in implementation and the like while improving the ranging precision.

Description

Technical Field

[0001] The present invention belongs to the technical field of laser ranging, and particularly relates to a vernier caliper type pulsed laser ranging system and method. Background Art

[0002] With the wide application of laser ranging technology in fields such as industrial inspection, autonomous driving, and geodetic surveying, the pulsed laser ranging method has received key attention due to its advantages such as long measurement distance and strong anti-interference ability. Traditional pulsed laser ranging mainly adopts the principle of time-of-flight (TOF), and calculates the target distance by measuring the product of the round-trip time of the laser pulse and the speed of light. However, the measurement accuracy of this method is limited by the resolution of the time interval measurement device, and the existing technology faces the contradiction between accuracy improvement and cost control.

[0003] In the prior art, although a high-precision time-to-digital converter (TDC) can achieve picosecond-level time resolution, its expensive manufacturing cost is difficult to meet the large-scale application requirements in the civilian field. And the digital circuit scheme adopting the time expansion method reduces the hardware cost, but the measurement stability decreases due to the accumulation of signal jitter. Some improvement schemes attempt to improve the signal-to-noise ratio through multiple average measurements, but significantly increase the system power consumption and reduce the real-time performance.

[0004] In the field of phase method ranging, some researchers have proposed to use the vernier ranging principle to improve the resolution. However, this method has an inherent contradiction between the modulation frequency and the ranging range in long-distance measurement: although high-frequency modulation can improve the accuracy, it causes a significant reduction in the maximum unambiguous distance. In addition, existing vernier type schemes are mostly designed for continuous wave lasers, and it is difficult to adapt to the transient characteristics of pulsed lasers, and the anti-interference ability in complex environments is insufficient.

[0005] In recent years, the development of metasurface optical devices has provided a new idea for optical path subdivision. However, such schemes have extremely high requirements for the calibration accuracy of the optical system, and the change of environmental temperature is likely to cause optical path drift, which limits their engineering practicability. The existing technology has not effectively solved the key technical problem of achieving low-cost and high-precision time interval measurement while maintaining the inherent advantages of pulsed laser ranging. Summary of the Invention

[0006] Aiming at the above-mentioned defects existing in the prior art, the present invention provides a vernier caliper type pulsed laser ranging system and method, which has the advantages of simple structure, low cost, easy implementation, etc. while improving the ranging accuracy.

[0007] The present invention is realized through the following technical solutions:

[0008] A vernier caliper type pulsed laser ranging system, comprising: a control and calculation unit 1, a pulse generation unit 2, a dual-channel synchronous pulse counting unit 3, an LD driving unit 4 and a photoelectric detection unit 5; the control and calculation unit 1 is used to send a trigger signal to drive the pulse generation unit 2 to generate a pulse and start the dual-channel synchronous pulse counting unit 3 to count and time. The pulse generation unit 2 has two output ports, respectively outputting a first pulse with a period of T L and a second pulse with a period of T S . The first pulse is directly input into the dual-channel synchronous pulse counting unit 3, and the second pulse is input into the LD driving unit 4. The LD driving unit 4 emits pulsed laser, which is received by the photoelectric detection unit 5 after being reflected by an object and converted into an electrical pulse signal and input into the dual-channel synchronous pulse counting unit 3. The dual-channel synchronous pulse counting unit 3 synchronously counts and measures the time difference of the two received pulse signals, and transmits the data back to the control and calculation unit 1 for distance calculation.

[0009] Further, the control and calculation unit 1 includes an FPGA 8 and an embedded processor. The FPGA is used to generate a synchronous trigger signal and output it to the pulse generation unit 2 and the dual-channel synchronous pulse counting unit 3 through dedicated I / O pins to achieve high-precision timing control. The embedded processor is used to run algorithms and system management.

[0010] Further, the pulse generation unit 2 includes a temperature-controlled crystal oscillator 6, a splitter 7 and a DDS chip 9. The temperature-controlled crystal oscillator 6 outputs a 10 GHz clock signal, which is distributed to the FPGA 8 and the DDS chip 9 through a 1:2 splitter 7; the DDS chip 9 outputs two pulses with periods of T L and T S respectively under the control of the FPGA 8, and realizes the initial phase alignment of the two pulses through a digital phase-locked loop (DPLL).

[0011] Further, the dual-channel synchronous pulse counting unit 3 includes a vernier ring oscillator 20, a counter and latch 21, a phase comparator 22 and a calibration circuit 23. The two pulse signals sent by the driving pulse generation unit 2 and the photoelectric detection unit 5 are optimized by delay units through the vernier ring oscillator 20, and the signal transmission duration is finely adjusted by using a tail current adjustment mechanism. Then, the counter and latch 21 respectively record the oscillation cycle numbers of the main ring and the sub-ring, and calculate the time difference between the two pulse signals based on the oscillation cycle numbers of the two rings; the phase comparator 22 is used to detect whether the edges of the two pulse signals are aligned. If the absolute value of the detected time difference ∣Δt∣ < ∣T L -T SIf it is ∣ / 2, it is determined as phase synchronization, the stop signal is triggered, and the frequency deviation of the vernier ring oscillator 20 is dynamically calibrated by the calibration circuit 23 with the built-in reference clock; finally, the control and calculation unit 1 calculates and processes the pulse counting time and the number of counted pulses returned, and outputs a high-precision ranging result.

[0012] Further, the adjustment step of the tail current adjustment mechanism is 5 picoseconds.

[0013] Further, the LD driving unit 4 includes a first high-speed comparator 10, a level conversion chip 11, a dedicated driving chip 12, a GaN FET array 13, and an LD 14. The LD driving unit 4 receives the second pulse from the pulse generating unit 2 through a high-speed coaxial cable. The input pulse is converted into a CMOS signal with a steep edge by the first high-speed comparator 10, and then the CMOS signal is converted into the gate driving voltage required by the GaN FET array 13 through the level conversion chip 11. The dedicated driving chip 12 receives the shaped signal and outputs a driving pulse with a peak current of 5A, and the driving signal triggers the GaN FET array 13 to output a driving pulse with a current of 100A. The output end of the GaN FET is connected to the pin of the LD 14 through a flexible PCB. The current pulse output by the GaN FET drives the LD14 to emit an optical pulse with a wavelength of 905 nm and a peak power of 75W.

[0014] Further, the photoelectric detection unit 5 includes an APD 16, a transimpedance amplifier 17, a fourth-order Butterworth filter 18, and a second high-speed comparator 19. The photoelectric detection unit 5 receives the laser pulse reflected from the target. The incident light is focused on the effective photosensitive area of the APD 16 through the aspherical lens 15. The APD 16 operates in the avalanche mode and is applied with a reverse bias voltage of 150V. Photons hitting the APD depletion layer generate electron-hole pairs, which are amplified into current pulses through the avalanche effect; the current pulse output by the APD 16 is converted into a voltage signal by the transimpedance amplifier 17, and the output pulse width is synchronized with the input optical pulse; the fourth-order Butterworth filter 18 is used to suppress ambient light and power supply noise, and the analog signal filtered by the fourth-order Butterworth filter 18 is sent to the high-speed comparator 19 to be converted into an LVDS digital pulse and sent to the dual-channel synchronous pulse counting unit 3.

[0015] Further, the diameter of the effective photosensitive area of the APD 16 is 0.2 mm; the center frequency of the fourth-order Butterworth filter 18 is 100 MHz, and the bandwidth is 50 MHz.

[0016] On the other hand, the present invention also provides a method for a vernier caliper type pulsed laser ranging system, specifically including the following steps:

[0017] Step 1: System initialization and parameter pre-configuration;

[0018] Step 2: Synchronous Triggering and Dual-Pulse Generation;

[0019] Executed jointly by the pulse generation unit 2 and the FPGA 8:

[0020] The FPGA 8 sends an LVTTL trigger signal to the pulse generation unit 2 and the dual-channel synchronous pulse counting unit 3 through a dedicated global clock network, with a path length matching error < 0.1 mm;

[0021] The DDS chip 9 generates two orthogonally modulated pulse signals;

[0022] The two pulse signals include:

[0023] A. The first pulse with a main channel output period T L is directly input into the dual-channel synchronous pulse counting unit 3;

[0024] B. The second pulse with a sub-channel output period T S is input into the LD driving unit 4 after FM-AM composite modulation;

[0025] Step 3: Laser Driving and Optical Carrier Emission;

[0026] Input the second pulse with a period T S into the LD driver to drive the laser diode to emit a frequency-modulated and amplitude-modulated continuous optical wave with a wavelength of 1550 nm, and its optical power output satisfies:

[0027] P(t) = P0·[1 + m·cos(2πf AM t)],

[0028] where P0 = 20 mW, m = 0.8;

[0029] The optical carrier frequency is modulated in a linear frequency sweep mode: f FM (t) = f0 + k·t

[0030] where P(t) is the amplitude-modulated signal power varying with time t, P0 is the carrier power before modulation, m is the modulation index, f AM is the frequency of the modulation signal; t is time, f0 is the initial carrier frequency, and the frequency sweep slope k is 100 MHz / ms;

[0031] Step 4: Echo Signal Reception and Processing;

[0032] The APD 16 receives the reflected optical signal under a reverse bias of 150 V, converts it into a voltage signal through the transimpedance amplifier 17, filters it through the 4th-order Butterworth filter 18, and then shapes the filtered signal into an LVDS digital pulse through the second high-speed comparator 19 and inputs it into the sub-channel of the dual-channel synchronous pulse counting unit 3;

[0033] Step Five: Dual-channel Synchronous Counting and Alignment Detection;

[0034] Under the control of the trigger signal, the two counters are synchronously reset, and the counter and the latch 21 respectively record the oscillation cycle numbers of the main loop and the secondary loop;

[0035] The time difference Δt between the edges of the two pulses is monitored in real time. When ∣Δt∣ < ∣T L -T S ∣ / 2, the counter and the latch 21 are triggered to lock the count values N and M of the two pulses;

[0036] Step Six: Flight Time Calculation and Dynamic Calibration;

[0037] Calculate the flight time t = N·T L +M·ΔT - tcal, where tcal is the inherent delay calibration value stored in the EEPROM;

[0038] Calculate the target distance d according to the formula d = c·t / 2, where c is the speed of light;

[0039] Among them, the system delay error is dynamically corrected by the least squares method, and the bias voltage is adjusted according to the temperature data of the APD;

[0040] Step Seven: Data Output and System Reset;

[0041] The real-time distance data is displayed through the LCD and uploaded to the host computer through the LVDS or Ethernet interface;

[0042] When detecting counter overflow or over-temperature failure, trigger the safety mode and reset the system.

[0043] Furthermore, in Step Two, the FM-AM composite modulation specifically includes:

[0044] B10. Generate a linear frequency-swept triangular wave with a frequency range of 1 - 1.1 GHz and a period of 1 ms as the FM signal;

[0045] B20. Generate a sine wave with a frequency of 10 kHz as the AM signal, and the modulation depth is 80%;

[0046] B30. Mix the FM signal and the AM signal through a multiplier to generate a composite modulation signal.

[0047] Compared with the prior art, the advantages of the present invention are as follows:

[0048] 1. The present invention uses the principle of dual-pulse vernier caliper to improve the time resolution to the sub-nanosecond level, and the theoretical ranging accuracy reaches 1.5 cm, far exceeding the traditional single-pulse scheme;

[0049] 2. Adaptive adjustment of the main pulse period (10 ns - 1 μs) is adopted, with a measurement range covering 15 m to 150 km, solving the contradiction between long / short distance measurements; and through co-prime period design (such as TL = 1000 ns, TR = 999 ns), the multi-period phase ambiguity problem is avoided;

[0050] 3. Strong anti-interference and strong environmental adaptability;

[0051] Dynamic delay calibration: The built-in reference channel measures the inherent delay of the system in real time (such as LD drive and detector circuit delays), dynamically corrects tcal, and the compensation accuracy reaches ±5 ps;

[0052] Through dynamic adjustment of the APD bias voltage (ΔVbias / ΔT = -0.05% / °C) and FPGA clock compensation, it adapts to the wide temperature environment of -40°C to +85°C;

[0053] Noise immunity design: Dual-channel majority vote filtering (requiring 3 consecutive alignments for confirmation) and band-pass filters (suppressing interference in non-laser bands) to improve the signal-to-noise ratio (SNR > 20 dB);

[0054] 4. The modular architecture (general DDS chip + FPGA hybrid design) replaces the dedicated chip, shortening the development cycle and reducing the hardware cost;

[0055] 5. All-solid-state without mechanical components, with a service life exceeding 100,000 hours. Description of the Drawings

[0056] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0057] Figure 1 It is the overall structural block diagram of a vernier caliper type pulsed laser ranging system of the present invention;

[0058] Figure 2 It is the structural block diagram of the pulse generation unit of the present invention;

[0059] Figure 3 It is the structural block diagram of the LD drive unit of the present invention;

[0060] Figure 4 It is the structural block diagram of the photoelectric detection unit of the present invention;

[0061] Figure 5 It is the structural block diagram of the dual-channel synchronous pulse counting unit of the present invention;

[0062] Figure 6Schematic diagram of pulse count alignment detection for the vernier caliper type pulsed laser ranging system of the present invention;

[0063] In the figure: control and calculation unit 1, pulse generation unit 2, dual-channel synchronous pulse counting unit 3, LD driving unit 4, photoelectric detection unit 5, constant temperature crystal oscillator 6, splitter 7, FPG8, DDS chip 9, first high-speed comparator 10, level conversion chip 11, dedicated driver chip 12, GaN FET array 13, LD 14, APD16, transimpedance amplifier 17, 4th-order Butterworth filter 18, second high-speed comparator 19, vernier ring oscillator 20, counter and latch 21, phase comparator 22, calibration circuit 23. Specific implementation mode

[0064] To clearly and completely describe the technical solution of the present invention and its specific working process, in combination with the accompanying drawings of the specification, the specific implementation mode of the present invention is as follows:

[0065] Embodiment 1

[0066] As Figure 1 shown, this embodiment provides a vernier caliper type pulsed laser ranging system, including: a control and calculation unit 1, a pulse generation unit 2, a dual-channel synchronous pulse counting unit 3, an LD driving unit 4 and a photoelectric detection unit 5; the control and calculation unit 1 is used to send a trigger signal to drive the pulse generation unit 2 to generate a pulse and start the dual-channel synchronous pulse counting unit 3 to count and time. The pulse generation unit 2 has two output ports, respectively outputting a first pulse with a period of T L and a second pulse with a period of T S . The first pulse is directly input into the dual-channel synchronous pulse counting unit 3, and the second pulse is input into the LD driving unit 4. The LD driving unit 4 emits pulsed laser, which is reflected by an object and received by the photoelectric detection unit 5 and converted into an electrical pulse signal and input into the dual-channel synchronous pulse counting unit 3. The dual-channel synchronous pulse counting unit 3 synchronously counts and measures the time difference of the two received pulse signals, and returns the data to the control and calculation unit 1 for distance calculation.

[0067] The control and calculation unit 1 includes an FPGA8 and an embedded processor. In this embodiment, an ARM Cortex-A53 processor is used. The FPGA is used to generate a synchronous trigger signal and output it to the pulse generation unit 2 and the dual-channel synchronous pulse counting unit 3 through dedicated I / O pins to achieve high-precision timing control. The embedded processor is used to run algorithms and system management.

[0068] As Figure 2As shown in the figure, the pulse generation unit 2 in this embodiment can generate two high-precision pulse signals simultaneously, ensuring that the two pulses start strictly synchronously and have steep pulse edges. The pulse generation unit 2 includes a temperature-controlled crystal oscillator 6, a splitter 7, and a DDS chip 9. The temperature-controlled crystal oscillator 6 outputs a 10 GHz clock signal, which is distributed to the FPGA 8 and the DDS chip 9 through a 1:2 splitter 7. The DDS chip 9 outputs two pulses with periods of T L and T S under the control of the FPGA 8, and the initial phases of the two pulses are aligned through a digital phase-locked loop (DPLL).

[0069] As Figure 5 shown in the figure, the dual-channel synchronous pulse counting unit 3 in this embodiment is implemented by a time-to-digital converter (TDC). The main channel is directly connected to the pulse generation unit 2, and reflections are reduced through an impedance matching network. The secondary channel is input through the photoelectric detection unit 5, and a band-pass filter is added to suppress noise. Specifically, the dual-channel synchronous pulse counting unit 3 includes a vernier ring oscillator 20, a counter and latch 21, a phase comparator 22, and a calibration circuit 23. The two pulse signals sent by the driving pulse generation unit 2 and the photoelectric detection unit 5 are optimized by the delay unit of the vernier ring oscillator 20, and the signal transmission duration is finely adjusted by using the tail current adjustment mechanism. The adjustment step of the tail current adjustment mechanism is 5 picoseconds. Then, the counter and latch 21 record the oscillation cycle numbers of the main loop and the secondary loop respectively, and calculate the time difference between the two pulse signals based on the oscillation cycle numbers of the two loops. The phase comparator 22 is used to detect whether the edges of the two pulse signals are aligned. If it is detected that the absolute value of the time difference |Δt| < |T L -T S | / 2, and in this embodiment, |Δt| < 10 ps is selected, it is determined that the phases are synchronized, and a stop signal is triggered. The calibration circuit 23 with an internal reference clock (such as a 100 MHz crystal oscillator) dynamically calibrates the frequency deviation of the vernier ring oscillator 20. Finally, the control and calculation unit 1 calculates and processes the pulse counting time and the number of counted pulses returned, and outputs a high-precision ranging result.

[0070] As Figure 3As shown in the figure, the LD driving unit 4 in this embodiment includes a first high-speed comparator 10, a level conversion chip 11, a dedicated driving chip 12, a GaN FET array 13, and an LD 14. The LD driving unit 4 receives the second pulse from the pulse generating unit 2 through a high-speed coaxial cable. The input pulse is converted into a CMOS signal with a steep edge by the first high-speed comparator 10. Then, the CMOS signal is converted into the gate driving voltage required by the GaN FET array 13 through the level conversion chip 11. The dedicated driving chip 12 receives the shaped signal and outputs a driving pulse with a peak current of 5A. The driving signal triggers the GaN FET array 13 to output a driving pulse with a current of 100A. The output end of the GaN FET is connected to the pin of the LD 14 through a flexible PCB. The current pulse output by the GaN FET drives the LD14 to emit an optical pulse with a wavelength of 905nm and a peak power of 75W.

[0071] As Figure 4 shown in the figure, the photoelectric detection unit 5 in this embodiment includes an APD 16, a transimpedance amplifier 17, a fourth-order Butterworth filter 18, and a second high-speed comparator 19. The photoelectric detection unit 5 receives the laser pulse reflected from the target. The incident light is focused on the effective photosensitive area of the APD 16 through the aspherical lens 15. The APD 16 operates in the avalanche mode and is applied with a reverse bias voltage of 150V. Photons hitting the APD depletion layer generate electron-hole pairs, which are amplified into current pulses through the avalanche effect. The current pulse output by the APD 16 is converted into a voltage signal by the transimpedance amplifier 17, and the output pulse width is synchronized with the input optical pulse. The fourth-order Butterworth filter 18 is used to suppress ambient light and power supply noise. The analog signal filtered by the fourth-order Butterworth filter 18 is sent to the high-speed comparator 19 to be converted into an LVDS digital pulse, and then sent to the dual-channel synchronous pulse counting unit 3.

[0072] Among them, the diameter of the effective photosensitive area of the APD 16 is 0.2mm; the center frequency of the fourth-order Butterworth filter 18 is 100MHz, and the bandwidth is 50MHz.

[0073] Embodiment 2

[0074] This embodiment provides a method for a vernier caliper type pulsed laser ranging system, which specifically includes the following steps:

[0075] Step 1: System initialization and parameter pre-configuration;

[0076] The following content is executed by the embedded processor of the control and calculation unit 1:

[0077] S100. Read the calibration parameters pre-stored in the EEPROM through the SPI bus, including the double-pulse period parameters T L 、T S = TL -ΔT (ΔT << T L ), the inherent delay calibration value tcal, the temperature compensation coefficient, and the alignment detection threshold;

[0078] S110. Detect the temperature of the GaN FET in the LD driving unit 4, the counter synchronization of the dual-channel synchronous pulse counting unit 3, and the system power supply voltage, and trigger the output of a fault code when abnormal;

[0079] S120. Receive the ranging mode parameters input by the user and write them into the FPGA8 register, and configure T L = 10 ns, ΔT = 0.1 ns in the high-precision mode, and configure T L = 1 μs in the long-distance mode;

[0080] Step Two: Synchronous Triggering and Dual-Pulse Generation;

[0081] Executed jointly by the pulse generation unit 2 and the FPGA8:

[0082] The FPGA8 sends an LVTTL trigger signal to the pulse generation unit 2 and the dual-channel synchronous pulse counting unit 3 through a dedicated global clock network, and the path length matching error < 0.1 mm;

[0083] The DDS chip 9 generates two orthogonally modulated pulse signals;

[0084] The two pulse signals include:

[0085] A. The first pulse with a main channel output period T L is directly input into the dual-channel synchronous pulse counting unit 3;

[0086] B. The second pulse with a sub-channel output period T S is input into the LD driving unit 4 after FM-AM composite modulation;

[0087] Among them, the FM-AM composite modulation specifically includes:

[0088] B10. Generate a linear frequency-swept triangular wave with a frequency range of 1 - 1.1 GHz and a period of 1 ms as the FM signal;

[0089] B20. Generate a sine wave with a frequency of 10 kHz as the AM signal, and the modulation depth is 80%;

[0090] B30. Mix the FM signal and the AM signal through a multiplier to generate a composite modulation signal.

[0091] Step Three: Laser Driving and Optical Carrier Emission;

[0092] The period T SThe second pulse input LD driver drives the laser diode to emit a frequency-modulated and amplitude-modulated continuous optical wave with a wavelength of 1550 nm, and its optical power output satisfies:

[0093] P(t) = P0·[1 + m·cos(2πf AM t)],

[0094] where P0 = 20 mW and m = 0.8;

[0095] The optical carrier frequency is modulated in a linear frequency-sweeping mode: f FM (t) = f0 + k·t

[0096] where P(t) is the amplitude-modulated signal power varying with time t, P0 is the carrier power without modulation, m is the modulation index, and f AM is the frequency of the modulation signal; t is the time, f0 is the initial carrier frequency, and the frequency-sweeping slope k is 100 MHz / ms;

[0097] Step Four: Echo signal reception and processing;

[0098] S400, APD16 receives the reflected optical signal under a reverse bias of 150 V. Among them, the APD operates in the avalanche mode (bias voltage Vbias = 150 V), the avalanche gain M = 100, and the sensitivity reaches -50 dBm;

[0099] S410, The reflected optical signal is converted into a voltage signal by the transimpedance amplifier 17 (gain Rf = 10 kΩ), and then filtered by the 4th-order Butterworth filter 18. The filtered signal is shaped into an LVDS digital pulse by the second high-speed comparator 19 (threshold Vth = 50 mV) and input into the sub-channel of the dual-channel synchronous pulse counting unit 3;

[0100] Step Five: Dual-channel synchronous counting and alignment detection;

[0101] S500, Under the control of the trigger signal, the two counters are synchronously reset, and the counters and the latch 21 respectively record the oscillation cycle numbers of the main loop and the sub-loop;

[0102] S510, Real-time monitor the time difference Δt between the edges of the two pulses. When |Δt| < |T L - T S | / 2, trigger the counters and the latch 21 to lock the count values N and M of the two pulses;

[0103] Among them, this embodiment adopts a majority voting mechanism: the count values N and M are locked after detecting alignment three times continuously;

[0104] Step Six: Flight time calculation and dynamic calibration;

[0105] S600. Calculate the flight time t = N·T L + M·ΔT - tcal, where tcal is the inherent delay calibration value stored in the EEPROM;

[0106] S610. Calculate the target distance d according to the formula d = c·t / 2, where c is the speed of light;

[0107] Among them, the system delay error is dynamically corrected by the least squares method, and the bias voltage is adjusted according to the temperature data of the APD to suppress the gain drift;

[0108] Step Seven: Data output and system reset;

[0109] S700. Display the real-time distance data through the LCD and upload it to the host computer through the LVDS or Ethernet interface; after completing a single measurement, the counter is automatically reset and waits for the next trigger signal.

[0110] S710. When detecting a counter overflow or overtemperature fault, trigger the safety mode and reset the system.

[0111] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0112] In addition, it should be noted that, in the case of no contradiction, the various specific technical features described in the above specific embodiments can be combined in any appropriate way. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0113] In addition, any combination can be made between different embodiments of the present invention, as long as it does not violate the idea of the present invention, it should also be regarded as the content disclosed by the present invention.

Claims

1. A vernier caliper type pulsed laser ranging system, characterized in that, It includes: Control and calculation unit (1), pulse generation unit (2), dual-channel synchronous pulse counting unit (3), LD driving unit (4) and photoelectric detection unit (5); the control and calculation unit (1) is used to send a trigger signal to drive the pulse generation unit (2) to generate pulses and start the dual-channel synchronous pulse counting unit (3) to count and time. The pulse generation unit (2) has two output ports, respectively outputting a first pulse with a period of T L and a second pulse with a period of T S . The first pulse is directly input into the dual-channel synchronous pulse counting unit (3), and the second pulse is input into the LD driving unit (4). The LD driving unit (4) emits pulsed laser, which is reflected by the object and received by the photoelectric detection unit (5), and converted into an electrical pulse signal and input into the dual-channel synchronous pulse counting unit (3). The dual-channel synchronous pulse counting unit (3) synchronously counts and measures the time difference of the two received pulse signals, and transmits the data back to the control and calculation unit (1) for distance calculation.

2. A vernier caliper type pulsed laser ranging system according to claim 1, characterized in that, The control and computing unit (1) includes an FPGA (8) and an embedded processor. The FPGA is used to generate a synchronous trigger signal, which is output to the pulse generation unit (2) and the dual-channel synchronous pulse counting unit (3) through dedicated I / O pins to achieve high-precision timing control. The embedded processor is used to run algorithms and system management.

3. A vernier caliper type pulsed laser ranging system according to claim 1, characterized in that, The pulse generating unit (2) includes a temperature-controlled crystal oscillator (6), a splitter (7) and a DDS chip (9). The temperature-controlled crystal oscillator (6) outputs a 10 GHz clock signal, which is distributed to the FPGA 8 and the DDS chip (9) through a 1:2 splitter (7). The DDS chip (9) outputs two paths of pulses with periods of T L , T S under the control of the FPGA (8), and the initial phase alignment of the two paths of pulses is achieved through a digital phase-locked loop.

4. A vernier caliper type pulsed laser ranging system according to claim 1, characterized in that, The dual-channel synchronous pulse counting unit (3) includes a vernier ring oscillator (20), a counter and a latch (21), a phase comparator (22), and a calibration circuit (23). The two pulse signals sent by the driving pulse generating unit (2) and the photoelectric detection unit (5) are optimized by the vernier ring oscillator (20) for the delay unit, and the tail current adjustment mechanism is used to finely adjust the signal transmission duration. Then, the counter and the latch (21) are used to record the oscillation cycle numbers of the main ring and the secondary ring respectively, and the time difference between the two pulse signals is calculated based on the oscillation cycle numbers of the two rings. The phase comparator (22) is used to detect whether the edges of the two pulse signals are aligned. If the absolute value of the detected time difference |Δt| < |T L -T S | / 2, it is determined that the phases are synchronized, and a stop signal is triggered. The calibration circuit (23) with an internal reference clock dynamically calibrates the frequency deviation of the vernier ring oscillator (20). Finally, the control and calculation unit (1) calculates and processes the returned pulse counting time and the number of counted pulses to output a high-precision ranging result.

5. The vernier caliper type pulsed laser ranging system according to claim 4, characterized in that The adjustment step of the tail current adjustment mechanism is 5 picoseconds.

6. A vernier caliper type pulsed laser ranging system according to claim 1, characterized in that, The LD driving unit (4) includes a first high-speed comparator (10), a level conversion chip (11), a dedicated driving chip (12), a GaN FET array (13), and an LD (14). The LD driving unit (4) receives a second pulse from the pulse generation unit (2) through a high-speed coaxial cable. The first high-speed comparator (10) converts the input pulse into a CMOS signal with a steep edge, and then the level conversion chip (11) converts the CMOS signal into the gate drive voltage required by the GaN FET array (13). The dedicated driving chip (12) receives the shaped signal and outputs a driving pulse with a peak current of (5) A. The driving signal triggers the GaN FET array (13) to output a driving pulse with a current of (100) A. The output end of the GaN FET is connected to the pin of the LD (14) through a flexible PCB. The current pulse output by the GaN FET drives the LD (14) to emit an optical pulse with a wavelength of 905 nm and a peak power of 75 W.

7. A vernier caliper type pulsed laser ranging system according to claim 1, characterized in that, The photoelectric detection unit (5) includes an APD (16), a transimpedance amplifier (17), a fourth-order Butterworth filter (18), and a second high-speed comparator (19). The photoelectric detection unit (5) receives the laser pulse reflected from the target. The incident light is focused on the effective photosensitive area of the APD (16) through an aspherical lens (15). The APD (16) operates in avalanche mode and is applied with a reverse bias voltage of 150 V. Photons strike the APD depletion layer to generate electron-hole pairs, which are amplified into a current pulse through the avalanche effect. The current pulse output by the APD (16) is converted into a voltage signal by the transimpedance amplifier (17), and the output pulse width is synchronized with the input optical pulse. The fourth-order Butterworth filter (18) is used to suppress ambient light and power supply noise. The analog signal filtered by the fourth-order Butterworth filter (18) is sent to the high-speed comparator (19) to be converted into an LVDS digital pulse, which is sent to the dual-channel synchronous pulse counting unit (3).

8. A vernier caliper type pulsed laser ranging system according to claim 7, characterized in that, The diameter of the effective photosensitive area of the APD (16) is 0.2 mm; the center frequency of the fourth-order Butterworth filter (18) is 100 MHz, and the bandwidth is 50 MHz.

9. The method of a vernier caliper type pulsed laser ranging system according to claim 1, characterized in that Specifically, it includes the following steps: Step 1: System initialization and parameter pre-configuration; Step 2: Synchronous trigger and dual-pulse generation; It is jointly executed by the pulse generation unit (2) and the FPGA (8): The FPGA (8) sends an LVTTL trigger signal to the pulse generation unit (2) and the dual-channel synchronous pulse counting unit (3) through a dedicated global clock network, and the path length matching error <0.1 mm; The DDS chip (9) generates two orthogonally modulated pulse signals; The two-way pulse signals include: A. Main channel output period T L The first pulse is directly input into the dual-channel synchronous pulse counting unit (3); B. Secondary channel output period T S The second pulse is input into the LD driving unit (4) after being subjected to FM-AM composite modulation; Step 3: Laser driving and optical carrier emission; Input the second pulse with a period T S into the LD driver to drive the laser diode to emit a frequency-modulated and amplitude-modulated continuous optical wave with a wavelength of 1550 nm, and its optical power output satisfies: P(t) = P0·[1 + m·cos(2πf AM t)], where P0 = 20 mW and m = 0.8; The optical carrier frequency is modulated in a linear frequency sweep mode: f FM (t) = f0 + k·t Among them, P(t) is the power of the amplitude-modulated signal varying with time t, P0 is the carrier power when not modulated, m is the modulation index, and f AM is the frequency of the modulation signal; t is the time, f0 is the initial carrier frequency, and the sweep rate k is 100 MHz / ms; Step 4: Echo signal reception and processing; APD (16) receives the reflected optical signal under a reverse bias of 150 V, converts it into a voltage signal via a transimpedance amplifier (17), filters the signal via a 4th-order Butterworth filter (18), and then shapes the filtered signal into an LVDS digital pulse through a second high-speed comparator (19), and inputs it into the sub-channel of the dual-channel synchronous pulse counting unit (3); Step 5: Dual-channel synchronous counting and alignment detection; Under the control of the trigger signal, the two counters are synchronously reset, and the counters and the latch (21) respectively record the oscillation cycle numbers of the main loop and the sub-loop; Real-time monitor the time difference Δt between the edges of two pulses. When ∣Δt∣<∣T L -T S ∣ / 2 is satisfied, trigger the counter and the latch (21) to lock the count values N and M of the two pulses; Step 6: Flight time calculation and dynamic calibration; Calculate the flight time t = N·T L + M·ΔT - tcal, where tcal is the inherent delay calibration value stored in the EEPROM; Calculate the target distance d according to the formula d = c·t / 2, where c is the speed of light; wherein, the system delay error is dynamically corrected by the least squares method, and the bias voltage is adjusted according to the temperature data of the APD; Step 7: Data output and system reset; Display the real-time distance data through the LCD and upload it to the host computer via the LVDS or Ethernet interface; When detecting a counter overflow or over-temperature fault, trigger the safety mode and reset the system.

10. The method of a vernier caliper type pulsed laser ranging system as claimed in claim 9, characterized in that, In Step 2, the FM-AM composite modulation specifically includes: B10. Generate a linear frequency-swept triangular wave with a frequency range of 1 - 1.1 GHz and a period of 1 ms as the FM signal; B20. Generate a sine wave with a frequency of 10 kHz as the AM signal, and the modulation depth is 80%; B30. Mix the FM signal and the AM signal through a multiplier to generate a composite modulation signal.

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