High-precision reference circuit, PCB and chip

Abstract

The invention relates to the technical field of electronics, and discloses a high-precision reference circuit, a PCB and a chip, the high-precision reference circuit comprises a starting unit, a reference unit, a bias unit and an operational amplifier unit; the reference unit comprises two feedback loops; the starting unit is used for providing a starting condition for the reference unit, and the bias unit is used for providing stable bias current for the reference unit and the operational amplifier unit, so that the working stability of each unit is ensured; then the operational amplifier unit is used for assisting the reference unit to generate the reference voltage, meanwhile, the reference unit eliminates the influence of the offset voltage generated by the amplifier unit on the reference voltage through two feedback loops in the reference unit, interference of the offset voltage on the reference voltage is reduced, and the precision and stability of the reference voltage are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a high-precision reference circuit, a PCB board and a chip. Background Art

[0002] In the current era of rapid development of electronic technology, highly integrated intelligent power drive chips have been widely used in many fields, such as communication devices, consumer electronics and industrial automation systems; the control and protection circuits in such chips have extremely high requirements for the accuracy and stability of the reference voltage, because the accuracy of the reference voltage directly affects the performance of the entire system.

[0003] However, in the traditional design of reference circuits, due to the inability to effectively overcome the influence of the offset voltage of the operational amplifier, it is difficult to output a reference voltage with high precision and temperature stability, which seriously restricts the further development of highly integrated intelligent power drive chips.

[0004] It can be seen that the existing technology still needs to be improved. Summary of the Invention

[0005] The present invention aims to improve at least one technical problem in the background art.

[0006] The first aspect embodiment of the present invention provides a high-precision reference circuit, including a startup unit, a reference unit, a bias unit and an operational amplifier unit;

[0007] The reference unit includes a first feedback loop and a second feedback loop; the first feedback loop and the second feedback loop are connected between the node in the reference unit affected by the signal of the operational amplifier unit and the node where the reference voltage is generated; the first feedback loop and the second feedback loop are used to eliminate the influence of the offset voltage generated by the operational amplifier unit on the reference voltage;

[0008] The startup unit is connected to the reference unit and is used to start the reference unit;

[0009] The bias unit is connected to the reference unit and the operational amplifier unit and is used to provide bias current and bias voltage for the reference unit and the operational amplifier unit;

[0010] The operational amplifier unit is connected to the reference unit and is used to assist the reference unit in generating a reference voltage.

[0011] The beneficial effects of the embodiments of the first aspect of the present invention are as follows: The present invention first uses a startup unit to provide startup conditions for a reference unit, and uses a bias unit to provide a stable bias current for the reference unit and an operational amplifier unit, thereby ensuring the stability of the operation of each unit; then uses the operational amplifier unit to assist the reference unit in generating a reference voltage, and at the same time the reference unit uses two feedback loops therein to eliminate the influence of the offset voltage generated by the amplification unit on the reference voltage; one feedback loop feeds back the offset voltage to a suitable node to compensate for the offset voltage in the circuit; the other feedback loop optimizes and balances the first feedback loop to ensure that the entire process of eliminating the offset voltage is more stable and efficient; the present invention fundamentally reduces the interference of the offset voltage on the reference voltage and significantly improves the accuracy and stability of the reference voltage.

[0012] As some sub-schemes of the above technical solution, the startup unit includes an eighteenth field effect transistor M18, a nineteenth field effect transistor M19, a twentieth field effect transistor M20, a twenty-first field effect transistor M21, a twenty-second field effect transistor M22, and a power supply voltage terminal; the source of the eighteenth field effect transistor M18 is connected to the source of the nineteenth field effect transistor M19 and the power supply voltage terminal, the gate of the eighteenth field effect transistor M18 is grounded, and the drain of the eighteenth field effect transistor M18 is connected to the gate of the twentieth field effect transistor M20 and the drain of the twenty-first field effect transistor M21; the gate of the nineteenth field effect transistor M19 is connected to the drain of the twentieth field effect transistor M20 and the reference unit, and the drain of the nineteenth field effect transistor M19 is connected to the drain of the twenty-second field effect transistor M22, the gate of the twenty-second field effect transistor M22, and the gate of the twenty-first field effect transistor M21; the source of the twentieth field effect transistor M20, the source of the twenty-first field effect transistor M21, and the source of the twenty-second field effect transistor M22 are all grounded.

[0013] As some sub - solutions of the above - mentioned technical solution, the reference unit includes a first field - effect transistor M1, a second field - effect transistor M2, a third field - effect transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; the source of the first field - effect transistor M1 is connected to the sources of the second field - effect transistor M2, the third field - effect transistor M3, and the nineteenth field - effect transistor M19; the gate of the first field - effect transistor M1 is connected to the gates of the second field - effect transistor M2, the third field - effect transistor M3, the nineteenth field - effect transistor M19, and the bias unit; the drain of the first field - effect transistor M1 is connected to the first end of the first resistor R1 and the operational - amplifier unit, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and a first feedback loop is provided between the second end of the first resistor R1 and the drain of the third field - effect transistor M3; the second end of the second resistor R2 is connected to the emitter of the third transistor Q3; the drain of the second field - effect transistor M2 is connected to the first end of the third resistor R3 and the operational - amplifier unit, the second end of the third resistor R3 is connected to the emitter of the fourth transistor Q4, and a second feedback loop is provided between the second end of the third resistor R3 and the drain of the third field - effect transistor M3; the drain of the third field - effect transistor M3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded; the base of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and the emitter of the second transistor Q2, the gate of the fourth transistor Q4 is connected to the collector of the third transistor Q3 and the emitter of the first transistor Q1, the gate of the first transistor Q1 is connected to the gate of the second transistor Q2 and is grounded, and the collectors of the first transistor Q1 and the second transistor Q2 are grounded.

[0014] As some sub - solutions of the above - mentioned technical solution, the first feedback loop includes a first feedback resistor RF1, and the second feedback loop includes a second feedback resistor RF2; the first end of the first feedback resistor RF1 is connected to the second end of the first resistor R1, and the second end of the first feedback resistor RF1 is connected to the drain of the third field - effect transistor M3; the first end of the second feedback resistor RF2 is connected to the second end of the third resistor R3, and the second end of the second feedback resistor RF2 is connected to the drain of the third field - effect transistor M3; the resistance values of the first feedback resistor RF1 and the second feedback resistor RF2 are equal.

[0015] As some sub - solutions of the above - mentioned technical solution, the channel width - to - length ratios of the first field - effect transistor M1, the second field - effect transistor M2, and the third field - effect transistor M3 are the same.

[0016] As some sub - solutions of the above - mentioned technical solution, the bias unit includes a fourth field - effect transistor M4, a sixth field - effect transistor M6, a fifteenth field - effect transistor M15, and a sixteenth field - effect transistor M16; the source of the fourth field - effect transistor M4 is connected to the source of the third field - effect transistor M3 and the source of the sixteenth field - effect transistor M16, the gate of the fourth field - effect transistor M4 is connected to the gate of the third field - effect transistor M3 and the drain of the sixteenth field - effect transistor M16, the drain of the fourth field - effect transistor M4 is connected to the drain of the sixth field - effect transistor M6, the gate of the sixth field - effect transistor M6, the gate of the fifteenth field - effect transistor M15, and the operational amplifier unit; the source of the sixth field - effect transistor M6 is grounded; the gate of the sixteenth field - effect transistor M16 is connected to the operational amplifier unit, the drain of the sixteenth field - effect transistor M16 is connected to the drain of the fifteenth field - effect transistor M15, and the source of the fifteenth field - effect transistor M15 is grounded.

[0017] As some sub - solutions of the above - mentioned technical solution, the bias unit further includes a seventeenth field - effect transistor M17 and a compensation resistor Rc; the drain of the seventeenth field - effect transistor M17 is connected to its source and the drain of the sixteenth field - effect transistor M16, the gate of the seventeenth field - effect transistor M17 is connected to the first end of the compensation resistor Rc, and the second end of the compensation resistor Rc is connected to the gate of the sixteenth field - effect transistor M16.

[0018] As some sub - solutions of the above - mentioned technical solution, the operational amplifier unit includes a seventh field - effect transistor M7, an eighth field - effect transistor M8, a ninth field - effect transistor M9, a tenth field - effect transistor M10, an eleventh field - effect transistor M11, a twelfth field - effect transistor M12, a thirteenth field - effect transistor M13, a fourteenth field - effect transistor M14, and a fifteenth field - effect transistor M15; the source of the twelfth field - effect transistor M12 is connected to the sources of the thirteenth field - effect transistor M13, the fourteenth field - effect transistor M14, and the fifteenth field - effect transistor M15, the gate of the twelfth field - effect transistor M12 is connected to the gate of the thirteenth field - effect transistor M13, and the gate of the fourteenth field - effect transistor M14 is connected to the gate of the fifteenth field - effect transistor M15; the drain of the twelfth field - effect transistor M12 is connected to the drain of the seventh field - effect transistor M7, the drain of the thirteenth field - effect transistor M13 is connected to the drain of the tenth field - effect transistor M10, the drain of the fourteenth field - effect transistor M14 is connected to the drain of the eleventh field - effect transistor M11, and the drain of the fifteenth field - effect transistor M15 is connected to the drain of the eighth field - effect transistor M8; the gate of the tenth field - effect transistor M10 is connected to the drain of the first field - effect transistor M1, the source of the tenth field - effect transistor M10 is connected to the sources of the eleventh field - effect transistor M11 and the drain of the ninth field - effect transistor M9, and the gate of the eleventh field - effect transistor M11 is connected to the drain of the second field - effect transistor M2; the gate of the ninth field - effect transistor M9 is connected to the gate of the fifteenth field - effect transistor M15, the source of the ninth field - effect transistor M9 is connected to the gates of the seventh field - effect transistor M7 and the eighth field - effect transistor M8, and the sources of the seventh field - effect transistor M7 and the eighth field - effect transistor M8 are grounded.

[0019] The second - aspect embodiment of the present invention provides a PCB board, including the high - precision reference circuit described in any one of the above.

[0020] Due to including the high - precision reference circuit of the above - mentioned technical solution, the PCB board according to the second - aspect embodiment of the present invention also has corresponding beneficial effects.

[0021] The third - aspect embodiment of the present invention provides a chip, including the high - precision reference circuit described in any one of the above.

[0022] Due to including the high - precision reference circuit of the above - mentioned technical solution, the chip according to the third - aspect embodiment of the present invention also has corresponding beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above - mentioned and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0024] Figure 1Circuit block diagram of the high-precision reference circuit provided by the present invention;

[0025] Figure 2 Circuit schematic diagram of the high-precision reference circuit provided by the present invention;

[0026] Figure 3 Application circuit diagram of the high-precision reference circuit provided by the present invention.

[0027] In the drawings: 1 - Start unit 1; 2 - Reference unit 2; 3 - Bias unit 3; 4 - Operational amplifier unit 4. Detailed implementation manners

[0028] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0029] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0030] In the description of the present invention, the meaning of several is indefinite, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the present number, and above, below, within, etc. are understood as including the present number. If the first and the second are described only for the purpose of distinguishing technical features, they should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or the sequence relationship of the indicated technical features. Throughout the text, and / or represents three parallel solutions. For example, A and / or B represents the solution satisfied by A, the solution satisfied by B, or the solution satisfied by both A and B.

[0031] In the description of the present invention, if there is a short sentence containing multiple parallel features, the attributive limits the closest feature. For example: B, C provided on A, E connected to D means that B is provided on A, E is connected to D, and C is not limited; but for the attributive indicating the relationship between features, such as "spaced apart" or "arranged in a ring", etc., it does not belong to this category. If the attributive is preceded by the word "all", it means that all the features in the short sentence are limited. For example, B, C, D all provided on A means that B, C, and D are all provided on A. For the sentence omitting the subject, the omitted subject is the subject of the previous sentence, that is, B is provided on A, including C means that B is provided on A and A includes C.

[0032] In the description of the present invention, unless otherwise clearly defined, terms such as "setting", "installing", "connecting", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0033] The following will be combined with Figures 1 to 3 to illustrate the embodiments of the present invention.

[0034] A high-precision reference circuit in this embodiment includes a startup unit 1, a reference unit 2, a bias unit 3, and an operational amplifier unit 4;

[0035] The reference unit 2 includes a first feedback loop and a second feedback loop; the first feedback loop and the second feedback loop are connected between the node in the reference unit 2 affected by the signal of the operational amplifier unit 4 and the node where the reference voltage is generated; the first feedback loop and the second feedback loop are used to eliminate the influence of the offset voltage generated by the operational amplifier unit 4 on the reference voltage;

[0036] The startup unit 1 is connected to the reference unit 2, and is used to start the reference unit 2;

[0037] The bias unit 3 is connected to the reference unit 2 and the operational amplifier unit 4, and is used to provide bias current and bias voltage for the reference unit 2 and the operational amplifier unit 4;

[0038] The operational amplifier unit 4 is connected to the reference unit 2, and is used to assist the reference unit 2 in generating a reference voltage.

[0039] The present invention first uses the startup unit 1 to provide a startup condition for the reference unit 2, and uses the bias unit 3 to provide a stable bias current for the reference unit 2 and the operational amplifier unit 4, thus ensuring the stability of the operation of each unit; then uses the operational amplifier unit 4 to assist the reference unit 2 in generating a reference voltage, and at the same time the reference unit 2 uses two feedback loops therein to eliminate the influence of the offset voltage generated by the amplification unit on the reference voltage; wherein the first feedback loop feeds back the offset voltage to a suitable node to enable the circuit to compensate for the offset voltage; the second feedback loop optimizes and balances the first feedback loop to ensure that the entire process of eliminating the offset voltage is more stable and efficient; the present invention fundamentally reduces the interference of the offset voltage on the reference voltage and significantly improves the accuracy and stability of the reference voltage.

[0040] Specifically, the startup unit 1 includes the eighteenth field effect transistor M18, the nineteenth field effect transistor M19, the twentieth field effect transistor M20, the twenty-first field effect transistor M21, the twenty-second field effect transistor M22, and a power supply voltage terminal; the source of the eighteenth field effect transistor M18 is connected to the source of the nineteenth field effect transistor M19 and the power supply voltage terminal, the gate of the eighteenth field effect transistor M18 is grounded, and the drain of the eighteenth field effect transistor M18 is connected to the gate of the twentieth field effect transistor M20 and the drain of the twenty-first field effect transistor M21; the gate of the nineteenth field effect transistor M19 is connected to the drain of the twentieth field effect transistor M20 and the reference unit 2, and the drain of the nineteenth field effect transistor M19 is connected to the drain of the twenty-second field effect transistor M22, the gate of the twenty-second field effect transistor M22, and the gate of the twenty-first field effect transistor M21; the sources of the twentieth field effect transistor M20, the twenty-first field effect transistor M21, and the twenty-second field effect transistor M22 are all grounded.

[0041] The working logic of the startup unit 1 is as follows: At the moment when the circuit is powered on, the gate potential of the eighteenth field effect transistor M18 is pulled down to the ground potential, causing the eighteenth field effect transistor M18 to conduct. Since the source of the eighteenth field effect transistor M18 is connected to the source of the nineteenth field effect transistor M19, after the eighteenth field effect transistor M18 conducts, the potential of its drain decreases, thereby causing the gate potential of the twentieth field effect transistor M20 to decrease, and the twentieth field effect transistor M20 conducts accordingly; at this time, based on the current mirror principle, current is injected from the power supply through the nineteenth field effect transistor M19, the first field effect transistor M1, and the second field effect transistor M2 into the cross-coupled first transistors Q1 - Q4 in a large amount, thereby quickly activating the bandgap reference core composed of the first transistors Q1 - Q4, enabling it to start generating the initial signal of the reference voltage, and prompting the reference unit 2 to gradually approach the stable working state; when reaching the stable working state, the twenty-first field effect transistor M21 plays a key role. Since the drain of the twenty-first field effect transistor M21 is connected to the gate of the twentieth field effect transistor M20, and the source of the twenty-first field effect transistor M21 is grounded, after the twenty-first field effect transistor M21 conducts, it pulls the gate of the twentieth field effect transistor M20 to the ground potential, causing the twentieth field effect transistor M20 to cut off, thereby separating the startup unit 1 from the reference unit 2, avoiding additional interference from the startup unit 1 to the reference unit 2 after the reference unit 2 works stably, and ensuring the stability of the operation of the reference unit 2.

[0042] Specifically, the reference unit 2 includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; the source of the first field-effect transistor M1 is connected to the sources of the second field-effect transistor M2, the third field-effect transistor M3, and the nineteenth field-effect transistor M19; the gate of the first field-effect transistor M1 is connected to the gates of the second field-effect transistor M2, the third field-effect transistor M3, the nineteenth field-effect transistor M19, and the bias unit 3; the drain of the first field-effect transistor M1 is connected to the first end of the first resistor R1 and the operational amplifier unit 4, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and a first feedback loop is provided between the second end of the first resistor R1 and the drain of the third field-effect transistor M3; the second end of the second resistor R2 is connected to the emitter of the third transistor Q3; the drain of the second field-effect transistor M2 is connected to the first end of the third resistor R3 and the operational amplifier unit 4, the second end of the third resistor R3 is connected to the emitter of the fourth transistor Q4, and a second feedback loop is provided between the second end of the third resistor R3 and the drain of the third field-effect transistor M3; the drain of the third field-effect transistor M3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded; the base of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and the emitter of the second transistor Q2, the gate of the fourth transistor Q4 is connected to the collector of the third transistor Q3 and the emitter of the first transistor Q1, the gates of the first transistor Q1 and the second transistor Q2 are connected and grounded, and the collectors of the first transistor Q1 and the second transistor Q2 are grounded.

[0043] Specifically, the first feedback loop includes a first feedback resistor RF1, and the second feedback loop includes a second feedback resistor RF2; the first end of the first feedback resistor RF1 is connected to the second end of the first resistor R1, and the second end of the first feedback resistor RF1 is connected to the drain of the third field-effect transistor M3; the first end of the second feedback resistor RF2 is connected to the second end of the third resistor R3, and the second end of the second feedback resistor RF2 is connected to the drain of the third field-effect transistor M3; the resistance values of the first feedback resistor RF1 and the second feedback resistor RF2 are equal.

[0044] Specifically, the channel width-to-length ratios of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are the same.

[0045] The working logic of the reference unit 2 is as follows: The first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 form a current mirror structure. Their sources are connected together and their gates are connected together, which makes the currents equal when their channel width-to-length ratios are equal, providing a stable current source for the generation of the reference voltage. The first transistor Q1 and the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 respectively form transistor pairs, and the four transistors are cross-coupled to form a differential amplifier structure.

[0046] The first feedback loop where the first feedback resistor RF1 is located is connected between the second end of the first resistor R1 and the drain of the third field-effect transistor M3. It feedback-couples the offset voltage VOS of the operational amplifier to the non-inverting input terminal. When there is an offset voltage, the current and voltage relationship in the circuit can be adjusted through this feedback loop, thereby reducing the influence of the offset voltage on the reference voltage. The second feedback loop where the second feedback resistor RF2 is located is connected between the second end of the third resistor R3 and the drain of the third field-effect transistor M3. It is used to balance the current loss of the first feedback loop. Since the existence of the first feedback loop may have a certain impact on the current distribution in the circuit, the second feedback loop can compensate for this impact, ensure the current balance of the entire circuit, and further suppress the influence of the offset voltage on the output accuracy.

[0047] Refer to Figure 2 and Figure 3 , Figure 2 The operational amplifier OP in Figure 3 is equivalent to the op-amp unit 4 in Figure 3 . The non-inverting input terminal of the OP operational amplifier is equivalent to Figure 3 VIN+ in

[0048] Let RF1 = RF2 = RF. The currents flowing through the feedback loops RF1 and RF2 can be obtained as follows:

[0049]

[0050] In Equation (1), V A’ is Figure 2 the voltage at point A' in RF1 ; RF is the resistance value of the feedback resistor; I RF2 and I

[0051] Because the channel width-to-length ratios of the field-effect transistors M1 to M3 are equal, it can be obtained that:

[0052]

[0053] In Equation (2), VBE is the base-emitter voltage of the transistor; I1, I2, and I3 are the currents in the branches where the drains of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are located, respectively;

[0054] According to Equation (1) and Equation (2), the magnitude I of the current in the current branch where the fourth resistor R4 is located can be obtained R4 as:

[0055]

[0056] Therefore, the final expression of Vref is:

[0057]

[0058] In Equation (4), N is the transistor characteristic parameter, and Equation (4) gives the relationship between the reference voltage Vref and the resistor and transistor parameters in the circuit;

[0059] Taking the derivative of Equation (4) with respect to temperature T, we obtain:

[0060]

[0061] In Equation (5), is the rate of change of the transistor base-emitter voltage with temperature, and the thermal voltage coefficient

[0062] It can be seen from Equation (5) that by reasonably setting and the value of parameter N, the temperature coefficient of the reference voltage Vref can be optimized to be close to zero, so as to obtain an output voltage that is approximately independent of temperature;

[0063] Through the above current mirror structure, the temperature characteristics of the transistor, and the regulation of the feedback loop, the reference voltage Vref is finally formed across the fourth resistor R4. The reference voltage Vref is proportional to the current I3 through the fourth resistor R4, that is, Vref = I3 × R4, and I3 is jointly affected by the current mirror, transistor, and feedback loop described above, so that Vref can overcome the influence of temperature change and offset voltage to a certain extent and remain relatively stable.

[0064] Specifically, the bias unit 3 includes a fourth field effect transistor M4, a sixth field effect transistor M6, a fifteenth field effect transistor M15, and a sixteenth field effect transistor M16; the source of the fourth field effect transistor M4 is connected to the source of the third field effect transistor M3 and the source of the sixteenth field effect transistor M16, the gate of the fourth field effect transistor M4 is connected to the gate of the third field effect transistor M3 and the drain of the sixteenth field effect transistor M16, and the drain of the fourth field effect transistor M4 is connected to the drain of the sixth field effect transistor M6, the gate of the sixth field effect transistor M6, the gate of the fifteenth field effect transistor M15, and the operational amplifier unit 4; the source of the sixth field effect transistor M6 is grounded; the gate of the sixteenth field effect transistor M16 is connected to the operational amplifier unit 4, the drain of the sixteenth field effect transistor M16 is connected to the drain of the fifteenth field effect transistor M15, and the source of the fifteenth field effect transistor M15 is grounded.

[0065] The fourth field effect transistor M4 and the sixth field effect transistor M6 cooperate to generate a bias current. When the circuit is powered on, the fourth field effect transistor M4 and the sixth field effect transistor M6 form a current path; since the source of the sixth field effect transistor M6 is grounded, the drain current of the fourth field effect transistor M4 will flow through the sixth field effect transistor M6. The gate of the sixth field effect transistor M6 is connected to its drain, and this connection mode makes the sixth field effect transistor M6 operate in the saturation region. By reasonably selecting the sizes of the fourth field effect transistor M4 and the sixth field effect transistor M6, a stable current value can be determined, and this current is the bias current.

[0066] Specifically, the bias unit 3 further includes a seventeenth field effect transistor M17 and a compensation resistor Rc; the drain of the seventeenth field effect transistor M17 is connected to its source and the drain of the sixteenth field effect transistor M16, the gate of the seventeenth field effect transistor M17 is connected to the first end of the compensation resistor Rc, and the second end of the compensation resistor Rc is connected to the gate of the sixteenth field effect transistor M16.

[0067] The drain of the seventeenth field effect transistor M17 is connected to its source and the drain of the sixteenth field effect transistor M16, and this connection mode makes the seventeenth field effect transistor M17 equivalent to an adjustable element connected to the circuit and used as a compensation capacitor for the operational amplifier; the compensation resistor Rc is connected between the gate of the seventeenth field effect transistor M17 and the gate of the sixteenth field effect transistor M16; when the current or voltage in the circuit changes, the compensation resistor Rc will generate a voltage division, and this voltage division will be fed back to the gate of the seventeenth field effect transistor M17, thereby changing the conduction degree of the seventeenth field effect transistor M17; when the load of the operational amplifier unit 4 changes or is affected by external interference, the bias current may fluctuate. At this time, the adjustment structure composed of the seventeenth field effect transistor M17 and the compensation resistor Rc will automatically adjust the bias current according to the feedback signal to adapt to the working requirements of the operational amplifier unit 4.

[0068] Specifically, the operational amplifier unit 4 includes a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, a fourteenth field-effect transistor M14, and a fifteenth field-effect transistor M15. The source of the twelfth field-effect transistor M12 is connected to the sources of the thirteenth field-effect transistor M13, the fourteenth field-effect transistor M14, and the fifteenth field-effect transistor M15. The gate of the twelfth field-effect transistor M12 is connected to the gate of the thirteenth field-effect transistor M13. The gate of the fourteenth field-effect transistor M14 is connected to the gate of the fifteenth field-effect transistor M15. The drain of the twelfth field-effect transistor M12 is connected to the drain of the seventh field-effect transistor M7. The drain of the thirteenth field-effect transistor M13 is connected to the drain of the tenth field-effect transistor M10. The drain of the fourteenth field-effect transistor M14 is connected to the drain of the eleventh field-effect transistor M11. The drain of the fifteenth field-effect transistor M15 is connected to the drain of the eighth field-effect transistor M8. The gate of the tenth field-effect transistor M10 is connected to the drain of the first field-effect transistor M1. The source of the tenth field-effect transistor M10 is connected to the sources of the eleventh field-effect transistor M11 and the drain of the ninth field-effect transistor M9. The gate of the eleventh field-effect transistor M11 is connected to the drain of the second field-effect transistor M2. The gate of the ninth field-effect transistor M9 is connected to the gate of the fifteenth field-effect transistor M15. The source of the ninth field-effect transistor M9 is connected to the gates of the seventh field-effect transistor M7 and the eighth field-effect transistor M8. The sources of the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are grounded.

[0069] The tenth field-effect transistor M10 and the eleventh field-effect transistor M11 serve as differential input transistors. M10 is the negative input terminal VIN-, and M11 is the positive input terminal VIN+. The gates of the tenth field-effect transistor M10 and the eleventh field-effect transistor M11 are respectively connected to the drains of the first field-effect transistor M1 and the second field-effect transistor M2 in the reference unit 2, receive the input signals from the reference unit 2, and convert the input signals into differential signals. This differential input method can effectively suppress the interference of common-mode signals and improve the ability to distinguish weak signals. The ninth field-effect transistor M9 acts as a current source, providing a stable bias current for the differential input transistors to ensure that the differential input transistors operate in a suitable region.

[0070] The twelfth field effect transistor M12, the thirteenth field effect transistor M13, the fourteenth field effect transistor M14, and the fifteenth field effect transistor M15 form an amplification stage. The twelfth field effect transistor M12 and the thirteenth field effect transistor M13, and the fourteenth field effect transistor M14 and the fifteenth field effect transistor M15 are paired respectively, and their gates are connected pairwise. By reasonably setting parameters such as the width-to-length ratio of these field effect transistors, further amplification of the differential signal is achieved;

[0071] The output terminal VOUT of the operational amplifier unit is arranged between the drain of M15 and the drain of M8. It is connected to the gates of the field effect transistors M1 - M4 in the reference unit through a compensation capacitor formed by M17 and RC, forming a negative feedback loop; when the reference voltage fluctuates, the fluctuation signal will be fed back to the input of the operational amplifier unit. After being amplified and processed by the operational amplifier unit, it is then fed back to the reference unit to adjust the gate potential of the relevant field effect transistors, thereby adjusting the reference voltage to make it tend to be stable.

[0072] An embodiment of the second aspect of the present invention provides a PCB board, including the high-precision reference circuit described in any one of the above.

[0073] An embodiment of the third aspect of the present invention provides a chip, including the high-precision reference circuit described in any one of the above.

[0074] The above has specifically described the preferred embodiments of the present invention, but the present disclosure is not limited to the described embodiments. Those skilled in the art can also make various equivalent variations or substitutions without departing from the spirit of the present invention. These equivalent variations or substitutions are all included within the scope defined by the claims of the present disclosure.

Claims

1. A high-precision reference circuit, characterized in that: It includes a startup unit, a reference unit, a bias unit, and an operational amplifier unit; The reference unit includes a first feedback loop and a second feedback loop; the first feedback loop and the second feedback loop are connected between a node in the reference unit affected by the signal of the operational amplifier unit and a node where the reference voltage is generated; the first feedback loop and the second feedback loop are used to eliminate the influence of the offset voltage generated by the operational amplifier unit on the reference voltage; The startup unit is connected to the reference unit and is used to start the reference unit; The bias unit is connected to the reference unit and the operational amplifier unit and is used to provide a bias current and a bias voltage for the reference unit and the operational amplifier unit; The operational amplifier unit is connected to the reference unit and is used to assist the reference unit in generating a reference voltage.

2. The high-precision reference circuit according to claim 1, wherein: The startup unit includes an eighteenth field-effect transistor M18, a nineteenth field-effect transistor M19, a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a twenty-second field-effect transistor M22, and a supply voltage terminal; the source of the eighteenth field-effect transistor M18 is connected to the source of the nineteenth field-effect transistor M19 and the supply voltage terminal, the gate of the eighteenth field-effect transistor M18 is grounded, and the drain of the eighteenth field-effect transistor M18 is connected to the gate of the twentieth field-effect transistor M20 and the drain of the twenty-first field-effect transistor M21; the gate of the nineteenth field-effect transistor M19 is connected to the drain of the twentieth field-effect transistor M20 and the reference unit, and the drain of the nineteenth field-effect transistor M19 is connected to the drain of the twenty-second field-effect transistor M22, the gate of the twenty-second field-effect transistor M22, and the gate of the twenty-first field-effect transistor M21; the sources of the twentieth field-effect transistor M20, the twenty-first field-effect transistor M21, and the twenty-second field-effect transistor M22 are all grounded.

3. The high-precision reference circuit according to claim 2, characterized in that: The reference unit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; the source of the first field-effect transistor M1 is connected to the sources of the second field-effect transistor M2, the third field-effect transistor M3, and the nineteenth field-effect transistor M19; the gate of the first field-effect transistor M1 is connected to the gates of the second field-effect transistor M2, the third field-effect transistor M3, the nineteenth field-effect transistor M19, and the bias unit; the drain of the first field-effect transistor M1 is connected to the first end of the first resistor R1 and the operational amplifier unit, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and a first feedback loop is provided between the second end of the first resistor R1 and the drain of the third field-effect transistor M3; the second end of the second resistor R2 is connected to the emitter of the third transistor Q3; the drain of the second field-effect transistor M2 is connected to the first end of the third resistor R3 and the operational amplifier unit, the second end of the third resistor R3 is connected to the emitter of the fourth transistor Q4, and a second feedback loop is provided between the second end of the third resistor R3 and the drain of the third field-effect transistor M3; the drain of the third field-effect transistor M3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded; the base of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and the emitter of the second transistor Q2, the gate of the fourth transistor Q4 is connected to the collector of the third transistor Q3 and the emitter of the first transistor Q1, the gates of the first transistor Q1 and the second transistor Q2 are grounded, and the collectors of the first transistor Q1 and the second transistor Q2 are grounded.

4. The high-precision reference circuit according to claim 3, wherein: The first feedback loop includes a first feedback resistor RF1, and the second feedback loop includes a second feedback resistor RF2; the first end of the first feedback resistor RF1 is connected to the second end of the first resistor R1, and the second end of the first feedback resistor RF1 is connected to the drain of the third field-effect transistor M3; the first end of the second feedback resistor RF2 is connected to the second end of the third resistor R3, and the second end of the second feedback resistor RF2 is connected to the drain of the third field-effect transistor M3; the resistance values of the first feedback resistor RF1 and the second feedback resistor RF2 are equal.

5. The high-precision reference circuit according to claim 3, wherein: The channel width-to-length ratios of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are the same.

6. The high-precision reference circuit according to claim 3, wherein: The bias unit includes a fourth field effect transistor M4, a sixth field effect transistor M6, a fifteenth field effect transistor M15, and a sixteenth field effect transistor M16; the source of the fourth field effect transistor M4 is connected to the source of the third field effect transistor M3 and the source of the sixteenth field effect transistor M16, the gate of the fourth field effect transistor M4 is connected to the gate of the third field effect transistor M3 and the drain of the sixteenth field effect transistor M16, and the drain of the fourth field effect transistor M4 is connected to the drain of the sixth field effect transistor M6, the gate of the sixth field effect transistor M6, the gate of the fifteenth field effect transistor M15, and the operational amplifier unit; the source of the sixth field effect transistor M6 is grounded; the gate of the sixteenth field effect transistor M16 is connected to the operational amplifier unit, the drain of the sixteenth field effect transistor M16 is connected to the drain of the fifteenth field effect transistor M15, and the source of the fifteenth field effect transistor M15 is grounded.

7. The high-precision reference circuit according to claim 3, wherein: The bias unit further includes a seventeenth field effect transistor M17 and a compensation resistor Rc; the drain of the seventeenth field effect transistor M17 is connected to its source and the drain of the sixteenth field effect transistor M16, the gate of the seventeenth field effect transistor M17 is connected to the first end of the compensation resistor Rc, and the second end of the compensation resistor Rc is connected to the gate of the sixteenth field effect transistor M16.

8. The high-precision reference circuit according to claim 4, characterized in that: The operational amplifier unit includes a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, and a fifteenth field effect transistor M15; the source of the twelfth field effect transistor M12 is connected to the sources of the thirteenth field effect transistor M13, the fourteenth field effect transistor M14, and the fifteenth field effect transistor M15, the gate of the twelfth field effect transistor M12 is connected to the gate of the thirteenth field effect transistor M13, and the gate of the fourteenth field effect transistor M14 is connected to the gate of the fifteenth field effect transistor M15; the drain of the twelfth field effect transistor M12 is connected to the drain of the seventh field effect transistor M7, the drain of the thirteenth field effect transistor M13 is connected to the drain of the tenth field effect transistor M10, the drain of the fourteenth field effect transistor M14 is connected to the drain of the eleventh field effect transistor M11, and the drain of the fifteenth field effect transistor M15 is connected to the drain of the eighth field effect transistor M8; the gate of the tenth field effect transistor M10 is connected to the drain of the first field effect transistor M1, the source of the tenth field effect transistor M10 is connected to the sources of the eleventh field effect transistor M11 and the drain of the ninth field effect transistor M9, and the gate of the eleventh field effect transistor M11 is connected to the drain of the second field effect transistor M2; the gate of the ninth field effect transistor M9 is connected to the gate of the fifteenth field effect transistor M15, the source of the ninth field effect transistor M9 is connected to the gates of the seventh field effect transistor M7 and the eighth field effect transistor M8, and the sources of the seventh field effect transistor M7 and the eighth field effect transistor M8 are grounded.

9. A PCB board, characterized in that, Comprising the high-precision reference circuit according to any one of claims 1 to 8.

10. A chip, characterized in that, Comprising the high-precision reference circuit according to any one of claims 1 to 8.

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