A bandgap reference circuit with low temperature drift and high power supply noise rejection

Abstract

The low-temperature drift high-power noise suppression band gap reference circuit disclosed by the application comprises a starting circuit, a pre-stabilization circuit, a curvature compensation circuit, a core band gap reference circuit and a low-pass filter circuit, the starting circuit is used for power-on starting of the pre-stabilization circuit and the core band gap reference circuit, the pre-stabilization circuit is used for filtering a part of power ripples in advance and supplying power for the core band gap reference circuit, the curvature compensation circuit and the low-pass filter circuit, the curvature compensation circuit is used for injecting and extracting exponential currents respectively in the high-temperature section and the low-temperature section to complete temperature curvature compensation in different temperature sections, and the low-pass filter circuit is used for completing power ripple suppression in the high-frequency section. The low-temperature drift high-power noise suppression band gap reference circuit realizes high-order curvature compensation in a wide temperature range of high and low temperatures, so that the temperature drift is effectively reduced in the whole temperature range, thereby reducing the power consumption of the circuit and significantly improving the precision of the voltage reference. And the PSR of the circuit is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of power supply technology, and specifically relates to a bandgap reference circuit for suppressing power supply noise at low temperature drift. Background Technology

[0002] As an indispensable module in analog integrated circuits, the bandgap voltage reference is responsible for providing a stable reference voltage that is unaffected by process-voltage-temperature (PVT) variations to other circuit systems. It is essential in structures such as ADCs, LDOs, and DC-DC converters. Therefore, the voltage accuracy and power supply ripple suppression capability of the bandgap reference are crucial.

[0003] The traditional bandgap reference circuits proposed by previous researchers are first-order temperature-compensated references. Because the temperature curve of ΔVBE includes nonlinear components, the temperature coefficient of a first-order temperature-compensated reference is generally limited to 20 to 100 ppm / ℃. Therefore, many higher-order compensation methods have been proposed, such as the higher-order temperature compensation method proposed by Allen et al., which can achieve a smaller temperature coefficient, but still cannot meet the current demands for high performance and high precision. Furthermore, there are still significant shortcomings in power supply ripple suppression. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a bandgap reference circuit that combines high-order curvature compensation and high power supply ripple suppression with low temperature drift and high power supply noise suppression.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: a bandgap reference circuit with low temperature drift and high power supply noise suppression, comprising a startup circuit, a pre-regulator circuit, a curvature compensation circuit, a core bandgap reference circuit, and a low-pass filter circuit. One output terminal of the startup circuit is connected to the input terminal of the pre-regulator circuit, and the other output terminal of the startup circuit is connected to one input terminal of the core bandgap reference circuit. One output terminal of the pre-regulator circuit is connected to the input terminal of the curvature compensation circuit, and the other output terminal of the pre-regulator circuit is connected to another input terminal of the core bandgap reference circuit. The output terminal of the curvature compensation circuit is connected to yet another input terminal of the core bandgap reference circuit, and the output terminal of the core bandgap reference circuit is connected to the input terminal of the low-pass filter circuit. The output of the core bandgap reference circuit is the reference voltage, and the output of the low-pass filter circuit is the reference voltage after filtering out high-frequency power supply ripple.

[0006] The startup circuit is used for power-on startup of the pre-regulator circuit and the core bandgap reference circuit. The pre-regulator circuit is used to pre-filter out a portion of the power supply ripple and supply power to the core bandgap reference circuit, curvature compensation circuit and low-pass filter circuit. The curvature compensation circuit is used to inject and extract exponential current in the high temperature range and the low temperature range respectively to complete temperature curvature compensation in different temperature ranges. The low-pass filter circuit is used to complete power supply ripple suppression in the high frequency range.

[0007] In one specific implementation scheme:

[0008] The core bandgap reference circuit includes PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, MN3, MN4, PNP transistors Q1, Q2, and resistors R0, R1, R2.

[0009] The curvature compensation circuit includes PMOS transistors MP5 and MC3, resistors R4 and R3, and NMOS transistors MC1 and MC2.

[0010] The pre-regulator circuit includes PMOS transistors MP8, MP9, MP10, and MP11, NMOS transistors MN5, MN6, MN7, and MN8, and capacitor C2.

[0011] The low-pass filter circuit includes PMOS transistors MR1, MR2, MR3, MR4, and MR5, and capacitor C3;

[0012] The sources of MP3 and MP4 are connected to the drain of MP11, respectively. The gates of MP3 and MP4 are connected and then connected to the gate of MP8 and the drain of MP1, respectively. The gate of MP1 is connected to the gate of MP2. The source of MP1 is connected to the drain of MP3, the source of MP2 is connected to the drain of MP4, and the drain of MP2 is connected to the gate of MN4. The upper end of R1 is connected to the gate of MP3, and the lower end of R1 is connected to the gate of MP1, forming a self-biased cascode current mirror structure. The gates of MN1 and MN2... After the gate is connected, it is connected to the lower end of R2. The source of MN1 is connected to the upper end of R0. The source of MN2 is connected to the emitter of Q2. The drain of MN1 is connected to the source of MN3. The drain of MN2 is connected to the source of MN4. The gates of MN3 and MN4 are connected and then connected to the upper end of R2. The drain of MN3 is connected to the lower end of R1. The drain of MN4 is connected to the lower end of R2, forming a self-biased cascode current mirror structure. The lower end of R0 is connected to the emitter of Q1. The bases and collectors of Q1 and Q2 are connected to ground respectively.

[0013] The source and substrate of MP10 and the source and substrate of MP11 are connected to an external power supply. The gate and drain of MP10 are shorted and connected to the gate of MP11, forming a current mirror. The source and substrate of MN5, the source and substrate of MN6, and the source and substrate of MN7 are connected to ground. The gate and drain of MN5 are shorted and connected to the gates of MN6 and MN7, respectively, forming a current mirror. The drain of MP8 is connected to the drain of MN5, and the drain of MP9 is connected to the drain of MN6. The source of MP8, the source of MP9, and the drain of MN8 are connected to the drain of MP11, and the drain of MN7 is connected to the drain of MP10. The source of MN8 and the lower plate of C2 are connected to ground. The gate of MN8 and the upper plate of C2 are connected to the drain of MN6. The gate of MP9 is connected to the output voltage V. BG Connected;

[0014] The source of MP5 is connected to the drain of MP11. The gate of MP5 is connected to the gate of MP3 and the upper end of R1. The drain of MP5 is connected to the upper end of R4 and the gate of MC3. The source of MC3 is connected to the drain of MP11. The lower end of R4 is connected to the gate of MC1, the gate of MC2, and the upper end of R3. The lower end of R3 is connected to ground. The drain of MC1 is connected to the upper end of R0. The drain of MC2 is connected to the emitter of Q2. The sources of MC1 and MC2 are connected to ground.

[0015] The gates of MR1, MR2, MR3, MR4, and MR5 are connected to ground. The source of MR1 is connected to the drain of MC3. The drain of MR1 is connected to the source of MR2. The drain of MR2 is connected to the source of MR3. The drain of MR3 is connected to the source of MR4. The drain of MR4 is connected to the source of MR5. The drain of MR5 is connected to the upper plate of C3. The lower plate of C3 is connected to ground.

[0016] The gate of MP5 is connected to the gate of PMOS transistor MP6, the source of MP6 is connected to the drain of MP11, the drain of MP6 is connected to the source of PMOS transistor MP7, the gate of MP7 is connected to the gate of MP2, the drain of MP7 is connected to the upper end of resistor R5, the lower end of R5 is connected to the emitter of PNP transistor Q3, and the base and collector of Q3 are connected to ground respectively.

[0017] Specifically, the startup circuit includes a first startup circuit and a second startup circuit. The first startup circuit includes NMOS transistors MS1 and MS2, a PMOS transistor MS3, and a capacitor C1. The second startup circuit includes NMOS transistors MS4, MS6, and MS7, and PMOS transistors MS5, MS8, and MS9.

[0018] The source and substrate of MS3 are connected to an external power supply. The gate and drain of MS3 are shorted and connected to the upper plate of C1, the drain of MS1, and the gate of MS2, respectively. The gate of MS1 is connected to the drain of MP9, and the drain of MS2 is connected to the drain of MP10. The lower plate of C1, the source of MS1, and the source of MS2 are connected to ground.

[0019] The drain of MS4 is connected to the drain of MS5 and the gate of MS6. The gate of MS4 is shorted to the gate of MS7 and connected to the drain of MS7 and the drain of MS8. The source of MS5 is connected to the source of MP11. The drain and gate of MS5 are shorted. The drain of MS6 is connected to the gate of MS8 and the gate of MP3. The source of MS8 is connected to the drain of MS9. The source of MS9 is connected to the drain of MP11. The gate of MS9 is connected to the gate of MP3. The sources of MS6, MS4, and MS7 are connected to ground.

[0020] Compared with existing technologies, the present invention has the following advantages: The low-temperature drift and high power supply noise suppression bandgap reference circuit of the present invention adopts a self-biased cascode current mirror structure as the core bandgap reference circuit, and utilizes the subthreshold current exponential characteristics of MOSFETs to achieve high-order curvature compensation over a wide temperature range at both high and low temperatures, effectively reducing temperature drift across the entire temperature range, thereby reducing circuit power consumption and significantly improving the accuracy of the voltage reference. Furthermore, the pre-regulator circuit and low-pass filter circuit suppress power supply ripple in the low-to-mid frequency band and high-frequency band respectively, resulting in a significant improvement in the PSR of the circuit. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the bandgap reference circuit for low-temperature drift and high power supply noise suppression according to the present invention.

[0022] Figure 2 This is a complete circuit diagram of the bandgap reference circuit for low-temperature drift and high power supply noise suppression in the embodiment;

[0023] Figure 3 This is a small-signal equivalent model diagram of the pre-regulator circuit in the embodiment;

[0024] Figure 4 This is a simulation diagram of the temperature characteristics of the bandgap reference circuit for low-temperature drift and high power supply noise suppression in the embodiment.

[0025] Figure 5 This is a simulation diagram illustrating the relationship between the output voltage PSR and frequency of the bandgap reference circuit with low temperature drift and high power supply noise suppression in the embodiment.

[0026] Figure 6 This is a simulation diagram of the startup process of the startup circuit in the embodiment. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0028] The bandgap reference circuit with low temperature drift and high power supply noise suppression in the embodiment, such as Figure 1 As shown, the circuit includes a startup circuit 100, a pre-regulator circuit 200, a curvature compensation circuit 300, a core bandgap reference circuit 400, and a low-pass filter circuit 500. One output terminal of the startup circuit 100 is connected to the input terminal of the pre-regulator circuit 200, and the other output terminal of the startup circuit 100 is connected to one input terminal of the core bandgap reference circuit 400. One output terminal of the pre-regulator circuit 200 is connected to the input terminal of the curvature compensation circuit 300, and the other output terminal of the pre-regulator circuit 200 is connected to another input terminal of the core bandgap reference circuit 400. The output terminal of the curvature compensation circuit 300 is connected to yet another input terminal of the core bandgap reference circuit 400, and the output terminal of the core bandgap reference circuit 400 is connected to the input terminal of the low-pass filter circuit 500. The output of the core bandgap reference circuit 400 is the reference voltage, and the output of the low-pass filter circuit 500 is the reference voltage after filtering out high-frequency power supply ripple.

[0029] The startup circuit 100 is used to power on the pre-regulator circuit 200 and the core bandgap reference circuit 400. The pre-regulator circuit 200 is used to pre-filter out a portion of the power supply ripple and supply power to the core bandgap reference circuit 400, the curvature compensation circuit 300, and the low-pass filter circuit 500. The curvature compensation circuit 300 is used to inject and extract exponential current in the high-temperature and low-temperature ranges respectively to complete temperature curvature compensation in different temperature ranges. The low-pass filter circuit 500 is used to complete power supply ripple suppression in the high-frequency range.

[0030] The startup circuit 100 includes a first startup circuit and a second startup circuit. The first startup circuit includes NMOS transistors MS1 and MS2, PMOS transistor MS3, and capacitor C1. The second startup circuit includes NMOS transistors MS4, MS6, and MS7, and PMOS transistors MS5, MS8, and MS9. The core bandgap reference circuit 400 includes PMOS transistors MP1, MP2, MP3, and MP4, NMOS transistors MN1, MN2, MN3, and MN4, PNP transistors Q1 and Q2, and resistors R0, R1, and R2. The curvature compensation circuit 300 includes PMOS transistors MP5 and MC3, resistors R4 and R3, and NMOS transistors MC1 and MC2. The pre-regulator circuit 200 includes PMOS transistors MP8, MP9, MP10, and MP11, NMOS transistors MN5, MN6, MN7, and MN8, and capacitor C2. The low-pass filter circuit 500 includes PMOS transistors MR1, MR2, MR3, MR4, and MR5, and capacitor C3.

[0031] The sources of MP3 and MP4 are connected to the drain of MP11, respectively. The gates of MP3 and MP4 are connected and then connected to the gate of MP8 and the drain of MP1, respectively. The gate of MP1 is connected to the gate of MP2. The source of MP1 is connected to the drain of MP3, the source of MP2 is connected to the drain of MP4, and the drain of MP2 is connected to the gate of MN4. The upper end of R1 is connected to the gate of MP3, and the lower end of R1 is connected to the gate of MP1, forming a self-biased cascode current mirror structure. The gates of MN1 and MN2... After the gate is connected, it is connected to the lower end of R2. The source of MN1 is connected to the upper end of R0. The source of MN2 is connected to the emitter of Q2. The drain of MN1 is connected to the source of MN3. The drain of MN2 is connected to the source of MN4. The gates of MN3 and MN4 are connected and then connected to the upper end of R2. The drain of MN3 is connected to the lower end of R1. The drain of MN4 is connected to the lower end of R2, forming a self-biased cascode current mirror structure. The lower end of R0 is connected to the emitter of Q1. The bases and collectors of Q1 and Q2 are connected to ground respectively.

[0032] The source and substrate of MP10 and the source and substrate of MP11 are connected to an external power supply. The gate and drain of MP10 are shorted and connected to the gate of MP11, forming a current mirror. The source and substrate of MN5, the source and substrate of MN6, and the source and substrate of MN7 are connected to ground. The gate and drain of MN5 are shorted and connected to the gates of MN6 and MN7, respectively, forming a current mirror. The drain of MP8 is connected to the drain of MN5, and the drain of MP9 is connected to the drain of MN6. The source of MP8, the source of MP9, and the drain of MN8 are connected to the drain of MP11. MP8 is used to introduce the current generated in the core bandgap reference circuit 400. The drain of MN7 is connected to the drain of MP10. The source of MN8 and the lower plate of C2 are connected to ground. The gate of MN8 and the upper plate of C2 are connected to the drain of MN6. The gate of MP9 is connected to the output voltage V. BG Connected.

[0033] The source of MP5 is connected to the drain of MP11. The gate of MP5 is connected to the gate of MP3 and the upper end of R1. The drain of MP5 is connected to the upper end of R4 and the gate of MC3. The source of MC3 is connected to the drain of MP11. The lower end of R4 is connected to the gate of MC1, the gate of MC2, and the upper end of R3. The lower end of R3 is connected to ground. The drain of MC1 is connected to the upper end of R0. The drain of MC2 is connected to the emitter of Q2. The sources of MC1 and MC2 are connected to ground.

[0034] The gates of MR1, MR2, MR3, MR4, and MR5 are connected to ground. The source of MR1 is connected to the drain of MC3. The drain of MR1 is connected to the source of MR2. The drain of MR2 is connected to the source of MR3. The drain of MR3 is connected to the source of MR4. The drain of MR4 is connected to the source of MR5. The drain of MR5 is connected to the upper plate of C3. The lower plate of C3 is connected to ground.

[0035] The gate of MP5 is connected to the gate of PMOS transistor MP6, the source of MP6 is connected to the drain of MP11, the drain of MP6 is connected to the source of PMOS transistor MP7, the gate of MP7 is connected to the gate of MP2, the drain of MP7 is connected to the upper end of resistor R5, the lower end of R5 is connected to the emitter of PNP transistor Q3, and the base and collector of Q3 are connected to ground respectively.

[0036] The source and substrate of MS3 are connected to an external power supply. The gate and drain of MS3 are shorted and connected to the upper plate of C1, the drain of MS1, and the gate of MS2, respectively. The gate of MS1 is connected to the drain of MP9, and the drain of MS2 is connected to the drain of MP10. The lower plate of C1, the source of MS1, and the source of MS2 are connected to ground. The drain of MS4 is connected to the drain of MS5 and the gate of MS6, respectively. The gate of MS4 is shorted to the gate of MS7 and connected to the drain of MS7 and the drain of MS8, respectively. The source of MS5 is connected to the source of MP11. The drain and gate of MS5 are shorted. The drain of MS6 is connected to the gate of MS8 and the gate of MP3, respectively. The source of MS8 is connected to the drain of MS9, the source of MS9 is connected to the drain of MP11, and the gate of MS9 is connected to the gate of MP3. The sources of MS6, MS4, and MS7 are connected to ground, respectively.

[0037] In addition, the substrates of all NMOS transistors in this design are connected to ground, and the substrates of all PMOS transistors are connected to the source.

[0038] After the aforementioned low-temperature drift and high power supply noise suppression bandgap reference circuit is started, the pre-regulator circuit 100 turns on first to eliminate part of the power supply voltage ripple and provide current for subsequent circuits. Then, the core bandgap reference circuit 200 turns on and generates a current IPTAT proportional to the absolute temperature and a first-order temperature-compensated reference voltage V. BG Then, using IPTAT and resistors R3 and R4, a voltage V proportional to the absolute temperature is generated. PTAT As the bias voltage for the subthreshold compensation transistor in the curvature compensation circuit, it is V in the low-temperature region and the high-temperature region, respectively. BG Injecting a current that is exponentially proportional to temperature completes temperature curvature compensation for the circuit in both high-temperature and low-temperature regions. The voltage V after high-order temperature curvature compensation is then... BGA low-pass filter is used to filter out high-frequency ripple, resulting in the final output voltage V. REF .

[0039] The following describes each circuit module of the bandgap reference circuit for low-temperature drift and high power supply noise suppression of the present invention.

[0040] (1) Pre-regulator circuit

[0041] Although PSR is a parameter for small-signal response, general techniques for improving linearity can also be applied to optimize PSR performance. In short, the overall design of the reference source must consider power supply voltage variations. To achieve this, circuits typically employ cascode and / or pre-regulation techniques to reduce the impact of power supply voltage. The basic idea for improving power supply rejection (PSR) and linearity is to increase the effective impedance between the sensitive node (especially the output reference voltage) and the input power supply voltage. Power supply rejection can be equivalent to the voltage division of the impedance between the power supply voltage and ground, with the common node being the reference voltage. The effective PSR can be expressed as:

[0042]

[0043] In the formula, ΔV ref and ΔV in These represent the changes in the reference voltage and the supply voltage, respectively; z gnd and z i These represent the effective impedances from the reference voltage to the ground node and from the reference voltage to the supply voltage, respectively. Therefore, increasing the impedance from the reference voltage to the input supply voltage improves the power supply rejection performance (PSR becomes larger). Consequently, the fluctuation range of the pseudo-supply voltage after pre-regulation, used as the supply voltage of the reference source circuit, will be significantly reduced. The overall circuit's PSR can be expressed by the following formula:

[0044] PSR = PSR pre-reg ×PSR core-bgr Formula (2)

[0045] In the formula, PSR pre-reg and PSR core-bgr These represent the PSR performance of the pre-regulator circuit and the core reference source circuit, respectively.

[0046] This design employs a pre-regulated circuit structure, which addresses the small signal ripple (V) generated by the power supply voltage. dd When this happens, the voltage at the source terminals of MP10 and MP11 will change, but the gate terminal voltages of MP10 and MP11 are determined by I. DC Since it's a mirror image, the currents of MP10 and MP11 are to match I. DC Maintaining consistency will produce a simultaneously changing v at the gate. ddThis is to offset fluctuations at the source. This causes small-signal current variations i in MP11 to occur. d11 It can only be generated through channel length modulation effect, and can be written as:

[0047]

[0048] v here dd and v ref V DD and V REG Small signal ripple at the location. oMP11 This is the small-signal resistor for MP11.

[0049] At the same time, V REG The change produces a changing current i on MN8. dMN8 It can be written as:

[0050]

[0051] r here f For local feedback loop from v reg Equivalent resistance to ground.

[0052] According to Kirchhoff's current theorem, i d,MP11 =i d,MN8 +i d,MP9 +i core , where i d,MP9 This is the small signal current of MP9, which is generated by I. DC It comes from a mirror image, therefore it is not affected by v. dd The impact of fluctuations; and i core The current required for the core bandgap reference circuit is proportional to absolute temperature and hardly changes with variations in Vdd. Therefore, the i generated by the power supply voltage ripple... dMP11 The current flows entirely to MN8, therefore, according to the above two equations, we can conclude that:

[0053]

[0054]

[0055] Because r f Very small, and r oMP11 It's very big, so v reg The value is much smaller than v dd The value of r. f Given the value of , draw the small-signal equivalent model of the local feedback loop, such as Figure 3 As shown, the results are as follows:

[0056]

[0057] in,

[0058] Therefore, the equivalent resistance of the local negative feedback loop can be obtained:

[0059]

[0060] Therefore we can obtain:

[0061]

[0062] And ripple rejection ratio:

[0063] PSR≈-20lg(1+g m,MP9 ·g m,MN9 ·r o,MP9 ·r o,MP11 )Formula (10)

[0064] Since all devices operate in the saturation region, ro is much greater than gm. According to the formula for output resistance:

[0065]

[0066] It can be seen that increasing the channel length of MP11 and MP9 can further increase the PSR.

[0067] (2) Core bandgap reference circuit

[0068] The core bandgap reference circuit uses a self-biased cascode current mirror to clamp the voltages at points X and Y, thus avoiding the complex design of operational amplifiers. The current mirrors constructed from PMOS transistors have the same size ratio, ensuring equal current in both paths. Similarly, the current mirrors constructed from NMOS transistors also have the same size ratio, and the bias current flowing through both branches is equal, based on the square-law characteristic of MOS transistors operating in the saturation region:

[0069]

[0070] We can see that the VGS of the NMOS is also the same, thus achieving consistency in the potentials at points X and Y. The relationship between the VBE voltage and the bias current of the transistor is as follows:

[0071] VBE=VT*ln(IC / IS) Formula (13)

[0072] Where, the hot spot voltage VT = kT / q, k is Boltzmann's constant, q is the charge of an electron, and I S It is the saturation current, I CThis is the collector current. Since the area ratio of the PNP transistors in the two branches is 1:7, the current in both branches is the same. According to the BJT current formula, the voltage across the resistor can be calculated as follows:

[0073] ΔV BE =V BE1 -V BE2 =V T ln(I0 / I S0 )-V T ln(I0 / 7*I S0 ) = V T ln7 formula (14)

[0074] This is a voltage proportional to absolute temperature, therefore the branch current can also be determined by the resistance value and ΔV. BE Sure:

[0075] I PTAT =ΔV BE / R

[0076] All resistors involved in the circuit are of the same type, namely P-type doped polysilicon resistors without siliconization process. Since their temperature coefficient is low, they will not affect the overall circuit, so the temperature coefficient of the resistors is ignored.

[0077] The current is cloned by a current mirror, generating a PTAT voltage across resistor R5, which is related to V. BE Superimposed order, in V OUT To achieve a first-order compensated voltage:

[0078] V BG =V BE +I PTAT *R Formula (15)

[0079] But due to V BE The higher-order nonlinear components present in V BE The relationship with temperature:

[0080] V BE (T)=V g0 -BT-Cf(T) Formula (16)

[0081] By performing a Taylor expansion on it, we can see that, apart from the first-order linear CTAT voltage, V BE It will also contain a negative higher-order term, thus yielding a result such as Figure 4 As a result, higher-order curvature compensation is still needed to meet the requirements of low-temperature drift.

[0082] (3) Curvature compensation circuit

[0083] Typical first-order bandgap references are no longer sufficient to meet the needs of many high-performance systems. Therefore, higher-order references—curvature-corrected references—are required. In addition to canceling the first-order temperature component of the voltage, curvature-corrected bandgap references also need to cancel the nonlinear component of the base-emitter voltage (diode voltage) as much as possible. This structure employs… Figure 2 The curvature correction technique in this circuit utilizes the exponential characteristic of the MOSFET during subthreshold conduction to compensate for curvature in both high-temperature and low-temperature segments. The current in this branch originates from the mirror current of the core BGR's branch circuit; therefore, this current also exhibits PTAT characteristics, generating PTAT voltages across resistors R1 and R2, which are V... L =I PTAT *R1 and V H =I PTAT *(R1+R2).

[0084] As temperature increases, the gate-source voltage V of the NMOS increases. GS From V, which is much lower than NMOS TH (At this point, NMOS is off) gradually rises to near V TH This allows the NMOS transistor to operate in the subthreshold region, and the current of the MOS transistor can be obtained from the subthreshold current formula:

[0085]

[0086] Therefore, by choosing a suitable or relatively small resistor R1, the NMOS transistor can be turned on at a higher temperature, generating a subthreshold current. Furthermore, connecting the drain terminals of the two NMOS transistors to the X and Y terminals of the core BGR not only ensures the consistency of the drain voltages of the two NMOS transistors, reduces the channel length modulation effect of the MOS transistors, and reduces the mismatch between the two transistors, but also increases the current of the core BGR at high temperatures.

[0087] I = I PTAT +I HTC Formula (18)

[0088] Among them, I HTC ={0, I D =I0*exp(V GS / ξV T )

[0089] This improves the V in VREF at high temperatures. PTAT Quantity:

[0090] V BG =(I PTAT +I HTC )*R+V BE Formula (19)

[0091] This achieves curvature compensation in the high-temperature range. Similarly, the gate voltage of the PMOS is:

[0092] VGS=I PTAT *(R1+R2) Formula (20)

[0093] By choosing a larger R2, the PMOS can be made to conduct subthreshold at low temperatures and cut off at high temperatures. For example... Figure 2 As shown, connect the drain of the PMOS to V. REF In the low-temperature range, the PMOS subthreshold conduction is achieved, providing V REF Injecting low-temperature compensation current I LTC We can obtain:

[0094] V BG =(I PTAT +I LTC )*R+V BE Formula (21)

[0095] Among them, I LTC ={I D =-I S0 *exp(V BE / ξV T ), 0}

[0096] This achieves curvature compensation in the low-temperature range. The curvature compensation effect diagrams for the high and low temperature ranges are shown below. Figure 4 As shown by the solid line in the figure, the TC is significantly improved after curvature compensation, greatly enhancing the accuracy of the bandgap reference output voltage and meeting the requirements of a high-performance BGR. This compensation method is not only simple and easy to understand, but also has extremely low power consumption and almost no impact on the overall circuit's PSR.

[0097] (4) Low-pass filter circuit

[0098] Due to the parasitic capacitance in the pre-regulator circuit, which primarily suppresses low-to-medium frequency power supply voltage ripple, a low-pass filter circuit is still needed to suppress high-frequency power supply voltage ripple. The low-pass filter structure is as follows: Figure 2 As shown.

[0099] Transistors MR1-MR5 and capacitor C3 form a first-order RC low-pass filter, with MR1-MR5 acting as resistors. MOSFETs M5-M9 are designed to operate in the linear region to take advantage of their relatively large channel resistance. Using MOSFETs as capacitors also reduces layout area. The low-pass filter further improves the PSR in the mid-to-high frequency range because a pole is introduced. Due to the large channel resistance R and the relatively large capacitance of the MOSFETs, the pole is located in the mid-to-high frequency range, thus improving the PSR across the entire operating frequency range. Figure 5 This is a simulation diagram illustrating the relationship between the output voltage PSR and frequency of a bandgap reference circuit (i.e., a simulation diagram illustrating the power supply ripple suppression PSR). The overall structure of this invention can achieve a PSR of 120.6dB at low frequencies and a PSR of approximately 70dB across the entire frequency band.

[0100] (5) Start-up circuit

[0101] Current source circuits all have an additional stable operating point, namely I. PTAT The state of zero resistance is also called the degeneracy point. In this case, a startup circuit is needed to prevent the circuit from entering this undesirable state. The startup circuit injects or draws a certain amount of current into or out of the current source circuit. This current flows into or out of a low-resistance node in the circuit; typically, the startup current is very small. The startup circuit used in this article is as follows: Figure 2 As shown.

[0102] During startup, the pre-regulator circuit's startup circuit turns on first, followed by the core BGR's startup circuit. Capacitor C is used to eliminate potential self-oscillations during startup. When the power supply voltage is applied to the circuit, the source voltage of MS3 gradually increases, while the gate voltage of MS3 remains zero. When VGS of MS3 exceeds VTH, MS3 turns on to charge C. Since the bias point of MS2 has not yet been established, the gate voltage of MS3 continues to rise, causing MS1 to turn on. After the pre-regulator circuit is fully turned on and the core BGR is operating normally, the gate bias voltage of MS2 is established, causing MS2 to turn on and pull down the gate voltage of MS3. This shuts down MS1 ​​without affecting the main circuit branch. The transient simulation results of startup are as follows: Figure 6 As shown.

[0103] The bandgap reference circuit of this invention has good temperature stability, with a temperature coefficient (TC) of 1.8ppm / ℃ in the temperature range of -25℃ to 125℃ when the input voltage is 3.3V; at the same time, the circuit also has a high PSR; the circuit implementation is simple, without the use of an operational amplifier structure, thus avoiding the influence of operational amplifier offset; the temperature coefficient of the resistor has little impact on the output, and the trimming of the reference output is also very convenient.

[0104] The bandgap reference circuit of this invention can be implemented using standard 0.18μm CMOS technology. High-order temperature curvature compensation is achieved through a simple circuit using subthreshold exponential curvature compensation. This compensation method requires a very simple circuit and can be easily implemented. Furthermore, this invention is also applicable to general trimming processes. Due to its high accuracy, good performance, low quiescent current, and low operating voltage, the reference source of this invention can be applied to many mixed-signal systems.

[0105] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A bandgap reference circuit with low temperature drift and high power supply noise suppression, characterized in that: The circuit includes a startup circuit, a pre-regulator circuit, a curvature compensation circuit, a core bandgap reference circuit, and a low-pass filter circuit. One output terminal of the startup circuit is connected to the input terminal of the pre-regulator circuit, and the other output terminal of the startup circuit is connected to one input terminal of the core bandgap reference circuit. One output terminal of the pre-regulator circuit is connected to the input terminal of the curvature compensation circuit, and the other output terminal of the pre-regulator circuit is connected to another input terminal of the core bandgap reference circuit. The output terminal of the curvature compensation circuit is connected to yet another input terminal of the core bandgap reference circuit, and the output terminal of the core bandgap reference circuit is connected to the input terminal of the low-pass filter circuit. The output of the core bandgap reference circuit is the reference voltage, and the output of the low-pass filter circuit is the reference voltage after filtering out high-frequency power supply ripple. The startup circuit is used for power-on startup of the pre-regulator circuit and the core bandgap reference circuit. The pre-regulator circuit is used to pre-filter out a portion of the power supply ripple and supply power to the core bandgap reference circuit, curvature compensation circuit and low-pass filter circuit. The curvature compensation circuit is used to inject and extract exponential current in the high temperature range and the low temperature range respectively to complete temperature curvature compensation in different temperature ranges. The low-pass filter circuit is used to complete power supply ripple suppression in the high frequency range. The core bandgap reference circuit includes PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, MN3, MN4, PNP transistors Q1, Q2, and resistors R0, R1, R2. The curvature compensation circuit includes PMOS transistors MP5 and MC3, resistors R4 and R3, and NMOS transistors MC1 and MC2. The pre-regulator circuit includes PMOS transistors MP8, MP9, MP10, and MP11, NMOS transistors MN5, MN6, MN7, and MN8, and capacitor C2. The low-pass filter circuit includes PMOS transistors MR1, MR2, MR3, MR4, and MR5, and capacitor C3; The source of MP3 and the source of MP4 are connected to the drain of MP11, respectively. The gate of MP3 and the gate of MP4 are connected and then connected to the gate of MP8 and the drain of MP1, respectively. The gate of MP1 is connected to the gate of MP2. The source of MP1 is connected to the drain of MP3. The source of MP2 is connected to the drain of MP4. The drain of MP2 is connected to the gate of MN4. The upper end of R1 is connected to the gate of MP3, and the lower end of R1 is connected to the gate of MP1. The gate of MN1 and the gate of MN2... After the gate is connected, it is connected to the lower end of R2. The source of MN1 is connected to the upper end of R0. The source of MN2 is connected to the emitter of Q2. The drain of MN1 is connected to the source of MN3. The drain of MN2 is connected to the source of MN4. The gates of MN3 and MN4 are connected and then connected to the upper end of R2. The drain of MN3 is connected to the lower end of R1. The drain of MN4 is connected to the lower end of R2. The lower end of R0 is connected to the emitter of Q1. The bases and collectors of Q1 and Q2 are connected to ground respectively. The source and substrate of MP10 and the source and substrate of MP11 are connected to an external power supply. The gate and drain of MP10 are shorted and connected to the gate of MP11. The source and substrate of MN5, the source and substrate of MN6, and the source and substrate of MN7 are connected to ground. The gate and drain of MN5 are shorted and connected to the gates of MN6 and MN7, respectively. The drain of MP8 is connected to the drain of MN5, and the drain of MP9 is connected to the drain of MN6. The source of MP8, the source of MP9, and the drain of MN8 are connected to the drain of MP11, and the drain of MN7 is connected to the drain of MP10. The source of MN8 and the lower plate of C2 are connected to ground. The gate of MN8 and the upper plate of C2 are connected to the drain of MN6. The gate of MP9 is connected to the output voltage V. BG Connected; The source of MP5 is connected to the drain of MP11. The gate of MP5 is connected to the gate of MP3 and the upper end of R1. The drain of MP5 is connected to the upper end of R4 and the gate of MC3. The source of MC3 is connected to the drain of MP11. The lower end of R4 is connected to the gate of MC1, the gate of MC2, and the upper end of R3. The lower end of R3 is connected to ground. The drain of MC1 is connected to the upper end of R0. The drain of MC2 is connected to the emitter of Q2. The sources of MC1 and MC2 are connected to ground. The gates of MR1, MR2, MR3, MR4, and MR5 are connected to ground. The source of MR1 is connected to the drain of MC3. The drain of MR1 is connected to the source of MR2. The drain of MR2 is connected to the source of MR3. The drain of MR3 is connected to the source of MR4. The drain of MR4 is connected to the source of MR5. The drain of MR5 is connected to the upper plate of C3. The lower plate of C3 is connected to ground. The gate of MP5 is connected to the gate of PMOS transistor MP6, the source of MP6 is connected to the drain of MP11, the drain of MP6 is connected to the source of PMOS transistor MP7, the gate of MP7 is connected to the gate of MP2, the drain of MP7 is connected to the upper end of resistor R5, the lower end of R5 is connected to the emitter of PNP transistor Q3, and the base and collector of Q3 are connected to ground respectively.

2. The bandgap reference circuit for suppressing high power supply noise at low temperatures according to claim 1, characterized in that: The startup circuit includes a first startup circuit and a second startup circuit. The first startup circuit includes NMOS transistors MS1 and MS2, a PMOS transistor MS3, and a capacitor C1. The second startup circuit includes NMOS transistors MS4, MS6, and MS7, and PMOS transistors MS5, MS8, and MS9. The source and substrate of MS3 are connected to an external power supply. The gate and drain of MS3 are shorted and connected to the upper plate of C1, the drain of MS1, and the gate of MS2, respectively. The gate of MS1 is connected to the drain of MP9, and the drain of MS2 is connected to the drain of MP10. The lower plate of C1, the source of MS1, and the source of MS2 are connected to ground. The drain of MS4 is connected to the drain of MS5 and the gate of MS6. The gate of MS4 is shorted to the gate of MS7 and connected to the drain of MS7 and the drain of MS8. The source of MS5 is connected to the source of MP11. The drain and gate of MS5 are shorted. The drain of MS6 is connected to the gate of MS8 and the gate of MP3. The source of MS8 is connected to the drain of MS9. The source of MS9 is connected to the drain of MP11. The gate of MS9 is connected to the gate of MP3. The sources of MS6, MS4, and MS7 are connected to ground.

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