Systems and methods for data transmission

Abstract

Systems and methods for data transmission are disclosed. The system can include a phase test circuit including a difference detection circuit, a low pass filter circuit, and a reference comparison circuit. The difference detection circuit can be configured to produce an output signal having a duty cycle corresponding to a phase difference between a first input signal and a second input signal. The low pass filter circuit can be connected to an output of the difference detection circuit, and the reference comparison circuit can be configured to compare an output signal of the low pass filter circuit to a threshold.

Description

Technical Field

[0001] One or more aspects of embodiments of this disclosure relate to data links, and more specifically to phase calibrators for data links. Background Technology

[0002] Data links can be used in a variety of applications, such as between separately packaged devices or between dies in multi-chip modules.

[0003] The aspects of this disclosure are relevant to the general technical environment.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0005] According to embodiments of the present disclosure, a system for data transmission is provided, comprising: a phase test circuit including: a difference detection circuit; a low-pass filter circuit; and a reference comparison circuit, wherein the difference detection circuit is configured to generate an output signal having a duty cycle corresponding to a phase difference between a first input signal and a second input signal, the low-pass filter circuit being connected to the output of the difference detection circuit, and the reference comparison circuit being configured to compare the output signal of the low-pass filter circuit with a threshold.

[0006] In some embodiments, the threshold is set by a programmable voltage reference circuit.

[0007] In some embodiments, the programmable voltage reference circuit includes a digital-to-analog converter.

[0008] In some embodiments, the system further includes a first phase interpolator and a second phase interpolator, wherein the system is configured to calibrate the first phase interpolator by setting a phase interpolator control signal of the first phase interpolator to a first value; and adjusting the threshold.

[0009] In some embodiments, the difference detection circuit includes: a first AND gate having: a first input configured to receive a first input signal, and a second input configured to receive a second input signal; and a second AND gate having: a third input configured to receive a third input signal, and a fourth input configured to receive a fourth input signal.

[0010] In some embodiments, the difference detection circuit includes: a first switch located between the output of the first AND gate and the output of the difference detection circuit, and a second switch located between the output of the second AND gate and the output of the difference detection circuit.

[0011] In some embodiments, the first switch is controlled by the output of the second AND gate, and the second switch is controlled by the output of the first AND gate.

[0012] In some embodiments: the difference detection circuit is configured to receive the first input signal via a first timing circuit, and the difference detection circuit is configured to receive the second input signal via a second timing circuit.

[0013] In some embodiments, the reference comparator circuit includes a clocked comparator and a digital accumulator circuit.

[0014] In some embodiments, the clocked comparator is configured to generate an output corresponding to a comparison between the output of the low-pass filter circuit and the threshold.

[0015] In some embodiments, the digital accumulator circuit is configured to generate an output signal based on a plurality of bits received from the clock comparator.

[0016] In some embodiments, the digital accumulator circuit includes: a first counter for counting bits having a value of 1; a second counter for counting bits having a value of 0; and an output circuit for generating a first output value based on the first counter reaching a threshold count, or generating a second output value based on the second counter reaching the threshold count.

[0017] According to embodiments of this disclosure, a method for data transmission is provided, comprising: setting a first phase interpolator control signal to a first value; determining by a phase testing circuit that the phase difference between the output of the first phase interpolator and the output of the second phase interpolator exceeds a first threshold; setting the first phase interpolator control signal to a second value; determining by the phase testing circuit that the phase difference between the output of the first phase interpolator and the output of the second phase interpolator is less than the first threshold; and storing the first value or the second value as a calibrated control signal value corresponding to the first threshold.

[0018] In some embodiments, the phase testing circuit includes: a difference detection circuit; a low-pass filter circuit; and a reference comparison circuit, wherein the difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between a first input signal and a second input signal, the low-pass filter circuit is connected to the output of the difference detection circuit, and the reference comparison circuit is configured to compare the output signal of the low-pass filter circuit with a second threshold.

[0019] In some embodiments, the second threshold is set by a programmable voltage reference circuit.

[0020] In some embodiments, the programmable voltage reference circuit includes a digital-to-analog converter.

[0021] In some embodiments, the difference detection circuit implements an XOR truth table.

[0022] In some embodiments, the difference detection circuit includes: a first AND gate having: a first input configured to receive a first input signal, and a second input configured to receive a second input signal; and a second AND gate having: a third input configured to receive a third input signal, and a fourth input configured to receive a fourth input signal.

[0023] In some embodiments, the difference detection circuit includes: a first switch located between the output of the first AND gate and the output of the difference detection circuit, and a second switch located between the output of the second AND gate and the output of the difference detection circuit.

[0024] According to embodiments of this disclosure, a method for data transmission is provided, comprising: determining, by a phase test circuit, that a phase difference between the output of a first phase interpolator and the output of a second phase interpolator exceeds a first threshold, wherein the phase test circuit includes: a difference detection circuit; a low-pass filter circuit; and a reference comparison circuit, the difference detection circuit being configured to generate an output signal having a duty cycle corresponding to the phase difference between a first input signal and a second input signal, the low-pass filter circuit being connected to the output of the difference detection circuit, and the reference comparison circuit being configured to compare the output signal of the low-pass filter circuit with the second threshold. Attached Figure Description

[0025] These and other features and advantages of this disclosure will be appreciated and understood by referring to the specification, claims and drawings, wherein:

[0026] Figure 1A This is a block diagram of a system including multiple interconnected digital circuits according to embodiments of the present disclosure;

[0027] Figure 1B This is a block diagram of two interconnected digital circuits according to embodiments of the present disclosure;

[0028] Figure 1C This is a block diagram of a transmitter and receiver according to embodiments of the present disclosure;

[0029] Figure 2 This is a circuit diagram of a phase test circuit according to an embodiment of the present disclosure;

[0030] Figure 3 A circuit diagram of a digital accumulator according to an embodiment of the present disclosure; and

[0031] Figure 4 This is a flowchart of a method according to an embodiment of the present disclosure. Detailed Implementation

[0032] The detailed description set forth below with reference to the accompanying drawings is intended to describe aspects of a data transmission system and method that includes, for example, a phase calibrator provided according to this disclosure, and is not intended to represent the only form in which this disclosure may be constructed or utilized. This description illustrates features of this disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments that are also intended to be included within the scope of this disclosure. As indicated elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0033] In various electronic and computer systems, it may be desirable to enable components within the system (such as graphics cards, hard disk drives (including solid-state drives (SSDs)), memory devices, network components or adapters, or other peripheral components or devices) to communicate with each other using high-speed data transmission links. Such high-speed data transmission links can include, for example, Universal Chipset Interconnect High Speed ​​(UCIe), Peripheral Component Interconnect High Speed ​​(PCIe), Integrated Many-Core Token Interface (KTI), Ultra Path Interconnect (UPI), Quick Path Interconnect (QPI), Universal Serial Bus (USB), etc. These data transmission links enable relatively high data transfer rates, flexible bandwidth allocation, simultaneous data transmission, relatively low latency, and other characteristics.

[0034] In a data transmission link, data can be transmitted along with a clock signal from a transmitter component or circuit (hereinafter referred to as the "transmitter") to a receiver component or circuit (hereinafter referred to as the "receiver"). A clock signal that may include two complementary signals can be generated by two phase interpolators in the transmitter. In some systems, the bit stream may carry an embedded clock. In some embodiments, the clock is transmitted separately as a forwarded clock.

[0035] The phase interpolator can be adjusted using a feed from the receiver to use a phase that is halfway between the minimum and maximum phases of successfully received data. The minimum and maximum phases of successfully received data can be determined by the transmitter and receiver using a process in which the phases are adjusted to the minimum and maximum points, where the error rate measured by the receiver increases significantly.

[0036] Adjusting the phase interpolator to a phase that is halfway between the minimum phase (the phase in which data is successfully received) and the maximum phase (the phase in which data is successfully received) can include setting the phase interpolator control signal to an intermediate value that is approximately halfway between the values ​​corresponding to the minimum and maximum phases; however, for example, if the phase generated by each phase interpolator is not linear with the phase interpolator control signal, the phase corresponding to these intermediate values ​​may not be exactly halfway between the values ​​corresponding to the minimum and maximum phases.

[0037] Therefore, in some embodiments described in more detail below, when the first phase interpolator of the phase interpolator is set to a fixed phase, and the second phase interpolator is set to several different phase settings by setting the phase interpolator control signal of the second phase interpolator to several different values, a phase test circuit can be used to measure the phase difference between the phase interpolators. In this way, the second phase interpolator can be calibrated, for example, by measuring the true phase produced for each of several values ​​of the phase interpolator control signal, and a calibration table containing the corresponding phase interpolator control signal values ​​that can be used to achieve any phase in the desired set of phases can be generated and stored. The first phase interpolator can then be calibrated in a similar manner when the second phase interpolator is set to a fixed phase.

[0038] A phase test circuit can be a circuit that determines whether the phase difference between the phase interpolator control signals is greater than or less than a threshold phase value, which is adjustable. Thus, the phase test circuit can be used to measure the phase difference by adjusting the threshold phase value until the output of the phase test circuit changes; at this point, the phase difference is equal to (or almost equal to) the threshold phase value.

[0039] As described in more detail below, according to some embodiments, the phase test circuit may include (i) a difference detection circuit (which can compute a function equivalent to XOR), (ii) a low-pass filter connected to the output of the difference detection circuit, and (iii) a reference comparison circuit for determining whether the output of the low-pass filter is greater than or less than a threshold (e.g., a reference voltage generated by the low-pass filter). The difference detection circuit may function to generate a rectangular wave signal whose duty cycle is proportional to the phase difference between the inputs of the difference detection circuit (0 duty cycle if the input signals are the same (in which case the XOR of these signals is always 0), and 100% duty cycle if the input signals are 180 degrees out of phase (in which case the XOR of these signals is always 1)). The low-pass filter may function to generate an output signal proportional to the average value of the rectangular wave signal (and proportional to the duty cycle). Thus, the output of the low-pass filter can be proportional to the phase difference between the input signals. In some embodiments, each input signal is processed by a frequency divider to reduce the frequency by a factor of 2 and (for a given delay) the phase difference by a factor of 2.

[0040] Figure 1A A system-level diagram of a system comprising multiple digital circuits 105 is shown. Each of these circuits may be a single semiconductor chip (e.g., a silicon digital integrated circuit), such as a tensor stream processing unit (TPU), a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (e.g., a silicon application-specific integrated circuit (ASIC)), a hard disk drive (e.g., a solid-state drive (SSD)), a memory device, a network component or adapter, or other peripheral components or devices. The digital circuits 105 may be connected via multiple data links 110, each of which may be a data link utilizing a data link protocol or mechanism. Such data links 110 may enable, for example, the digital circuits 105 to transmit data (e.g., data to be processed, or data already processed by one or more of the digital circuits 105) to each other. For example, a first digital circuit may process data it receives (e.g., from off-chip or on-chip memory) and transmit the result to a second digital circuit. Communication between the multiple digital circuits 105 and other circuits (e.g., memory circuitry for storing the data to be processed) may be performed via additional data links (not shown).

[0041] In some embodiments, each of the data links 110 is a Universal Chipset Interconnect Fast (UCIe) data link, but embodiments of this disclosure are not limited thereto, and data link 110 may utilize other data link protocols or mechanisms according to various embodiments. A Universal Chipset Interconnect Fast (UCIe) data link may be a data link compliant with an open industry standard (UCIe standard) designed to facilitate die-to-die interconnects and communication between dies (or “chiplets”) in a multi-chip module (e.g., a multi-chip system-on-a-chip (SoC)). UCIe can be used as a package-level universal interconnect (e.g., within the package of a multi-chip module (e.g., a multi-chip SoC)).

[0042] The UCIe standard specifies standardized die-to-die interconnects, including the physical layer, protocol stack, software model, and compliance test procedures. Standardization allows components manufactured by different companies to be compatible with each other. The UCIe physical layer supports relatively fast data transfer rates (e.g., up to 32 gigabits per second (Gbps)) over multiple channels (e.g., between 16 and 64 channels). Like Fast Peripheral Component Interconnect (PCIe) 6.0 links, UCIe links can use 256-byte Flow Control Units (FLITs) for data transfer. The physical specifications of the UCIe standard are based on the Advanced Interface Bus (AIB) specifications; these physical specifications result in high performance and power efficiency.

[0043] The UCIe protocol layer is based on the Compute Fast Link (CXL) standard and includes the CXL.io (PCIe), CXL.mem, and CXL.cache protocols. UCIe-compliant data links are compatible with a variety of interconnect technologies, including organic substrates, silicon interposers, and fan-out embedded bridges for standard 2D packaging and embedded silicon bridges (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). Such interconnect technologies can enhance bandwidth density and power efficiency. Compared to, for example, PCIe serializer deserializers (SerDes), UCIe-compliant data links can exhibit significantly higher I / O performance and lower power consumption. For example, for a 45 μm bump pitch, a UCIe-compliant data link can provide up to [percentage missing] mm / s. 2 A bandwidth density of 1.35 Tb / s.

[0044] UCIe-compliant data links can be used in a variety of applications, including high-performance computing data centers, edge computing, and automotive and high-reliability applications. UCIe-compliant data links are suitable for high-performance computing applications where efficient interconnects between chips can be critical. In data centers, using UCIe-compliant data links enables the integration of various chips, allowing for customized solutions.

[0045] Artificial intelligence and machine learning applications can benefit from the high bandwidth and low latency offered by UCIe-compliant data links. By enabling efficient data transmission between dies, UCIe-compliant data links make it possible to rapidly process and analyze large datasets. In edge computing, UCIe-compliant data links can serve as part of the infrastructure for deploying and managing dies at the network edge.

[0046] In automotive and high-reliability applications, UCIe-compliant data links can provide runtime health monitoring and remediation features (which are part of the UCIe specification). These features ensure the robustness and reliability of the data links, allowing them to be used in safety-critical systems. UCIe-compliant data links are compatible with three-dimensional (3D) packaging, enabling high package density.

[0047] Figure 1B A data link 110 is shown between a first digital circuit 105a and a second digital circuit 105b in digital circuitry 105. The first digital circuit 105a includes a transmitter (Tx) (e.g., a UCIe transmitter) 115, and the second digital circuit 105b includes a receiver (Rx) (e.g., a UCIe receiver) 120. Although for ease of illustration and description, Figure 1B A first digital circuit 105a including a transmitter 115 and a second digital circuit 105b including a receiver 120 are shown, but in various embodiments, each of the digital circuits may include both a transmitter and a receiver or a transceiver. For example, the transmitter 115 may operate to convert or encode digital data from the first digital circuit 105a into a bit stream and transmit the bit stream to the receiver 120 of the second digital circuit 105b via the physical medium of the data link 110 (e.g., conductive wiring, optical fiber, etc.).

[0048] Figure 1C The connection between transmitter 115 and receiver 120 is shown. Data link 110 may include a data channel 125 and a clock channel. Figure 1C As shown, the two clock signals (CKP and CKN) can be generated by a first phase interpolator (PI) 140 and a second phase interpolator 145. In operation, these signals (CKP and CKN) can be separated, for example, by 180 degrees or 90 degrees (when transmitting in-phase (I) and quadrature (Q) clock signals). The phase of each phase interpolator (e.g., the first phase interpolator 140 or the second phase interpolator 145) can be controlled by a corresponding digital control signal (e.g., a 5-bit control signal), which may be referred to as the phase interpolator control signal (or PI code, or "PI_code").

[0049] Sideband channel 135 can be used to transmit feed or control signals from receiver 120 to transmitter 115. During operation (e.g., at startup), transmitter 115 can scan the clock phase over a range of clock phases while transmitting data (e.g., a set pseudo-random bit pattern) to receiver 120, and receiver 120 can transmit an indication to transmitter 115 of whether the data has been successfully received. Transmitter 115 can then determine the range of phase values ​​for which data was successfully received, and for subsequent operations, set the operating phase to the midpoint of that range.

[0050] If the phase of the output of a phase interpolator (e.g., first phase interpolator 140, second phase interpolator 145) is not linear with the interpolator control signal, setting the operating phase to the midpoint of the range may be inaccurate. For example, if the first phase interpolator 140 is linear, setting the control signal of the first phase interpolator 140 to a value halfway between a first value and a second value will result in a phase halfway between the phase corresponding to the first value and the phase corresponding to the second value. However, if the first phase interpolator 140 is not linear, such a control signal setting may result in a different, potentially incorrect phase. Thus, each of the phase interpolators (e.g., first phase interpolator 140 or second phase interpolator 145) can be calibrated (using the systems and methods disclosed herein).

[0051] Figure 2 Aspects of a phase test circuit 205 according to some embodiments are shown. The phase test circuit 205 can be, for example, a transmitter 115 (such as...). Figure 1C Part of the operation (shown) is used to measure the phase of the signal generated by each of the phase interpolators (e.g., the first phase interpolator 140 or the second phase interpolator 145) in response to a series of phase interpolator control signals, in order to calibrate the phase interpolators (e.g., the first phase interpolator 140, the second phase interpolator 145). In some embodiments, the phase test circuit 205 is alternatively part of the receiver 120. Although Figure 2 Various components in a phase test circuit 205 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and the phase test circuit 205 according to various embodiments may include additional components or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0052] Phase test circuit 205 (i) receives a first clock signal CKP at a first input, (ii) receives a second clock signal CKN at a second input, and (iii) receives a threshold signal (which can be received from the control circuit of transmitter 115) at a fifth input 210. The threshold signal can be used to set a first phase threshold. Phase test circuit 205 generates a one-bit digital output signal (at output 215). If the phase difference between the first clock signal CKP and the second clock signal CKN is greater than the first phase threshold, the one-bit digital output signal has a first value; if the phase difference between the first clock signal CKP and the second clock signal CKN is less than the first phase threshold, the one-bit digital output signal has a second value.

[0053] The phase test circuit 205 includes two frequency dividers 220, a difference detection circuit 230, a low-pass filter 235 connected to the output of the difference detection circuit 230, a programmable voltage reference (or programmable voltage reference circuit 255) (which may include a digital-to-analog converter 245 and a low-pass filter 247), and a comparator circuit 260 including a clocked comparator 240 and a digital accumulator 250. Figure 2 The difference detection circuit 230 has four inputs, such as (i) the first input and the second input (which are... Figure 2 The inputs of the AND gate (also called the first AND gate) at the top and the third and fourth inputs (they are...) Figure 2 The difference detection circuit 230 determines whether the signals at the first input and the second input are different. Equivalently, since the signals at the third and fourth inputs are the complements of the signals at the first and second inputs, the difference detection circuit 230 determines whether the signals at the third and fourth inputs are different. For example, the difference detection circuit 230 may also include a first switch and a second switch, wherein the first switch may be located between the output of the first AND gate and the output of the difference detection circuit 230, and the second switch may be located between the output of the second AND gate and the output of the difference detection circuit 230. Furthermore, for example, the first switch may be controlled by the output of the second AND gate, and the second switch may be controlled by the output of the first AND gate.

[0054] For example, the difference detection circuit 230 can calculate the XOR of the output of the frequency divider 220 and filter the result using a low-pass filter 235. The XOR output can be a square wave with a duty cycle proportional to the phase difference between the signals at the output of the frequency divider 220; thus, the output of the low-pass filter 235 (e.g., the DC component of the output of the low-pass filter 235) is proportional to the phase difference between the signals at the output of the frequency divider 220. The low-pass filter 235 can be a linear time-invariant circuit, and it can have a corner frequency between 10^-6 F and F, where F is the clock frequency of the data link. The low-pass filter 235 can have a DC gain of approximately 1.0 (e.g., between 0.1 and 1.0). Figure 2 (Example shown).

[0055] The output of the low-pass filter 235 is compared (via comparator circuit 260) with the voltage output from the programmable voltage reference circuit 255, which corresponds to a second phase threshold (because the frequency divider 220 reduces the phase difference (corresponding to a given delay) by a factor of 2, so the second phase threshold is half of the first phase threshold). Thus, the phase test circuit 205 (as described above) determines whether the phase difference between the first clock signal CKP and the second clock signal CKN is greater than or less than the first phase threshold. This capability can be used to calibrate phase interpolators (e.g., first phase interpolator 140, second phase interpolator 145), as discussed in further detail below. Figure 2 In one embodiment, the combination of programmable voltage reference circuit 255 and comparator circuit 260 determines whether the output of low-pass filter 235 is less than or greater than a threshold (set by programmable voltage reference circuit 255); thus, the combination of programmable voltage reference circuit 255 and comparator circuit 260 can be referred to as a reference comparator circuit.

[0056] In the phase test circuit 205, as described above, the frequency of each of the first clock signal CKP and the second clock signal CKN is divided by 2 by the frequency divider 220 (converting it into a signal with half the frequency of the original signal). This forms an inverted version of each of the resulting signals, and the resulting signals are processed by the retiming stage 225 (which may include a retiming circuit (e.g., a flip-flop) for each of the four signals to be retimed, as shown). The retiming circuit can synchronize the divided clock signals to the first clock signal CKP and the second clock signal CKN. The four signals are then fed to the difference detection circuit 230, which generates an output value of one when the outputs of the frequency divider 220 are the same (i.e., all zero or all one), and an output value of zero when the outputs of the frequency divider 220 are different (i.e., one is zero and the other is one). Thus, the difference detection circuit 230 has the effect of an XOR gate with differential inputs (e.g., it has the same truth table as an XOR gate). Although various components are shown as included in the difference detection circuit 230, some embodiments are not limited to such implementations, and any other suitable components may be used to construct circuitry for performing the functions of the difference detection circuit 230.

[0057] The output of the difference detection circuit 230 is fed to a low-pass filter 235 (e.g., a low-pass filter circuit), and the output of the low-pass filter 235 is fed to a first input of a comparator circuit 260, which includes a clocked comparator (e.g., a clocked comparator circuit, such as a strong-arm latch) 240 and a digital accumulator 250 (e.g., a digital accumulator circuit). Another input of the comparator circuit 260 may be fed by a reference voltage generated by a programmable voltage reference circuit 255. In the comparator circuit 260, the output of the clocked comparator 240 may be fed to the digital accumulator 250 (discussed in further detail below). If the phase difference between the first clock signal CKP and the second clock signal CKN is greater than a first phase threshold, the digital accumulator 250 produces a digital output with a first value (e.g., 1), and if the phase difference between the first clock signal CKP and the second clock signal CKN is less than the first phase threshold, the digital accumulator 250 produces a digital output with a second value (e.g., 0).

[0058] Figure 3 A schematic diagram showing further details of the digital accumulator 250 is provided. Figure 2 and 3As shown, the digital accumulator 250 may include two inputs connected to the respective outputs of the clock comparator 240: a first input S, which is high when the output of the clock comparator 240 is high; and a second input R, which is high when the output of the clock comparator 240 is low. The digital accumulator 250 includes an upper arm and a lower arm, each arm including an AND gate 305, a 4-bit counter 310, a NAND gate 315, and an inverter 320. In operation, the 4-bit counter 310 of the upper arm counts the number of clock edges during which the output of the low-pass filter 235 is greater than the output of the programmable voltage reference circuit 255, and the 4-bit counter 310 of the lower arm counts the number of clock edges during which the output of the low-pass filter 235 is less than the output of the programmable voltage reference circuit 255. The 4-bit counter 310, which first reaches its maximum value (where each of the 4 bits has a value of 1), then causes (i) the output of the NAND gate 315 connected to its output to go low (causing both counters to stop counting), and (ii) the output of the inverter 320 connected to the NAND gate to go high. Thus, the digital accumulator 250 can effectively add (e.g., accumulate) multiple comparator decisions (each comparator decision represented by a corresponding bit received from the clocked comparator 240), thereby reducing the impact of comparator noise.

[0059] Because the phase test circuit 205 can be used to determine whether the phase difference between the first clock signal CKP and the second clock signal CKN is greater than or less than a set phase threshold, it can be used to measure (and correct) the nonlinearity of the phase generated in either of the phase interpolators (e.g., the first phase interpolator 140 and the second phase interpolator 145) as it changes with the phase interpolator control signal it receives. For example, the first phase interpolator 140, which generates the first clock signal CKP, can be set to a fixed value (e.g., by setting the first phase interpolator control signal controlling the first phase interpolator 140 to zero), and the second phase interpolator control signal controlling the second phase interpolator 145 can be adjusted until the measured phase difference is 225 degrees. This can be accomplished by setting the programmable voltage reference circuit 255 to a value corresponding to 225 degrees and searching for two adjacent values ​​of the phase interpolator control signal, with the output of the phase test circuit 205 varying between these two adjacent values. Then, either of these two values ​​can be used as a phase interpolator control signal value, which generates a phase offset (e.g., 225 degrees) in the second phase interpolator 145 corresponding to the output voltage of the programmable voltage reference circuit 255. This process can be repeated for multiple settings of the programmable voltage reference circuit 255, and the second phase interpolator control signal found for each setting of the programmable voltage reference circuit 255 can be stored as a phase interpolator control signal value in a calibration table of the second phase interpolator 145, generating a phase offset in the second phase interpolator 145 corresponding to the setting of the programmable voltage reference circuit 255. This process can be repeated for other phase offset values ​​(e.g., 135 degrees or 180 degrees). In some embodiments, a finer phase step size (e.g., a 5-degree step) is used instead of a 45-degree step size for phase calibration. In some embodiments, only the phase offset of approximately 180 degrees between the first clock signal CKP and the second clock signal CKN is calibrated.

[0060] Once one of the phase interpolators (e.g., the first phase interpolator 140, the second phase interpolator 145) has been calibrated in this manner, the calibrated phase interpolator can be set to a fixed value, and the other phase interpolator can be calibrated in the same way.

[0061] Figure 4 A flowchart illustrating a method for calibrating the first phase interpolator 140 using a phase test circuit 205 is shown. Although Figure 4 Various operations in this method are illustrated, but the embodiments according to this disclosure are not limited thereto. For example, according to some embodiments, such a method may include additional or fewer operations, or the order of operations may be varied (unless otherwise expressly stated or implied) without departing from the spirit and scope of the embodiments according to this disclosure.

[0062] exist Figure 4 In one embodiment, a first calibration process 402 is used to find a second phase interpolator control signal corresponding to a phase difference of 180 degrees. At 404, the first phase interpolator control signal is set to a nominal (uncalibrated) value corresponding to 0 degrees, the second phase interpolator control signal is set to a nominal (uncalibrated) value corresponding to 180 degrees, and the programmable voltage reference circuit 255 is configured to generate a voltage of VDD / 2, corresponding to a phase difference of 180 degrees. A wait operation is performed at 406 to allow the system to reach a steady state, the counter of the digital accumulator 250 is reset (e.g., cleared) at 408, and at 410 and 412, the system waits until one of the counters of the digital accumulator 250 reaches its maximum value. At 414, the system determines whether the output of the comparator circuit 260 has changed from its value for the phase interpolator control signal value tested previously; if it has changed, the calibration is completed for the calibrated phase value, and the current phase interpolator control signal value or the phase interpolator control signal value tested previously can be stored at 417 as a calibration control signal value corresponding to the threshold; if it has not changed, the phase interpolator control signal value is incremented or decremented by 1 at 416.

[0063] The second calibration process 422 is performed for a phase difference of 225 degrees in a manner similar to that shown in the first calibration process 402. At 424, the first phase interpolator control signal is set to a nominal (uncalibrated) value corresponding to 0 degrees, the second phase interpolator control signal is set to a nominal (uncalibrated) value corresponding to 225 degrees, and the programmable voltage reference circuit 255 is configured to generate a voltage of 3VDD / 8, corresponding to a phase difference of 225 degrees. A wait operation is performed at 426 to allow the system to reach a steady state, the counter of the digital accumulator 250 is reset (e.g., cleared) at 428, and at 430 and 432, the system waits until one of the counters of the digital accumulator 250 reaches its maximum value. At 434, the system determines whether the output of the comparator circuit 260 has changed from its value for the phase interpolator control signal value tested previously; if it has changed, calibration is complete for the calibrated phase value, and the current phase interpolator control signal value or the previously tested phase interpolator control signal value can be stored at 437 as a calibration control signal value corresponding to the threshold; if it has not changed, the phase interpolator control signal value is incremented or decremented by 1 at 436. Additional calibration procedures can be performed ( Figure 4 This process is repeated in (not shown in the image) for example, to calibrate the phase interpolator control signal required to achieve a 135-degree phase difference.

[0064] As used herein, “a portion” of something means “at least some” of that thing, and therefore can mean less than or all of that thing. Thus, “a portion” of something includes the whole thing as a special case, i.e., an example where the whole thing is a portion of something. As used herein, when a second quantity is “within Y” of a first quantity X, it means that the second quantity is at least XY and at most X+Y. As used herein, when a second quantity is “within Y%” of a first quantity, it means that the second quantity is at least (1-Y / 100) times the first quantity and at most (1+Y / 100) times the first quantity. As used herein, the term “or” should be interpreted as “and / or”, such that, for example, “A or B” means any one of “A” or “B” or “A and B”.

[0065] The background information provided in the Background section of this disclosure is included only to set the context, and the content of that section is not intended to be prior art. Any component or combination of components described (e.g., in any system diagram included herein) may be used to perform one or more operations of any flowchart included herein. Furthermore, (i) the operations are example operations and may involve various additional steps not explicitly covered, and (ii) the temporal order of the operations may vary.

[0066] The terms “processing circuit” and “means for processing” are used herein to refer to any combination of hardware, firmware, and software used for processing data or digital signals. Processing circuit hardware may include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable gate arrays (FPGAs). In processing circuitry, as used herein, each function is performed by hardware configured (i.e., hardwired) to perform said function or by more general-purpose hardware (e.g., a CPU) configured to execute instructions stored in a non-transitory storage medium. Processing circuitry may be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processing circuitry may include other processing circuitry; for example, processing circuitry may include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

[0067] As used herein, when a method (e.g., adjustment) or a first quantity (e.g., a first variable) is referred to as “based on” a second quantity (e.g., a second variable), it means that the second quantity is an input to the method or affects the first quantity. For example, the second quantity may be an input to a function that computes the first quantity (e.g., a unique input or one of several inputs), or the first quantity may be equal to the second quantity, or the first quantity may be the same as the second quantity (e.g., stored in memory at one or more locations that are the same as the second quantity).

[0068] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of the inventive concept, the first element, component, region, layer, or portion discussed herein may be referred to as the second element, component, region, layer, or portion.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases of measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0070] Expressions such as "at least one of..." modify the entire list of elements when preceding it, but do not modify individual elements in the list. Furthermore, the use of "may" when describing embodiments of the inventive concept means "one or more embodiments of this disclosure." Additionally, the term "exemplary" is intended to refer to an example or illustration. As used herein, the terms "use," "using," and "used" can be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0071] It should be understood that when a component or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component or layer, or one or more intermediate components or layers may exist. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another component or layer, no intermediate components or layers exist.

[0072] Any numerical range described herein is intended to include all subranges containing the same numerical precision within the range. For example, a range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between the minimum value 1.0 and the maximum value 10.0 (and including the endpoints), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Similarly, a range described as “within 35% of 10” is intended to include all subranges between the minimum value 6.5 (i.e., (1-35 / 100) multiplied by 10) and the maximum value 13.5 (i.e., (1+35 / 100) multiplied by 10) (and including the endpoints), i.e., a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5, such as 7.4 to 10.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein.

[0073] It should be understood that when a component is referred to as “directly connected” or “directly coupled” to another component, there is no intermediate component. As used herein, “generally connected” means a connection via an electrical path that may contain any intermediate component, including those whose presence qualitatively alters the circuit behavior. As used herein, “connection” means (i) “directly connected” or (ii) connected to an intermediate component that does not qualitatively affect the circuit behavior (e.g., a low-value resistor or inductor, or a short section of a transmission line).

[0074] Some embodiments may include the features stated by the following numbers.

[0075] 1. A system for data transmission, comprising:

[0076] Phase test circuit, including:

[0077] Difference detection circuit;

[0078] Low-pass filter circuit; and

[0079] Reference comparator circuit,

[0080] The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal.

[0081] The low-pass filter circuit is connected to the output of the difference detection circuit.

[0082] The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a threshold.

[0083] 2. The system according to statement 1, wherein the threshold is set by a programmable voltage reference circuit.

[0084] 3. The system according to statement 2, wherein the programmable voltage reference circuit includes a digital-to-analog converter.

[0085] 4. The system according to any of the foregoing statements further includes a first phase interpolator and a second phase interpolator, wherein the system is configured to calibrate the first phase interpolator in the following manner:

[0086] Set the phase interpolator control signal of the first phase interpolator to a first value; and

[0087] Adjust the threshold.

[0088] 5. The system according to any of the preceding statements, wherein the difference detection circuit comprises:

[0089] The first AND gate, the first AND gate having:

[0090] The first input, configured to receive the first input signal, and

[0091] A second input, configured to receive a second input signal; and

[0092] The second AND gate, the second AND gate having:

[0093] The third input, configured to receive a third input signal, and

[0094] The fourth input is configured to receive a fourth input signal.

[0095] 6. The system according to statement 5, wherein the difference detection circuit comprises:

[0096] A first switch, located between the output of the first AND gate and the output of the difference detection circuit, and

[0097] A second switch is located between the output of the second AND gate and the output of the difference detection circuit.

[0098] 7. The system according to statement 6, wherein the first switch is controlled by the output of the second AND gate, and the second switch is controlled by the output of the first AND gate.

[0099] 8. The system according to any of the preceding statements, wherein:

[0100] The difference detection circuit is configured to receive the first input signal via a first timing circuit, and

[0101] The difference detection circuit is configured to receive the second input signal via a second timing circuit.

[0102] 9. The system according to any of the preceding statements, wherein the reference comparator circuit includes a clocked comparator and a digital accumulator circuit.

[0103] 10. The system according to statement 9, wherein the clock comparator is configured to generate an output corresponding to a comparison between the output of the low-pass filter circuit and the threshold.

[0104] 11. The system according to statement 9, wherein the digital accumulator circuit is configured to generate an output signal based on a plurality of bits received from the clock comparator.

[0105] 12. The system according to any one of statements 9 to 11, wherein the digital accumulator circuit comprises:

[0106] The first counter is used to count bits that have a value of 1;

[0107] A second counter is used to count bits with a value of 0; and

[0108] An output circuit is configured to generate a first output value based on the first counter reaching a threshold count, or to generate a second output value based on the second counter reaching the threshold count.

[0109] 13. A method for data transmission, comprising:

[0110] Set the first phase interpolator control signal to the first value;

[0111] The phase difference between the output of the first phase interpolator and the output of the second phase interpolator is determined by the phase test circuit to exceed a first threshold.

[0112] Set the first phase interpolator control signal to the second value;

[0113] The phase difference between the output of the first phase interpolator and the output of the second phase interpolator is determined by the phase testing circuit to be less than the first threshold; and

[0114] The first value or the second value is stored as a calibrated control signal value corresponding to the first threshold.

[0115] 14. The method according to statement 13, wherein the phase test circuit comprises:

[0116] Difference detection circuit;

[0117] Low-pass filter circuit; and

[0118] Reference comparator circuit,

[0119] The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal.

[0120] The low-pass filter circuit is connected to the output of the difference detection circuit.

[0121] The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a second threshold.

[0122] 15. The method according to statement 13 or statement 14, wherein the second threshold is set by a programmable voltage reference circuit.

[0123] 16. The method according to statement 15, wherein the programmable voltage reference circuit includes a digital-to-analog converter.

[0124] 17. The method according to statement 14, wherein the difference detection circuit implements an XOR truth table.

[0125] 18. The method according to any one of statements 14 to 17, wherein the difference detection circuit comprises:

[0126] The first AND gate, the first AND gate having:

[0127] The first input, configured to receive the first input signal, and

[0128] A second input, configured to receive a second input signal; and

[0129] The second AND gate, the second AND gate having:

[0130] The third input, configured to receive a third input signal, and

[0131] The fourth input is configured to receive a fourth input signal.

[0132] 19. The method according to statement 18, wherein the difference detection circuit comprises:

[0133] A first switch, located between the output of the first AND gate and the output of the difference detection circuit, and

[0134] A second switch is located between the output of the second AND gate and the output of the difference detection circuit.

[0135] 20. A method for data transmission, comprising:

[0136] The phase test circuit determines that the phase difference between the output of the first phase interpolator and the output of the second phase interpolator exceeds a first threshold.

[0137] The phase testing circuit includes:

[0138] Difference detection circuit;

[0139] Low-pass filter circuit; and

[0140] Reference comparator circuit,

[0141] The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal.

[0142] The low-pass filter circuit is connected to the output of the difference detection circuit.

[0143] The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a second threshold.

[0144] While exemplary embodiments of the phase calibrator have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that a phase calibrator constructed according to the principles of this disclosure may be implemented in a manner different from that specifically described herein. The invention is also defined in the appended claims and their equivalents.

Claims

1. A system for data transmission, comprising: Phase test circuit, including: Difference detection circuit; Low-pass filter circuit; and Reference comparator circuit, The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal. The low-pass filter circuit is connected to the output of the difference detection circuit. The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a threshold.

2. The system according to claim 1, wherein, The threshold is set by a programmable voltage reference circuit.

3. The system according to claim 2, wherein, The programmable voltage reference circuit includes a digital-to-analog converter.

4. The system according to claim 1 further includes a first phase interpolator and a second phase interpolator, wherein, The system is configured to calibrate the first phase interpolator in the following manner: Set the phase interpolator control signal of the first phase interpolator to a first value; and Adjust the threshold.

5. The system according to claim 1, wherein, The difference detection circuit includes: The first AND gate, the first AND gate having: The first input, configured to receive the first input signal, and A second input, configured to receive a second input signal; and The second AND gate, the second AND gate having: The third input, configured to receive a third input signal, and The fourth input is configured to receive a fourth input signal.

6. The system according to claim 5, wherein, The difference detection circuit includes: A first switch, located between the output of the first AND gate and the output of the difference detection circuit, and A second switch is located between the output of the second AND gate and the output of the difference detection circuit.

7. The system according to claim 6, wherein, The first switch is controlled by the output of the second AND gate, and the second switch is controlled by the output of the first AND gate.

8. The system according to claim 1, wherein: The difference detection circuit is configured to receive the first input signal via a first timing circuit, and The difference detection circuit is configured to receive the second input signal via a second timing circuit.

9. The system according to claim 1, wherein, The reference comparator circuit includes a clocked comparator and a digital accumulator circuit.

10. The system according to claim 9, wherein, The clock comparator is configured to generate an output corresponding to a comparison between the output of the low-pass filter circuit and the threshold.

11. The system according to claim 9, wherein, The digital accumulator circuit is configured to generate an output signal based on a plurality of bits received from the clock comparator.

12. The system according to claim 11, wherein, The digital accumulator circuit includes: The first counter is used to count bits that have a value of 1; A second counter is used to count bits with a value of 0; and An output circuit is configured to generate a first output value based on the first counter reaching a threshold count, or to generate a second output value based on the second counter reaching the threshold count.

13. A method for data transmission, comprising: Set the first phase interpolator control signal to the first value; The phase difference between the output of the first phase interpolator and the output of the second phase interpolator is determined by the phase test circuit to exceed a first threshold. Set the first phase interpolator control signal to the second value; The phase difference between the output of the first phase interpolator and the output of the second phase interpolator is determined by the phase testing circuit to be less than the first threshold; and The first value or the second value is stored as a calibrated control signal value corresponding to the first threshold.

14. The method according to claim 13, wherein, The phase testing circuit includes: Difference detection circuit; Low-pass filter circuit; and Reference comparator circuit, The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal. The low-pass filter circuit is connected to the output of the difference detection circuit. The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a second threshold.

15. The method according to claim 14, wherein, The second threshold is set by a programmable voltage reference circuit.

16. The method according to claim 15, wherein, The programmable voltage reference circuit includes a digital-to-analog converter.

17. The method of claim 14, wherein, The difference detection circuit implements an XOR truth table.

18. The method according to claim 14, wherein, The difference detection circuit includes: The first AND gate, the first AND gate having: The first input, configured to receive the first input signal, and A second input, configured to receive a second input signal; and The second AND gate, the second AND gate having: The third input, configured to receive a third input signal, and The fourth input is configured to receive a fourth input signal.

19. The method according to claim 18, wherein, The difference detection circuit includes: A first switch, located between the output of the first AND gate and the output of the difference detection circuit, and A second switch is located between the output of the second AND gate and the output of the difference detection circuit.

20. A method for data transmission, comprising: The phase test circuit determines that the phase difference between the output of the first phase interpolator and the output of the second phase interpolator exceeds a first threshold. The phase testing circuit includes: Difference detection circuit; Low-pass filter circuit; and Reference comparator circuit, The difference detection circuit is configured to generate an output signal having a duty cycle corresponding to the phase difference between the first input signal and the second input signal. The low-pass filter circuit is connected to the output of the difference detection circuit. The reference comparator circuit is configured to compare the output signal of the low-pass filter circuit with a second threshold.

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