Flash memory controller, solid-state storage device and method for monitoring temperature information of solid-state storage device

Abstract

The invention discloses a flash memory controller, a solid-state storage device and a method for monitoring temperature information of the solid-state storage device. The flash memory controller of the solid-state storage device comprises a PCIe physical layer, a PCIe media access control layer, a flash memory control circuit and a temperature information calculation circuit. The method comprises the following steps: respectively detecting first temperature information of a PCIe physical layer and second temperature information of a flash memory control circuit by using a first temperature sensor and a second temperature sensor; calculating average temperature information of the flash memory controller in a preset period by utilizing a temperature information calculation circuit according to the first temperature information and the second temperature information; loading the average temperature information to a buffer of a PCIe media access control layer by utilizing a temperature information calculation circuit in response to a configuration read packet from a host; and reporting the average temperature information to the host through the PCIe bus by using the PCIe media access control layer.

Description

Technical Field

[0001] The present invention relates to integrated circuits, and more particularly to a flash memory controller, a solid state storage device, and a method for monitoring temperature information thereof.

[0002] Prior Art

[0003] In today's computer systems, a host and a solid state storage device can be electrically connected to each other through a Peripheral Component Interconnect Express (PCIe) bus. Although data can be transmitted between the host and a traditional solid state storage device through the PCIe bus, the traditional solid state storage device often needs to use other buses in addition to the PCIe bus to transmit the temperature information of one or more components detected by a temperature sensor in the solid state storage device to the host in real time. This method not only increases the difficulty of circuit design and maintenance and manufacturing cost, but may also cause the host to misjudge the temperature information. Summary of the Invention

[0004] Therefore, the present invention provides a flash memory controller, a solid state storage device, and a method for monitoring temperature information thereof to solve the above problems.

[0005] The present invention provides a flash memory controller electrically connected to a host through a Peripheral Component Interconnect Express (PCIe) bus. The flash memory controller includes a PCIe physical layer, a PCIe media access control layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, and a temperature information calculation circuit. The PCIe physical layer is configured to be electrically connected to the host through the PCIe bus, wherein the PCIe physical layer includes a first temperature sensor for detecting first temperature information of the PCIe physical layer. The PCIe media access control layer, electrically connected to the PCIe physical layer, is configured to convert an access instruction from the host into a PCIe signal. The NVMe conversion circuit is configured to convert the PCIe signal from the PCIe media access control layer into an NVMe signal. The flash memory control circuit is configured to control data access to the flash memory according to the NVMe signal. The flash memory control circuit includes a second temperature sensor for detecting second temperature information of the flash memory control circuit. The temperature information calculation circuit is configured to calculate average temperature information of the flash memory controller within a predetermined period according to the first temperature information and the second temperature information. In response to a configuration read packet from the host, the temperature information calculation circuit is configured to load the average temperature information into a buffer of the PCIe media access control layer, and the PCIe media access control layer returns the average temperature information stored in the buffer to the host through the PCIe bus.

[0006] The present invention further provides a method for monitoring temperature information of a solid-state storage device. The solid-state storage device is electrically connected to a host via a Peripheral Component Interconnect Express (PCIe) bus. The flash memory controller of the solid-state storage device includes a PCIe physical layer, a PCIe media access control layer, a flash memory control circuit, and a temperature information calculation circuit. The method includes: using a first temperature sensor disposed in the PCIe physical layer and a second temperature sensor disposed in the flash memory control circuit to respectively detect first temperature information of the PCIe physical layer and second temperature information of the flash memory control circuit of the flash memory controller within a predetermined period; using the temperature information calculation circuit to calculate average temperature information of the flash memory controller based on the first temperature information and the second temperature information; in response to a configuration read packet from the host, using the temperature information calculation circuit to load the average temperature information into a buffer of the PCIe media access control layer; and using the PCIe media access control layer to report the average temperature information stored in the buffer to the host via the PCIe bus.

[0007] The present invention further provides a solid-state storage device, including a flash memory and a flash memory controller. The flash memory controller includes a PCIe physical layer, a PCIe media access control layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, and a temperature information calculation circuit. The PCIe physical layer is configured to be electrically connected to a host via a PCIe bus, wherein the PCIe physical layer includes a first temperature sensor for detecting first temperature information of the PCIe physical layer. The PCIe media access control layer, electrically connected to the PCIe physical layer, is configured to convert an access instruction from the host into a PCIe signal. The NVMe conversion circuit is configured to convert the PCIe signal from the PCIe media access control layer into an NVMe signal. The flash memory control circuit is configured to control data access of the flash memory based on the NVMe signal. The flash memory control circuit includes a second temperature sensor for detecting second temperature information of the flash memory control circuit. The temperature information calculation circuit is configured to calculate average temperature information of the flash memory controller within a predetermined period based on the first temperature information and the second temperature information. In response to a configuration read packet from the host, the temperature information calculation circuit is configured to load the average temperature information into a buffer of the PCIe media access control layer, and the PCIe media access control layer reports the average temperature information stored in the buffer to the host via the PCIe bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a block diagram of a computer system according to an embodiment of the present invention.

[0010] Figure 2A According to the present invention Figure 1 The block diagram of the temperature information calculation circuit in the embodiment.

[0011] Figure 2B According to the present invention Figure 2A The circuit diagram of the temperature information calculation circuit in the embodiment.

[0012] Figure 3 The schematic diagram of the PCIe configuration space of the solid state storage device according to an embodiment of the present invention.

[0013] Figure 4 The schematic diagram of the vendor capabilities structure according to an embodiment of the present invention.

[0014] Figure 5 The flowchart of the host obtaining the average temperature information of the flash memory controller according to an embodiment of the present invention.

[0015] Figure 6 The block diagram of the computer system according to another embodiment of the present invention.

[0016] Figure 7 The flowchart of the method for monitoring the temperature information of the solid state storage device according to an embodiment of the present invention. Embodiment

[0018] The following description is the preferred implementation for implementing the invention, which aims to describe the basic spirit of the present invention, but is not intended to limit the present invention. The actual content of the invention must refer to the claims hereinafter.

[0019] It must be understood that the words "comprising", "including", etc. used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operations, elements, and / or components, but do not exclude the addition of more technical features, numerical values, method steps, operations, elements, components, or any combination of the above.

[0020] The words such as "first", "second", "third", etc. used in the claims are used to modify the components in the claims, and do not indicate a priority order, precedence relationship, or that one component precedes another component, or the chronological order when performing method steps, but are only used to distinguish components with the same name.

[0021] The term "configured to" can describe or assert that various units, circuits, or other components are "configured to" perform one or more tasks. In such contexts, the term "configured to" is used to imply structure by indicating that the above-mentioned unit / circuit / component includes a structure (e.g., circuitry) that performs those one or more tasks during operation. Thus, even when the specified unit / circuit / component is not currently operating (e.g., not powered on), it can still be said that the above-mentioned unit / circuit / component is configured to perform the above-mentioned tasks. The above-mentioned unit / circuit / component used in conjunction with the term "configured to" includes hardware - such as circuits, memory (storing program instructions executable to implement operations), etc. In addition, "configured to" can include a generic structure (e.g., a general-purpose circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the one or more tasks to be solved. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) that is adapted to implement or perform one or more tasks.

[0022] Figure 1 FIG. is a block diagram of a computer system according to an embodiment of the present invention.

[0023] As Figure 1 shown, the computer system 1 includes a host 10 and a solid-state storage device 20, and the host 10 is electrically connected to the data storage device 20 through a PCIe bus 15. That is, the host 10 and the solid-state storage device 20 can perform data transmission through links 16 and 17 of the PCIe bus 15, where the link 16 is, for example, from the transmit end TX0 of the host 10 to the receive end RX1 of the solid-state storage device 20, and the link 17 is, for example, from the transmit end TX1 of the solid-state storage device 20 to the receive end RX0 of the host 10.

[0024] In some embodiments, the solid-state storage device 20 includes a flash memory controller 200 and a flash memory 30. The flash memory controller 200 is electrically connected to the flash memory 30 and configured to control data access to the flash memory 30. The flash memory controller 200 is, for example, an integrated circuit that supports the PCIe protocol and the Non-Volatile Memory Express (NVMe) protocol. The flash memory 30 is, for example, a NAND flash memory. The flash memory controller 200 includes a PCIe physical layer 210, a PCIe media access control layer 220, an NVMe conversion circuit 230, a flash memory control circuit 240, and a temperature information calculation circuit 250. The PCIe physical layer 210 includes physical interfaces for data transmission, such as a transmitter TX1 and a receiver RX1. The PCIe media access control layer 220 is, for example, a collective term for various circuits and buffers with different functions, which includes a PCIe configuration space 221 and other general control circuits (not shown). The PCIe media access control layer 220 can convert the control signals and data of the host 10 received by the PCIe physical layer 210 through the link 16 into PCIe signals 21. The NVMe conversion circuit 230 is configured to convert the PCIe signals 21 from the PCIe media access control layer 220 into NVMe signals 22, or convert the NVMe signals 22 from the flash memory control circuit 240 into PCIe signals 21. The flash memory control circuit 240 is configured to generate flash memory interface signals 23 according to the NVMe signals 22 to control data access to the flash memory 30. The temperature information calculation circuit 250 is, for example, used to calculate the average temperature information TA of the flash memory controller 200 based on the temperature information TEMP1 detected by the temperature sensor 211 and the temperature information TEMP2 detected by the temperature sensor 241. The details will be described later.

[0025] Figure 2A According to the present invention Figure 1 The block diagram of the temperature information calculation circuit in the embodiment. Figure 2B According to the present invention Figure 2A The circuit diagram of the temperature information calculation circuit in the embodiment.

[0026] In some embodiments, as Figure 2AAs shown, the input signals of the temperature information calculation circuit 250 include a frequency signal CLK, a sampling period signal SP, a request signal REQ, and temperature information TEMP, and its output signal is the average temperature information TA of the flash memory controller 200 (or the solid-state storage device 20). The numerical values on the arrows of the above-mentioned signals represent the widths (number of bits) of the above-mentioned signals. For example, the frequency signal CLK and the request signal REQ are 1-bit signals, and the sampling period signal SP is an n-bit signal, which can be represented by SP[N - 1:0] for example. In some embodiments, the temperature information TEMP1 detected by the temperature sensor 211 and the temperature information TEMP2 detected by the temperature sensor 241 are both 16-bit numerical values for example, and the temperature information TEMP is a 32-bit numerical value obtained by combining the temperature information TEMP1 and TEMP2. The average temperature information TA of the flash memory controller 200 output by the temperature information calculation circuit 250 is also a 32-bit numerical value.

[0027] Please refer to Figure 2B Temperature information calculation circuit 250 includes N D flip-flops 2501 to 250N, N AND gates 2511 to 251N, an adder 2520, and a divider 2530, where N is a positive integer. Each of the D flip-flops 2501 to 250N includes a frequency input terminal CK, an input data terminal D, and an output data terminal Q, and the D flip-flops 2501 to 250N are serially connected in sequence to form a delay chain. For example, the data output terminal Q of the D flip-flop 2501 is connected to the data input terminal D of the D flip-flop 2502, the data output terminal Q of the D flip-flop 2502 is connected to the data input terminal D of the D flip-flop 2503, and so on. It should be noted that the width N (i.e., N bits) of the sampling period signal SP is the same as the number N of the D flip-flops 2501 to 250N and the AND gates 2511 to 251N.

[0028] The data output terminal Q of each of the D flip-flops 2501 to 250N is connected to one of the input terminals of the corresponding AND gates 2511 to 251N. In addition, the other input terminal of each of the AND gates 2511 to 251N receives the corresponding bit of the sampling period signal SP. For example, the AND gate 2511 receives the least significant bit of the sampling period signal SP (i.e., SP[0]), the AND gate 2512 receives the second least significant bit of the sampling period signal SP (i.e., SP[1]), and so on. The AND gates 2511 to 251N generate individual temperature signals S1 to SN, and the adder 2520 adds up the temperature signals S1 to SN to obtain a sum value SUM. The divider 2530 divides the sum value SUM by the effective number M, where the effective number M is equal to the number of bits in the sampling period signal SP that are equal to 1.

[0029] Several examples will be given below to illustrate the operation of the temperature information calculation circuit 250. In Examples 1 to 3, it is assumed that the period length of the frequency signal CLK is 1 millisecond (ms) and the number N = 8, indicating that the temperature information calculation circuit 250 includes 8 D flip-flops, which can form a delay chain with a delay of 8 milliseconds to record the temperature information within 8 frequency cycles. In addition, the width of the sampling period signal SP is 8 bits, for example, it can be represented by SP[7:0].

[0030] In Example 1, the sampling period signal SP[7:0] is set to the binary value 1111_1111, and the effective number M = 8. For the 8 effective sampling points, the sampling interval is 1 millisecond. That is to say, the temperature information calculation circuit 250 will use 1 millisecond as the sampling interval and calculate the average temperature information TA of the flash memory controller 200 within 8 milliseconds.

[0031] In Example 2, the sampling period signal SP[7:0] is set to the binary value 1010_1010, and the effective number M = 4. For these 4 effective sampling points, the sampling interval between two adjacent effective sampling points is 2 milliseconds. That is to say, the temperature information calculation circuit 250 will use 2 milliseconds as the sampling interval and calculate the average temperature information TA of the flash memory controller 200 within 8 milliseconds.

[0032] In Example 3, the sampling period signal SP[7:0] is set to the binary value 1000_1000, and the effective number M = 2. The sampling interval between these 2 effective sampling points is 4 milliseconds. That is to say, the temperature information calculation circuit 250 will use 4 milliseconds as the sampling interval and calculate the average temperature information TA of the flash memory controller 200 within 8 milliseconds.

[0033] In Examples 4 to 5, it is assumed that the period length of the frequency signal CLK is 1 millisecond (ms) and the number N = 16, indicating that the temperature information calculation circuit 250 includes 16 D flip-flops, which can form a delay chain with a delay of 16 milliseconds to record the temperature information within 16 frequency cycles. In addition, the width of the sampling period signal SP is also 16 bits, for example, it can be represented by SP[15:0].

[0034] In Example 4, the sampling period signal SP[15:0] is set to the binary value 1111_1111_1111_1111, and the effective number M = 16. For these 16 effective sampling points, the sampling interval between two adjacent effective sampling points is 1 millisecond. That is to say, the temperature information calculation circuit 250 will use 1 millisecond as the sampling interval and calculate the average temperature information TA of the flash memory controller 200 within 16 milliseconds.

[0035] In Example 5, the sampling period signal SP[15:0] is set to the binary value 1000_1000_1000_1000, and the number of valid samples M = 4. For these 4 valid sampling points, the sampling interval between two adjacent valid sampling points is 4 milliseconds. That is, the temperature information calculation circuit 250 takes a 4-millisecond sampling interval and calculates the average temperature information TA of the flash memory controller 200 within 16 milliseconds.

[0036] In some embodiments, when the sampling interval between two adjacent valid sampling points is M frequency periods, there will be (M - 1) bits equal to 0 between two adjacent valid bits (i.e., bit value = 1) in the sampling period signal SP, where M is a positive integer and M < N. For example, the sampling interval between two valid sampling points in Example 1 is 1 millisecond = 1 frequency period (i.e., M = 1). At this time, the sampling period signal SP[7:0] is the binary value 1111_1111, indicating that there is no 0 between two adjacent bits equal to 1 (i.e., M - 1 = 0). The sampling interval between two valid sampling points in Example 3 is 4 milliseconds = 4 frequency periods (i.e., M = 4). At this time, the sampling period signal SP[7:0] is the binary value 1000_1000, indicating that there are 3 0s between two bits equal to 1 (i.e., M - 1 = 3).

[0037] In some embodiments, when calculating the sum value SUM of the temperature signals S1 to SN, the adder 2520 adds up the first half (e.g., the highest 16 bits) and the second half (e.g., the lowest 16 bits) of the temperature signals S1 to SN respectively to obtain the sum value SUM. That is, the first half and the second half of the sum value SUM are the added values of the temperature information TEMP1 and TEMP2 respectively. Therefore, the average temperature information TA calculated by the divider 2530 also includes the first half and the second half, representing the average value of the temperature information TEMP1 and the average value of the temperature information TEMP2 respectively.

[0038] Figure 3 FIG. is a schematic diagram of the PCIe configuration space of a solid-state storage device according to an embodiment of the present invention. Figure 4 FIG. is a schematic diagram of the PCIe capability structure according to an embodiment of the present invention.

[0039] In some embodiments, the PCIe media access control layer 220 of the solid-state storage device 20 has a buffer bank (not shown) to store the PCIe configuration space 221, where the PCIe configuration space 221 can be used, for example Figure 3is represented by the PCIe configuration space 300. After the PCIe links 16 and 17 between the host 10 and the solid-state storage device 20 are established, the host 10 reads the settings of its PCIe configuration space 221 via the PCIe bus 15 from the flash controller 200 to obtain information about the capabilities of the solid-state storage device 20, such as supported capabilities, device identification, and power management settings. For the sake of illustration, the solid-state storage device 20 supports vendor-specific capabilities, and the host 10 can send a configuration read packet with a specific address through the link 16 to the solid-state storage device 20 to read the value of the average temperature information TA of the flash controller 200, the details of which will be described in detail later.

[0040] For example, the PCIe configuration space 300 includes a PCI configuration space 312 and a PCIe extended configuration space 310, as Figure 3 shown. The PCI configuration space 312 includes a configuration space header 302 that is compatible with the PCI 3.0 standard, configuration spaces 304 and 308, and a PCIe Capability Structure 306. It should be noted that the range of each configuration space in Figure 3 includes the lower limit value of the address offset but does not include the upper limit value. For example, the range of the address offset of the PCIe configuration space 300 is between 0 and 0xFFF (represented in hexadecimal). The range of the address offset of the configuration space header 302 is between 0 and 0x3F.

[0041] When the solid-state storage device 20 supports vendor-specific capabilities, the status register regarding the capability list in the configuration space header 302 is set to 1, and the Capability Pointer 3021 in the configuration space header 302 records the starting address offset of a specific PCIe Capability Structure (such as the PCIe Capability Structure 306). The above specific PCIe Capability Structure may also include a next capability pointer to provide the starting address offset of the next specific PCIe Capability Structure. The PCIe Capability Structure 306 is, for example, an 8-byte memory space, and its address offset range is between 0xF0 and 0xF7. For the sake of illustration, the capability pointer 3021 in the configuration space header 302 points to the PCIe Capability Structure 306 with a starting address offset of 0xF0, which means the address offset range of the PCIe Capability Structure 306 is between 0xF0 and 0xF7.

[0042] In some embodiments, the PCIe Capability Structure 306 can be used Figure 4The PCIe capability structure 400 is shown, which includes fields 402 to 410. Fields 402, 404, 406, and 408 respectively represent the Capability ID, Next Capability Pointer, Capability Length, and Type. Specifically, after the host 10 finishes reading the settings of the configuration space header 302, the host 10 issues a configuration read packet with the address 0xF0 according to the capability pointer 3021 in the configuration space header 302 to read the double-word length setting value starting from 0xF0 in the PCIe capability structure 306, that is, including the Capability ID, Next Capability Pointer, Capability Length, and Type, as shown in fields 402, 404, 406, and 408 in the PCIe capability structure 400 respectively as Figure 4 shown. In some embodiments, the above configuration read packet is, for example, a configuration read transaction layer packet defined by the PCIe protocol, but the present invention is not limited thereto.

[0043] For ease of explanation, the values recorded in fields 402 and 406 are 0x9 and 0x4 respectively. When the value recorded in field 402 is 0x9, it indicates that the solid-state storage device 20 supports vendor-specific capabilities, and at this time, the PCIe capability structure 400 can also be referred to as a vendor-specific capability structure. When the value recorded in field 406 is 0x4, it indicates that the length of the above-mentioned vendor-specific capabilities is 4 bytes. In addition, if the value recorded in field 404 is 0, it means that the PCIe capability structure 400 does not point to other PCIe capability structures. If the set value recorded in field 404 is not 0, it means that the PCIe capability structure 400 will point to the next PCIe capability structure with the value recorded in field 404 as the starting address offset value. Therefore, the host 10 can issue a configuration read packet with the above-mentioned value as the address to the solid-state storage device 20 to read the setting value of the next PCIe capability structure.

[0044] Therefore, after the host 10 checks the set values of fields 402, 404, and 406 to confirm that the solid-state storage device 20 supports vendor-specific capabilities and their lengths, and whether it points to the next PCIe capability structure, the host 10 will then check the set value of field 408 to determine the type of vendor-specific capabilities supported by the solid-state storage device 20. Here, when the set value of field 408 is equal to a specific value (for example, 0x2), the host 10 can determine that the vendor-specific capabilities supported by the solid-state storage device 20 can report the average temperature information TA of the flash memory controller 200.

[0045] In some embodiments, the host 10 can know from the setting value of the configuration space file header 302 that the starting address offset of the PCIe capability structure 306 is 0xF0, and obtain the double-word length setting value starting from the starting address deviation value 0xF0 of the PCIe capability structure 306, that is Figure 4 4 bytes starting from +000h of Figure 4 (including fields 402 to 408). Among them, the capability identifier of field 402 = 0x9, the capability length of field 406 = 0x4, and the type of field 408 = 0x2. Therefore, the host 10 can know that the solid-state storage device 20 supports the vendor-specific capability of reporting the average temperature information TA of the flash memory controller 200, and the PCIe capability structure 306 records the value of the average temperature information TA with a length of 4 bytes (for example, stored in the register 222, which corresponds to field 410 of the PCIe capability structure 400). The average temperature information TA is, for example, a double-word length setting value starting from 0xF4 (that is Figure 4 4 bytes starting from +004h of Figure 4 ). For the operation process of the host 10 to obtain the average temperature information TA of the flash memory controller 200, please refer to Figure 5 .

[0046] In step 502, the host 10 issues a configuration read packet with a specific address to the solid-state storage device 20. For example, the above specific address is 0xF4, which means the starting address deviation value of the average temperature information TA in the PCIe capability structure 306.

[0047] In step 504, in response to the above configuration read packet, the PCIe media access control layer 220 sends a request signal REQ to the temperature information calculation circuit 250. For example, the request signal REQ is used to notify the temperature information calculation circuit 250 to load the currently calculated average temperature information TA of the flash memory controller 200 into the register 222 of the PCIe media access control layer 220, where the register 222 corresponds to field 410 of the PCIe capability structure 400, for example.

[0048] In step 506, the temperature information calculation circuit 250 loads the currently calculated average temperature information TA of the flash memory controller 200 into the register 222.

[0049] In step 508, the PCIe media access control layer 220 packs the average temperature information TA in the register 222 into a data completion packet and transmits the data completion packet to the host 10. The above data completion packet is, for example, a completion with data transaction layer packet defined by the PCIe standard.

[0050] Figure 6A block diagram of a computer system according to another embodiment of the present invention.

[0051] Figure 6 The computer system 6 is similar to Figure 1 the computer system 1, except that the solid-state storage device 600 of the computer system 6 does not configure a temperature sensor at its PCIe physical layer (not shown, already included in the PCIe media access control layer 620), and the bus controller 650 transmits the temperature information TEMP3 of the flash memory control circuit 640 detected by the temperature sensor 641 to the host 50 in real time through the bus 58, rather than through the PCIe bus 55. In some embodiments, the bus 58 can be referred to as a sideband bus, and its communication protocol is different from that of the PCIe bus 55. For example, it can be a Serial Peripheral Interface (SPI), an Inter-Integrated Circuit (I2C), etc., but the present invention is not limited thereto.

[0052] However, in the computer system 6, both the host 50 and the flash memory controller 60 need to set up separate transmission interfaces and related control circuits (such as the bus controller 650) for the bus 58, which will increase the design difficulty and manufacturing cost. When any one of the transmission interfaces and control circuits related to the bus 58 in the host 50 and the flash memory controller 60 is damaged, the host 50 cannot obtain the temperature information TEMP3 of the flash memory control circuit 640 (or the solid-state storage device 20). Moreover, transmitting the temperature information TEMP3 of the flash memory control circuit 640 to the host 50 in real time through the bus 58 may cause the host 50 to misjudge that the instantaneous temperature of the flash memory control circuit 640 is too high and immediately take relevant cooling measures, thereby affecting the performance of the solid-state storage device 600.

[0053] Figure 7 A flowchart of a method for monitoring the temperature information of a solid-state storage device according to an embodiment of the present invention. Please refer to Figure 1 and Figure 7 .

[0054] In step 710, a first temperature sensor and a second temperature sensor are used to respectively detect the first temperature information and the second temperature information of the PCIe physical layer and the flash memory control circuit. For example, the first temperature sensor and the second temperature sensor are respectively the temperature sensor 211 disposed on the PCIe physical layer 210 and the temperature sensor 241 disposed on the flash memory control circuit 240, and the first temperature information and the second temperature information respectively correspond to Figure 1 the temperature information TEMP1 and TEMP2 shown in

[0055] In step 720, the temperature information calculation circuit 250 calculates the average temperature information TA of the flash memory controller 200 within a predetermined period based on the first temperature information and the second temperature information using the temperature information. For example, the temperature information TEMP1 detected by the temperature sensor 211 and the temperature information TEMP2 detected by the temperature sensor 241 can be combined into the temperature information TEMP, for example, TEMP = (TEMP1, TEMP2). In addition, the temperature information calculation circuit 250 can calculate the average temperature information within a predetermined period as the average temperature information TA of the flash memory controller 200 based on the frequency period of the frequency signal CLK, the sampling period signal SP, and the number of D flip-flops 2501 - 250N. Details can be referred to Figure 2B the embodiments of

[0056] In step 730, in response to a configuration read packet from the host 10, the temperature information calculation circuit 250 loads the average temperature information TA into the buffer 222 of the above-mentioned PCIe media access control layer 220. For example, step 730 can be further divided into the following steps: in response to a configuration read packet from the host 10, the PCIe media access control layer 220 issues a request signal REQ to the temperature information calculation circuit 250; and in response to the request signal REQ, the temperature information calculation circuit 250 loads the average temperature information TA into the buffer 222 of the PCIe media access control layer 220. The request signal REQ is used to notify the temperature information calculation circuit 250 to load the currently calculated average temperature information TA of the flash memory controller 200 into the buffer 222, where the buffer 222 corresponds to the field 410 of the PCIe capability structure 400

[0057] In step 740, the PCIe media access control layer 220 returns the average temperature information TA stored in the buffer 222 to the host 10 through the PCIe bus 15. For example, the PCIe media access control layer 220 packages the average temperature information TA in the buffer 222 as a data completion packet and transmits the data completion packet to the host 10. The above data completion packet is, for example, a completion with data transaction layer packet defined by the PCIe standard.

[0058] In summary, the flash memory controller, solid-state storage device, and method for monitoring temperature information of a solid-state storage device provided by the present invention can use a delay chain of D flip-flops in a temperature information calculation circuit to store temperature information of different components detected by one or more temperature sensors in the flash memory controller within a predetermined period, and can be combined with the design of a sampling period signal to adjust the sampling period. In addition, the average temperature information of the flash memory controller calculated by the temperature information calculation circuit can be stored in a register of a specific vendor capability structure in the PCIe configuration space, and the host can use a configuration read packet of the PCIe protocol to obtain the average temperature information from the flash memory controller through the PCIe bus. The above design can report the average temperature information of the flash memory controller within a predetermined period to the host through the PCIe bus. In addition to avoiding misjudgment by the host and taking cooling measures to limit the performance of the solid-state storage device, it is not necessary to use other buses other than the PCIe bus to report the average temperature information to the host, thereby increasing the performance of the computer system and reducing the design and maintenance difficulty and cost.

[0059] Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the relevant technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

[0060] Symbol Explanation

[0061] 1,6 Computer system

[0062] 10,50 Host

[0063] 15,55 PCIe bus

[0064] 16,17 Link

[0065] 20 Solid-state storage device

[0066] 21 PCIe signal

[0067] 22 NVMe signal

[0068] 23 Flash interface signal

[0069] 30 Flash memory

[0070] 56,57 Link

[0071] 58 Bus

[0072] 200,600 Flash memory controller

[0073] 210 PCIe physical layer

[0074] 211 Temperature Sensor

[0075] 220,620 PCIe Media Access Control Layer

[0076] 221 PCIe Configuration Space

[0077] 222 Register

[0078] 230,630 NVMe Protocol Conversion Circuit

[0079] 240,640 Flash Control Circuit

[0080] 241,641 Temperature Sensor

[0081] 250 Temperature Information Calculation Circuit

[0082] 2501 - 250N D-Type Flip-Flop

[0083] 2511 - 251N AND Gate

[0084] 2520 Adder

[0085] 2530 Divider

[0086] 300 PCIe Configuration Space

[0087] 302 Configuration Space File Header

[0088] 304,308 Configuration Space

[0089] 306 PCIe Capability Structure

[0090] 310 PCIe Extended Configuration Space

[0091] 312 PCI Configuration Space

[0092] 3021 Capability Index

[0093] 400 PCIe Capability Structure

[0094] 402 - 410 Fields

[0095] 500 Process

[0096] 502 - 508 Steps

[0097] 650 Bus Controller

[0098] 700 Method

[0099] 710 - 740 Steps

[0100] TX0, TX1 Transmitting End

[0101] RX0, RX1 Receiver

[0102] TEMP, TEMP1, TEMP2, TEMP3 Temperature Information

[0103] TA Average Temperature Information

[0104] REQ Request Signal

[0105] CLK Frequency Signal

[0106] SP Sampling Period Signal

[0107] S1~SN Temperature Signal

[0108] SUM Total Value

[0109] CK Frequency Input Terminal

[0110] D Data Input Terminal

[0111] Q Data Output Terminal

Claims

1. A flash memory controller, comprising: A high-speed peripheral component interconnect (PCIe) physical layer configured to be electrically connected to a host through a PCIe bus, wherein the PCIe physical layer includes a first temperature sensor for detecting first temperature information of the PCIe physical layer; A PCIe media access control layer electrically connected to the PCIe physical layer and configured to convert access instructions from the host into PCIe signals; A non-volatile memory communication protocol (NVMe) conversion circuit configured to convert the PCIe signals from the PCIe media access control layer into NVMe signals; A flash memory control circuit configured to control data access of a flash memory according to the NVMe signals, wherein the flash memory control circuit includes a second temperature sensor for detecting second temperature information of the flash memory control circuit; And A temperature information calculation circuit configured to calculate average temperature information of the flash memory controller within a predetermined period according to the first temperature information and the second temperature information; Wherein, in response to a configuration read packet from the host, the temperature information calculation circuit is configured to load the average temperature information into a buffer of the PCIe media access control layer, and the PCIe media access control layer reports the average temperature information stored in the buffer to the host through the PCIe bus.

2. The flash memory controller according to claim 1, wherein the temperature information calculation circuit is further configured to combine the first temperature information and the second temperature information into third temperature information, and calculate an average value of the third temperature information according to a frequency signal and a sampling period signal of the flash memory controller to obtain the average temperature information.

3. The flash memory controller according to claim 2, wherein the temperature information calculation circuit includes: N D flip-flops connected in series in sequence to form a delay chain to receive the third temperature information, where N is a positive integer, and the width of the sampling period signal is N bits; N AND gates, each of which includes: a first input terminal connected to a data output terminal of the corresponding D flip-flop and a second input terminal receiving a corresponding bit of the sampling period signal to generate a corresponding temperature signal; An adder for summing the corresponding temperature signals generated by each AND gate to obtain a sum value; and A divider for dividing the sum value by an effective number to obtain the average temperature information.

4. The flash memory controller according to claim 3, wherein the predetermined period is N times the frequency period of the frequency signal.

5. The flash memory controller according to claim 3, wherein the effective number is the number of bits equal to 1 in the sampling period signal.

6. The flash memory controller according to claim 5, wherein in response to the configuration read packet, the PCIe media access control layer is further configured to issue a request signal to the temperature information calculation circuit, and in response to the request signal, the temperature information calculation circuit further loads the average temperature information into the buffer of the PCIe media access control layer.

7. The flash memory controller as claimed in claim 6, wherein the average temperature information includes a first average value of the first temperature information within the predetermined period and a second average value of the second temperature information within the predetermined period.

8. The flash memory controller as claimed in claim 1, wherein a PCIe configuration space of the PCIe media access control layer includes a PCIe capability structure for defining a vendor - specific capability of the flash memory controller to support reporting the average temperature information, and the PCIe capability structure includes the buffer.

9. The flash memory controller as claimed in claim 8, wherein in response to a specific address of the configuration read packet pointing to the buffer, the temperature information calculation circuit loads the average temperature information into the buffer, and the PCIe media access control layer packages the average temperature information stored in the buffer into a data completion packet and reports the data completion packet to the host via the PCIe bus.

10. The flash memory controller as claimed in claim 9, wherein the configuration read packet is a configuration read exchange layer packet of the PCIe protocol, and the data completion packet is a data completion exchange layer packet of the PCIe protocol.

11. A method for monitoring temperature information of a solid - state storage device, wherein the solid - state storage device is electrically connected to a host via a Peripheral Component Interconnect Express (PCIe) bus, and a flash memory controller of the solid - state storage device includes a PCIe physical layer, a PCIe media access control layer, a flash memory control circuit, and a temperature information calculation circuit. The method includes: Using a first temperature sensor disposed in the PCIe physical layer and a second temperature sensor disposed in the flash memory control circuit to respectively detect first temperature information of the PCIe physical layer of the flash memory controller and second temperature information of the flash memory control circuit; Using the temperature information calculation circuit to calculate average temperature information of the flash memory controller within a predetermined period based on the first temperature information and the second temperature information; In response to a configuration read packet from the host, using the temperature information calculation circuit to load the average temperature information into a buffer of the PCIe media access control layer; And Using the PCIe media access control layer to report the average temperature information stored in the buffer to the host via the PCIe bus.

12. The method as claimed in claim 11, further comprising: Using the temperature information calculation circuit to combine the first temperature information and the second temperature information into third temperature information, and calculating an average value of the third temperature information based on a frequency signal and a sampling period signal of the flash memory controller to obtain the average temperature information.

13. The method as claimed in claim 12, further comprising: Using a delay chain formed by N D - type flip - flops to receive the third temperature information, where N is a positive integer and the width of the sampling period signal is N bits; Selecting corresponding third temperature information on the delay chain according to each valid bit of the sampling period signal to generate a temperature signal. Sum the temperature signals corresponding to the respective valid bits to obtain a sum value; and Divide the sum value by the number of valid signals of the sampling period signal to obtain the average temperature information.

14. The method according to claim 13, wherein the predetermined period is N times the frequency period of the frequency signal, and the number of valid signals is the number of bits equal to 1 in the sampling period signal.

15. The method according to claim 14, wherein in response to a configuration read packet from the host, the step of loading the average temperature information into a buffer of the PCIe media access control layer by the temperature information calculation circuit includes: In response to the configuration read packet, using the PCIe media access control layer to issue a request signal to the temperature information calculation circuit; and In response to the request signal, using the temperature information calculation circuit to load the average temperature information into the buffer of the PCIe media access control layer.

16. The method according to claim 15, wherein the average temperature information includes a first average value of the first temperature information during the predetermined period and a second average value of the second temperature information during the predetermined period.

17. The method according to claim 11, wherein the PCIe configuration space of the PCIe media access control layer includes a PCIe capability structure for defining a vendor-specific capability of the flash controller to support reporting the average temperature information, and the PCIe capability structure includes the buffer.

18. The method according to claim 17, further comprising: In response to a specific address of the configuration read packet pointing to the buffer, using the temperature information calculation circuit to load the average temperature information into the buffer; and Using the PCIe media access control layer to package the average temperature information stored in the buffer into a data completion packet, and reporting the data completion packet to the host via the PCIe bus.

19. The method according to claim 18, wherein the configuration read packet is a configuration read exchange layer packet of the PCIe protocol, and the data completion packet is a data completion exchange layer packet of the PCIe protocol.

20. A solid-state storage device, comprising: Flash memory; and A flash memory controller electrically connected to the flash memory, wherein the flash memory controller includes: A high-speed peripheral component interconnect (PCIe) physical layer configured to be electrically connected to a host via a PCIe bus, wherein the PCIe physical layer includes a first temperature sensor for detecting first temperature information of the PCIe physical layer; A PCIe media access control layer electrically connected to the PCIe physical layer and configured to convert an access instruction from the host into a PCIe signal; A non-volatile memory communication protocol (NVMe) conversion circuit configured to convert the PCIe signal from the PCIe media access control layer into an NVMe signal; A flash memory control circuit configured to control data access of the flash memory according to the NVMe signal; and A temperature information calculation circuit configured to calculate average temperature information of the flash memory controller within a predetermined period based on the first temperature information and the second temperature information; Wherein, in response to a configuration read packet from the host, the temperature information calculation circuit is configured to load the average temperature information into a buffer of the PCIe media access control layer, and the PCIe media access control layer reports the average temperature information stored in the buffer to the host through the PCIe bus.

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