Data transmission method, electronic device, storage medium and program product

Abstract

The present application discloses a data transmission method, electronic device, storage medium and program product, which relate to the field of computer technology. The method includes the following steps: when data transmission is required, the device side can receive first information corresponding to a direct memory access module sent by a processor based on a bus, the first information being configuration information or operation information; determining the type of the first information, the type of the first information being used to indicate that the first information is configuration information or operation information; storing the first information in a memory according to the type of the first information; and transmitting the data based on the first information in the memory in response to a data transmission instruction sent by the processor. In this way, the first information does not need to be stored in the memory of the processor, but is directly sent to the device side, which then stores the first information, thereby avoiding the problem of low memory usage caused by the storage of the first information during processing.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data transmission method, electronic equipment, storage medium, and program product. Background Art

[0002] During the data transfer process, data can be transferred through a Direct Memory Access (DMA) controller.

[0003] In related technologies, descriptors are allocated in host-side memory, and the transfer information for discrete memory blocks is populated into multiple descriptors. A direct memory access controller then sequentially transfers data based on the information in the descriptors until all descriptors are executed, completing the data transfer. However, in this process, a new descriptor must be allocated for each transfer, resulting in low memory usage. Summary of the Invention

[0004] The present application provides a data transmission method, electronic device, storage medium and program product to at least solve the problem of low memory usage.

[0005] This application provides a data transmission method, including:

[0006] receiving first information corresponding to the direct memory access module sent by the processor based on the bus, where the first information is configuration information or operation information, the configuration information is used to indicate an address for reading and writing data in the processor, and the operation information is used to indicate a data transmission strategy;

[0007] Storing the first information in a memory;

[0008] In response to the data transmission instruction sent by the processor, the data is transmitted based on the first information in the memory.

[0009] The present application also provides a data transmission device, comprising: a receiving module, a storage module and a transmission module, wherein:

[0010] The receiving module is used to receive first information corresponding to the direct memory access module sent by the processor based on the bus, where the first information is configuration information or operation information, the configuration information is used to indicate an address for reading and writing data in the processor, and the operation information is used to indicate a data transmission strategy;

[0011] The storage module is used to store the first information in the memory;

[0012] The transmission module is configured to transmit data based on the first information in the memory in response to a data transmission instruction sent by the processor.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data transmission methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data transmission methods are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned data transmission methods when executed by a processor.

[0016] Through this application, when data transmission is required, the first information corresponding to the direct memory access module sent by the processor based on the bus is received, the first information is configuration information or operation information, the configuration information is used to indicate the address where data is read and written in the processor, and the operation information is used to indicate the data transmission strategy; the first information is stored in the memory; in response to the data transmission instruction sent by the processor, the data is transmitted based on the first information in the memory. In this way, through the above method, there is no need to store the first information in the host-side memory, but it is sent directly to the device side, thereby reducing the discrete memory of the host side, improving the utilization rate of the host-side memory, and preventing the first information from being discretely stored in the host-side memory, thereby causing memory leakage problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic diagram of the system architecture provided in an embodiment of the present application;

[0019] Figure 2 A flowchart of a data transmission method provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the data transmission process provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a process for a direct memory access controller according to an embodiment of the present application to process operation information;

[0022] Figure 5 A schematic diagram of the structure of data transmission provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the interaction of data transmission provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0025] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0028] First, let’s explain the terms involved in this application:

[0029] Direct Memory Access (DMA): DMA allows external devices (such as hard drives, graphics cards, and network cards) to exchange data directly with computer memory without passing through the central processing unit (CPU). Through DMA, external devices can transfer data directly to and read data from memory, significantly reducing the CPU's burden and improving data transfer efficiency and overall computer performance.

[0030] Field-Programmable Gate Array (FPGA): An FPGA is an integrated circuit that can be programmed and configured at the hardware level. It allows users to customize its internal logic structure through programming to achieve specific functional requirements. This makes the FPGA extremely flexible and customizable in design, allowing it to adapt to different application scenarios.

[0031] Field Programmable Gate Array (FPGA) Accelerator: A FPGA accelerator is a hardware accelerator that leverages the flexibility and parallel processing capabilities of field-programmable gate arrays (FPGAs) to accelerate specific computing tasks. By converting computationally intensive tasks (such as machine learning inference, big data processing, and image recognition) into hardware-level parallel operations, FPGA accelerators can significantly improve processing speed and efficiency. In this accelerator, the FPGA is programmed to perform specific functions without relying on the central processing unit (CPU) to perform all calculations, thereby reducing latency, lowering power consumption, and improving overall performance.

[0032] In related technologies, descriptors are allocated in host-side memory, and the transfer information for discrete memory blocks is populated into multiple descriptors. A direct memory access controller then sequentially transfers data based on the information in the descriptors until all descriptors are executed, completing the data transfer. However, in this process, a new descriptor must be allocated for each transfer, resulting in low memory usage.

[0033] In response to the above-mentioned problem, in an embodiment of the present application, when data transmission is required, the device side can receive the first information corresponding to the direct memory access module sent by the processor based on the bus, where the first information is configuration information or operation information. The configuration information is used to indicate the address at which data is read and written in the processor, and the operation information is used to indicate the data transmission strategy; determine the type of the first information, where the type of the first information is used to indicate that the first information is configuration information or operation information; store the first information in the memory according to the type of the first information; and transmit the data based on the first information in the memory in response to the data transmission instruction sent by the processor. In this way, the first information does not need to be stored in the processor's memory, but is sent directly to the device side, which then stores the first information, thereby avoiding the problem of low memory utilization caused by the storage of the first information during processing.

[0034] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the data transmission method depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1 , Figure 1 This is a schematic diagram of the system architecture provided by the embodiment of this application. Figure 1, including a host side 101 and a device side 102. The host side 101 may be a central processing unit of an electronic device, the device side 102 may be a field programmable gate array accelerator, and the electronic device may be any device with on-device computing capabilities, such as a server, a terminal device, etc. The device side 102 may include a direct memory access controller, which can be used to transmit data from the host side 101 to the device side 102, and can also be used to transmit data from the device side 102 to the host side 101.

[0036] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0037] Figure 2 A flow chart of a data transmission method provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, an embodiment of the present application provides a data transmission method, which is described in detail as follows:

[0038] S201: Receive first information corresponding to a direct memory access module sent by a processor based on a bus.

[0039] The execution subject of the embodiments of the present application may be an electronic device or a device terminal in the electronic device. The device terminal may be a field programmable gate array accelerator, a hard disk, a graphics processing unit, a camera, an audio processing card, etc. The execution subject may also be a data transmission device provided in the device terminal. The data transmission device may be implemented by software or a combination of software and hardware.

[0040] The processor may refer to the host side. Data transmission may refer to the data transmission between the host side and the device side.

[0041] A bus can be used for communication between a processor and a device. A bus can refer to a bus control module, for example, a system management bus (SMBus) control module.

[0042] The direct memory access module can be used for data transmission between the device side and the host side.

[0043] The first information may be configuration information or operation information.

[0044] The configuration information may be used to indicate the address at which data is read and written in the processor. The configuration information may include at least one of the following: the address information of the memory used for data transmission corresponding to the direct memory access module, and / or the size of the memory used for data transmission corresponding to the direct memory access module.

[0045] Among them, when initializing the processor, the processor needs to apply for multiple memory spaces in the memory. The memory space can be used to store data to be transmitted, and can also be used to store received data. The address information of the memory space is the address information of the memory for data transmission, and the size of the memory space is the size of the memory for data transmission.

[0046] For example, for any read / write address, the configuration information may be: 0x0001, 128 kb.

[0047] The operation information can be used to indicate the data transmission strategy.

[0048] The operation information may include at least one of the following: a first address, a second address, and / or a transmission length transmitted by the direct memory access module. The first address is used to indicate the source address of the direct memory access module's transmission. The second address is used to indicate the destination address of the direct memory access module's transmission. The operation information may be transmitted in the form of an array. Optionally, the operation information may include arrays corresponding to multiple first addresses, multiple second addresses, and / or multiple transmission lengths; or it may include arrays corresponding to the first address, second address, and / or transmission lengths.

[0049] The source address refers to the starting location of data transmission, i.e., the DMA module transmits the data at the source address. The source address can be either the device address or the host address. The destination address refers to the final location of data transmission, i.e., the location where the DMA module writes the data. The destination address can be either the device address or the host address. The transfer length refers to the size of the data being transferred. The source and destination addresses can be used to determine the direction of data transmission, i.e., whether the data is from the host to the device or from the device to the host.

[0050] For example, the operation information may be: source address 0x1000, destination address 0x80000000, and transfer length 4MB.

[0051] S202: Store the first information in a memory.

[0052] Memory refers to the storage space on a device. Memory can include a cache module and a storage module. The cache module can be used to store frequently accessed data or temporarily stored data. The storage module can be used to store persistent data, meaning data that requires long-term storage.

[0053] The first information can be stored in the following manner: the device side determines the type of the first information, and the type of the first information is used to indicate that the first information is configuration information or operation information; according to the type of the first information, when the type of the first information indicates that the first information is configuration information, the first information is stored in the storage module; when the type of the first information indicates that the first information is operation information, the first information is stored in the cache module.

[0054] That is, the device side stores the configuration information in the storage module and stores the operation information in the cache module.

[0055] Optionally, the first information may be a preset protocol type, which may include a frame header field, a frame type field, a length field, a data field, a frame tail field, a check field, and the like.

[0056] The frame header field can be used to identify the beginning of a frame (i.e., the first information); the frame type field can be used to indicate the type of the first information. For example, if the first information is configuration information, the frame type field of the first information can be 0x0001; if the first information is operation information, the frame type field of the first information can be 0x0002. Thus, by obtaining the frame type field of the first information, the type of the first information, i.e., whether it is configuration information or operation information, can be determined; the length field can be used to indicate the length of the data field; the data field can be used to indicate the actual data being transmitted; the frame tail field can be used to identify the end of the frame (i.e., the first information); and the checksum field can be a checksum value of the first information, used to ensure the correctness of data transmission.

[0057] For example, assuming that the frame type field is 0x0001, it indicates that the first information is configuration information, and the frame type field is 0x0002, it indicates that the first information is operation information. The first information can be as shown in Table 1.

[0058] Table 1

[0059]

[0060] According to the frame type shown in Table 1 being 0x0001, it can be determined that the first information is configuration information.

[0061] For example, assuming that the frame type field is 0x0001, it indicates that the first information is configuration information, and the frame type field is 0x0002, it indicates that the first information is operation information. The first information may be as shown in Table 2.

[0062] Table 2

[0063]

[0064] According to the frame type shown in Table 2 being 0x0002, it can be determined that the first information is operation information.

[0065] S203: In response to the data transmission instruction sent by the processor, transmit the data based on the first information in the memory.

[0066] The data transmission instruction may be used to instruct the direct memory access module to transmit data according to the first information in the memory.

[0067] For example, assuming that based on the first information in the memory, it can be determined that the configuration information indicates that memory space 1, memory space 2 and memory space 3 exist in the processor, and the operation information indicates that the data of memory space 1 is transferred to the memory on the device side, then the direct memory access module responds to the data transfer instruction sent by the processor and transfers the data of memory space 1 to the memory on the device side.

[0068] Assuming that based on the first information in the memory, it can be determined that the configuration information indicates that memory space 1, memory space 2 and memory space 3 exist in the processor, and the operation information indicates that the memory data on the device side is transferred to memory space 2, then the direct memory access module responds to the data transfer instruction sent by the processor and transfers the memory data on the device side to memory space 2.

[0069] In an embodiment of the present application, when a direct memory access module needs to transmit data, it can receive first information corresponding to the direct memory access module sent by the processor based on the bus, the first information can be configuration information or operation information, the configuration information can be used to indicate the address of the data to be read and written in the processor, the configuration information can include the address information of the memory used for the data transmission corresponding to the direct memory access module, and / or the size of the memory used for the data transmission corresponding to the direct memory access module, the operation information can be used to indicate the transmission strategy of the data, the operation information can include the first address, the second address, and / or the transmission length transmitted by the direct memory access module; the first information is stored in the memory, the memory can include a cache module and a storage module, the configuration information is stored in the storage module, and the operation information is stored in the cache module; in response to the data transmission instruction sent by the processor, the data is transmitted based on the first information in the memory. In this way, through the above method, the first information used to indicate the data transmission can be stored in the memory without occupying the host-side memory space, thereby improving the utilization rate of the host-side memory, and at the same time, the configuration information and the operation information are distinguished by the frame type field and stored separately, thereby improving the utilization rate of the device-side storage space.

[0070] Based on any of the above embodiments, Figure 3, the data transmission process is described in detail.

[0071] Figure 3 This is a schematic diagram of the data transmission process provided in the embodiment of this application. Figure 3 , the method may include:

[0072] S301: Obtain configuration information and operation information from a memory.

[0073] The memory includes a storage module and a cache module, that is, the device side can obtain configuration information from the storage module and obtain operation information from the cache module.

[0074] S302: Determine whether data can be transmitted based on the configuration information and the operation information.

[0075] Whether data can be transmitted can be determined in the following way: obtain the address indicated by the configuration information and the address indicated by the operation information, and determine whether the address indicated by the configuration information matches the address indicated by the operation information. If they match, it is determined that the data can be transmitted; if not, it is determined that the data cannot be transmitted.

[0076] For example, assuming that for any data transmission, the addresses indicated by the configuration information are address A, address B and address C, and the operation information indicates that the data in the device-side memory is transferred to address B, it can be determined that the address indicated by the configuration information and the address indicated by the operation information match, that is, it is determined that the data can be transmitted; assuming that for any data transmission, the addresses indicated by the configuration information are address A, address B and address C, and the operation information indicates that the data in the device-side memory is transferred to address D, it can be determined that the address indicated by the configuration information and the address indicated by the operation information do not match, that is, it is determined that the data cannot be transmitted.

[0077] Optionally, the matching may also include determining whether the size of the memory space matches. Assuming that for any data transmission, the addresses indicated by the configuration information are address A, address B and address C, wherein the size of the memory space of address A is 10KB, the size of the memory space of address B is 20KB, and the size of the memory space of address C is 30KB, and the operation information indicates that 15KB of data in the device-side memory is transferred to address B, then it can be determined that the size of the memory space indicated by the configuration information and the size of the memory space indicated by the operation information match, that is, it is determined that the data can be transmitted; assuming that for any data transmission, the addresses indicated by the configuration information are address A, address B and address C, wherein the size of the memory space of address A is 10KB, the size of the memory space of address B is 20KB, and the size of the memory space of address C is 30KB, and the operation information indicates that 50KB of data in the device-side memory is transferred to address B, then it can be determined that the size of the memory space indicated by the configuration information and the size of the memory space indicated by the operation information do not match, that is, it is determined that the data cannot be transmitted.

[0078] S303: When the data can be transmitted, determine the transmission type of the data based on the operation information.

[0079] The transfer type may include a read operation type and a write operation type.

[0080] A read operation type refers to the device reading data from the host. Read operations flow from the host to the device. Based on the source and destination addresses of the operation information, when the source address is a host address and the destination address is a device address, the current transfer type is determined to be a read operation. This means the DMA controller can retrieve data from the host source address and then transfer the data to the device destination address.

[0081] For example, a read operation can refer to a network interface card reading a data packet to be sent from the host memory; a graphics card reading texture data from the host memory.

[0082] A write operation type can refer to the device writing data to the host. The data flow for a write operation is from the device to the host. Based on the source and destination addresses of the operation information, when the source address is a device address and the destination address is a host address, the current transfer type can be determined to be a write operation. In other words, the DMA controller can retrieve data from the source address on the device and then transfer the data to the destination address on the host.

[0083] For example, a write operation can mean that a disk controller writes data read from a disk to host memory; a device writes collected data (such as sensor data) or status information reports to host memory.

[0084] S304: Determine whether the transmission type is a read operation type.

[0085] If so, execute S305.

[0086] If not, execute S306.

[0087] S305 : The controller based on the read operation processes the operation information and transmits the data.

[0088] The direct memory access controller may include a controller for read operations and a controller for write operations.

[0089] The read operation controller further includes a read operation queue reading module, a read operation configuration information control module and a read operation configuration receiving module.

[0090] The following describes a process in which the controller of a read operation processes operation information through a specific example.

[0091] Figure 4 This is a schematic diagram of the process of processing operation information by the direct memory access controller provided in the embodiment of the present application. Figure 4 The device end may include a microcontroller and a field programmable gate array accelerator, wherein the microcontroller may include a cache module and a low-speed interface, the field programmable gate array accelerator may include a low-speed interface, a direct memory access controller, a read operation mover and a write operation mover, the low-speed interface may include a read operation control interface and a write operation control interface, the direct memory access controller may include a read operation queue reading module, a read operation configuration information control module, a read operation configuration receiving module, a write operation queue reading module, a write operation configuration information control module and a write operation configuration receiving module, the read operation mover may include a read operation control signal receiving module and a read operation status sending module, and the write operation mover may include a write operation control signal receiving module and a write operation status sending module.

[0092] When it is determined that the transmission type is a read operation, the device side can transmit the operation information in the cache module to the read operation control interface of the field programmable gate array accelerator through the read operation control interface of the microcontroller. After receiving the operation information, the field programmable gate array accelerator transmits the operation information to the read operation queue reading module of the direct memory access controller. The read operation queue reading module transmits the operation information to the read operation configuration information control module in queue order. The read operation configuration information control module then transmits the operation information to the read operation control signal receiving module of the read operation mover. After receiving the operation information, the read operation control signal receiving module performs a read operation according to the operation information. After the read operation is completed, the status of the read operation is transmitted to the read operation configuration receiving module of the direct memory access controller through the read operation status sending module for status recording.

[0093] S306: The controller based on the write operation processes the operation information and transmits the data.

[0094] The controller for write operations also includes a write operation queue reading module, a write operation configuration information control module, and a write operation configuration receiving module.

[0095] The following describes a process in which the controller of a write operation processes operation information through a specific example.

[0096] See Figure 4 When it is determined that the transmission type is a write operation, the device side can transmit the operation information in the cache module to the write operation control interface of the field programmable gate array accelerator through the write operation control interface of the microcontroller. After the field programmable gate array accelerator receives the operation information, it transmits the operation information to the write operation queue reading module of the direct memory access controller. The write operation queue reading module transmits the operation information to the write operation configuration information control module in queue order. The write operation configuration information control module then transmits the operation information to the write operation control signal receiving module of the write operation mover. After receiving the operation information, the write operation control signal receiving module performs a write operation according to the operation information. After the write operation is completed, the status of the write operation is transmitted to the write operation configuration receiving module of the direct memory access controller through the write operation status sending module for status recording.

[0097] exist Figure 3 In the illustrated embodiment, when data needs to be transmitted, the device can obtain configuration information from the storage module and operation information from the cache module. Based on the configuration information and the operation information, the device obtains the address indicated by the configuration information and the address indicated by the operation information, and determines whether the address indicated by the configuration information matches the address indicated by the operation information. If they match, the data is determined to be capable of transmission; if they do not match, the data is determined to be incapable of transmission. When data can be transmitted, the data transmission type is determined based on the operation information. The transmission type may include a read operation type and a write operation type. When the transmission type is a read operation type, a controller based on the read operation processes the operation information and transmits the data. When the transmission type is a write operation type, a controller based on the write operation processes the operation information and transmits the data. In this way, whether the address matches can be determined in advance based on the configuration information and the operation information, and data transmission is performed only when the address matches, thereby preventing data transmission failures caused by address mismatches. At the same time, during data transmission, the read operation type and the write operation type are separated according to the data transmission type to prevent transmission conflicts between the read and write operations, thereby improving data transmission efficiency.

[0098] Based on any of the above embodiments, Figure 5, which explains the structure of data transmission in detail.

[0099] Figure 5 This is a schematic diagram of the data transmission structure provided in the embodiment of this application. Figure 5 , including a host side and a device side, wherein the host side may include an application layer and a driver layer, the driver layer includes a bus and a transmission module, the device side may include a transmission interface, a microcontroller, a field programmable gate array accelerator and a memory, the microcontroller includes a receiving module, a storage module, a cache module, a control module and a low-speed interface, the field programmable gate array accelerator includes a low-speed interface, a direct memory access controller and a direct memory access mover.

[0100] When data transmission is required, the driver layer on the host side can apply for multiple memory spaces in the transmission module, and send the configuration information and operation information of the memory space to the transmission interface on the device side through the bus, and transmit it to the receiving module through the transmission interface. The receiving module determines whether the received information is configuration information or operation information based on the type of the first information, and sends the configuration information to the storage module for storage, and sends the operation information to the cache module for storage. When data transmission is performed, the control module can send the configuration information in the storage module to the cache module. The cache module sends the configuration information and operation information to the low-speed interface of the field programmable gate array accelerator through the low-speed interface, and transmits it to the direct memory access controller. The direct memory access controller sends the operation information to the direct memory access mover, so that the direct memory access mover performs corresponding data transmission operations on the memory.

[0101] Based on any of the above embodiments, Figure 6 , which explains the structure of data transmission in detail.

[0102] Figure 6 This is a diagram of the interaction of data transmission provided in the embodiment of this application. Figure 6 ,include:

[0103] S1. The host obtains configuration information and operation information.

[0104] S2. The host sends the configuration information and operation information to the device through the bus.

[0105] S3. The device stores the configuration information in the storage module and the operation information in the cache module.

[0106] S4. The device determines whether the data can be transmitted based on the configuration information and operation information.

[0107] S5. The device determines whether the transfer can be performed and determines the operation type.

[0108] S6. When the operation type of the device is a read operation type, the controller based on the read operation processes the operation information and transmits the data; when the operation type is a write operation type, the controller based on the write operation processes the operation information and transmits the data.

[0109] Figure 7 This is a schematic diagram of the structure of the data transmission device provided in the embodiment of the present application. Figure 7 As shown, the embodiment of the present application further provides a data transmission device 10, comprising: a receiving module 11, a storage module 12 and a transmission module 13, wherein:

[0110] The receiving module 11 is used to receive first information corresponding to the direct memory access module sent by the processor based on the bus, where the first information is configuration information or operation information, where the configuration information is used to indicate an address at which data is read and written in the processor, and the operation information is used to indicate a transmission strategy for the data;

[0111] The storage module 12 is used to store the first information in a memory;

[0112] The transmission module 13 is configured to transmit the data based on the first information in the memory in response to the data transmission instruction sent by the processor.

[0113] A data transmission device provided in an embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0114] In one possible design, the storage module 12 is specifically used to:

[0115] determining a type of the first information, where the type of the first information is used to indicate that the first information is the configuration information or the operation information;

[0116] The first information is stored in the memory according to the type of the first information.

[0117] In one possible design, the storage module 12 is specifically used to:

[0118] When the type of the first information indicates that the first information is the configuration information, storing the first information in the storage module;

[0119] When the type of the first information indicates that the first information is the operation information, the first information is stored in the cache module.

[0120] In one possible design, the receiving module 11 is specifically configured to: the configuration information includes at least one of the following:

[0121] Address information of the memory used for data transmission corresponding to the direct memory access module;

[0122] The size of the memory used for data transmission corresponding to the direct memory access module.

[0123] In one possible design, the receiving module 11 is specifically configured to transmit the operation information in an array-based form, where the operation information includes at least one of the following:

[0124] a first address, the first address being used to indicate a source address of a transmission of the direct memory access module;

[0125] a second address, the second address being used to indicate a destination address of a transmission of the direct memory access module;

[0126] The transmission length of the data.

[0127] In one possible design, the transmission module 13 is specifically configured to:

[0128] Retrieving the configuration information and the operation information from the memory;

[0129] Determining whether the data can be transmitted based on the configuration information and the operation information;

[0130] When the data can be transmitted, the data is transmitted based on the operation information.

[0131] In one possible design, the transmission module 13 is specifically configured to:

[0132] Determining a transmission type of the data based on the operation information, where the transmission type is a read operation type and a write operation type;

[0133] When the transmission type is a read operation type, the controller based on the read operation processes the operation information and transmits the data;

[0134] When the transmission type is a write operation type, the controller based on the write operation processes the operation information and transmits the data.

[0135] In one possible design, the transmission module 13 is specifically configured to:

[0136] determining whether the address indicated by the configuration information matches the address indicated by the operation information;

[0137] If they match, it is determined that the data can be transmitted;

[0138] If there is no match, it is determined that the data cannot be transmitted.

[0139] A data transmission device provided in an embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0140] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 8 As shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus.

[0141] During the specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that the at least one processor 501 executes the above-mentioned data transmission method embodiment.

[0142] The specific implementation process of the processor 501 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0143] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0144] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0145] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0146] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned data transmission method embodiments when running.

[0147] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0148] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned data transmission method embodiments are implemented.

[0149] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data transmission method embodiments are implemented.

[0150] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0151] The above is a detailed introduction to a data transmission method, electronic device, storage medium and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data transmission method, characterized in that: include: receiving first information corresponding to a direct memory access module sent by a processor based on a bus, the first information being configuration information or operation information, the configuration information being used to indicate an address at which data is read and written in the processor, and the operation information being used to indicate a transmission strategy for the data; the operation information being transmitted in the form of an array, so that the first information does not need to be stored in a memory of the processor but is directly sent to a device end; determining a type of the first information, where the type of the first information is used to indicate that the first information is the configuration information or the operation information; When the type of the first information indicates that the first information is the configuration information, persistently storing the first information in a storage module in a memory; When the type of the first information indicates that the first information is the operation information, temporarily storing the first information in a cache module in the memory; In response to the data transmission instruction sent by the processor, the data is transmitted based on the first information in the memory.

2. The method according to claim 1, characterized in that The configuration information includes at least one of the following: Address information of the memory used for data transmission corresponding to the direct memory access module; The size of the memory used for data transmission corresponding to the direct memory access module.

3. The method according to claim 1, characterized in that The operation information is transmitted in the form of an array, and includes at least one of the following: a first address, the first address being used to indicate a source address of a transmission of the direct memory access module; a second address, the second address being used to indicate a destination address of a transmission of the direct memory access module; The transmission length of the data.

4. The method according to claim 1, wherein Transmitting the data based on the first information in the memory includes: Retrieving the configuration information and the operation information from the memory; Determining whether the data can be transmitted based on the configuration information and the operation information; When the data can be transmitted, the data is transmitted based on the operation information.

5. The method according to claim 4, characterized in that Transmitting the data based on the operation information includes: Determining a transmission type of the data based on the operation information, where the transmission type is a read operation type and a write operation type; When the transmission type is a read operation type, the controller based on the read operation processes the operation information and transmits the data; When the transmission type is a write operation type, the controller based on the write operation processes the operation information and transmits the data.

6. The method according to claim 5, characterized in that Determining whether the data can be transmitted based on the configuration information and the operation information includes: determining whether the address indicated by the configuration information matches the address indicated by the operation information; If they match, it is determined that the data can be transmitted; If there is no match, it is determined that the data cannot be transmitted.

7. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data transmission method according to any one of claims 1 to 6 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 6 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 6 are implemented.

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