Data processing device suitable for a PCIe link and communication system having the same

Abstract

The application discloses a data processing device suitable for a PCIe link and a communication system with the same. The core PCIe channel module of the processing device comprises a first PCIe input interface for receiving upstream PCIe data; a first data enhancement unit for enhancing the upstream PCIe data to obtain physical layer encoding data flow; a data storage unit for receiving and storing the data output by the first data enhancement unit through a first path; a first data selector, a first data input end of which receives the data output by the first data enhancement unit through a second path, and a second data input end of which receives the data stored in the data storage unit through a third path; a control unit for controlling the first data selector to select and output the data received by one of the first data input end and the second data input end; and a first PCIe output interface for sending the data output by the first data selector to a downstream PCIe device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of PCIe communication, and in particular to a data processing device suitable for a PCIe link and a communication system having the same. BACKGROUND

[0002] PCI Express (PCIe) is a high-speed serial computer expansion bus standard, which is widely used in the fields of servers, storage, networks, etc. With the continuous improvement of PCIe speed, signal integrity problems are increasingly prominent, and a re-timer is introduced to restore signal quality and extend transmission distance. However, in some scenarios with extremely high data reliability requirements, relying solely on the re-timer to ensure signal physical layer quality may not be sufficient to cope with all data transmission risks, such as burst errors caused by instantaneous link interference or upstream device failure. In the prior art, data protection is usually implemented at a higher layer of the protocol stack or at the system level, and there is a lack of an effective solution to integrate signal conditioning and lightweight data backup and recovery in the intermediate node of the PCIe physical link.

[0003] The disclosure of the above background art content is only used to assist in understanding the concept and technical solutions of the present application, and it does not necessarily belong to the prior art of the present application, nor does it necessarily give technical teaching; in the absence of explicit evidence that the above content has been disclosed before the filing date of the present application, the above background art should not be used to evaluate the novelty and inventiveness of the present application. SUMMARY

[0004] The purpose of the present application is to provide a data processing device suitable for a PCIe link and a communication system having the same, to improve the data transmission reliability and fault tolerance of the PCIe link.

[0005] To achieve the above purpose, the technical solutions adopted by the present application are as follows:

[0006] A data processing device suitable for a PCIe link, comprising at least one PCIe channel module, each PCIe channel module being configured with:

[0007] a first PCIe input interface configured to receive PCIe upstream data of an upstream first PCIe device;

[0008] a first data enhancement unit configured to perform data enhancement on the PCIe upstream data to obtain a physical layer encoded data stream;

[0009] a data storage unit configured to receive and store the physical layer encoded data stream output by the first data enhancement unit through a first path;

[0010] a first data selector with multiple data inputs, a first data input of which is configured to receive a physical layer encoded data stream output by the first data enhancement unit through a second path, and a second data input of which is configured to receive a physical layer encoded data stream stored in the data storage unit through a third path;

[0011] a control unit configured to send a selection signal to a selection end of the first data selector, the selection signal being used to select one of the first data input and the second data input of the first data selector to output data received thereby;

[0012] a first PCIe output interface configured to send data output by the first data selector to a second PCIe device downstream.

[0013] Further, any of the technical solutions or combinations of the technical solutions described above, the data storage unit is configured with a write operation enable end and a read operation enable end, and the control unit is further connected to the write operation enable end and the read operation enable end;

[0014] If the control unit sends an enable signal to the write operation enable end, the first path is connected, otherwise the data storage unit stops receiving and storing data;

[0015] If the control unit sends an enable signal to the read operation enable end, the third path is connected, otherwise the data storage unit stops sending data to the second data input of the first data selector.

[0016] Further, any of the technical solutions or combinations of the technical solutions described above, the control unit executes different working modes according to a preset mode instruction, including:

[0017] If the mode instruction is to execute a normal working mode, the control unit sends a selection signal to the first data selector to select the first data input, and prohibits sending an enable signal to the write operation enable end and the read operation enable end;

[0018] If the mode instruction is to execute a data protection mode, the control unit sends a selection signal to the first data selector to select the first data input, sends an enable signal to the write operation enable end, and prohibits sending an enable signal to the read operation enable end;

[0019] If the mode instruction is to execute a data recovery mode, the control unit sends a selection signal to the first data selector to select the second data input, and sends an enable signal to the read operation enable end.

[0020] Further, any one of the above technical solutions or a combination of multiple technical solutions, the mode instruction for executing the data protection mode is configured to send to the control unit at a preset frequency;

[0021] Alternatively, the mode instruction for executing the normal operation mode or the data protection mode is configured to be sent to the control unit by a master controller outside the PCIe channel module.

[0022] Further, any one of the above technical solutions or a combination of multiple technical solutions, the continuous sequence numbers are allocated to each data packet of the data stream based on the PCIe link layer, and if the second PCIe device receives the data packet corresponding to the continuous sequence number, an ACK response signal is returned to the first PCIe device one by one in a one-to-one correspondence;

[0023] If the second PCIe device does not receive the data packet corresponding to the continuous next sequence number, an NACK response signal is sent to the PCIe channel module connected thereto to trigger the corresponding control unit to execute the data recovery mode.

[0024] Further, any one of the above technical solutions or a combination of multiple technical solutions, in the PCIe communication, if the second PCIe device sends an NACK response signal, the corresponding control unit is triggered to execute the data recovery mode, including sending a selection signal for selecting the second data input terminal to the first data selector, and sending an enable signal to the read operation enable terminal.

[0025] Further, any one of the above technical solutions or a combination of multiple technical solutions, the operation of executing the data recovery mode further includes:

[0026] The corresponding sequence number is parsed from the NACK response signal, which is the sequence number of the data packet not received by the second PCIe device;

[0027] It is checked whether the same sequence number exists in the data storage unit, if it exists, the code stream of the data packet corresponding to the sequence number is read from the data storage unit, and an ACK response signal is returned to the first PCIe device;

[0028] If not, an NACK response signal is returned to the first PCIe device.

[0029] Further, any one of the above technical solutions or a combination of multiple technical solutions, the data storage unit is configured to store the physical layer encoded data stream output by the first data enhancement unit by the following way:

[0030] The physical layer encoded data stream is parsed, including identifying the key layer markers therein to locate the start boundary and end boundary of each data packet, and parsing the sequence numbers corresponding to the respective data packets;

[0031] The physical layer encoded data stream is segmented into data packet units according to the start boundary and end boundary, and the corresponding sequence numbers are associated;

[0032] The segmented data packet units and the corresponding sequence numbers are associated and written into the memory inside the data storage unit.

[0033] Further, any of the above technical solutions or combinations of multiple technical solutions, if the same sequence number is found in the data storage unit, and there is a subsequent sequence number adjacent to the sequence number, the code stream of the multiple data packets corresponding to the multiple continuous sequence numbers with the sequence number as the starting sequence number is read from the data storage unit, and a one-to-one corresponding ACK response signal is returned to the first PCIe device;

[0034] The first PCIe device determines the next sequence number according to the last ACK response signal to continue transmitting data.

[0035] Further, any of the above technical solutions or combinations of multiple technical solutions, after searching for the same sequence number in the data storage unit and returning the response signal to the first PCIe device, further comprising:

[0036] The data storage unit feeds back a status signal to the control unit to drive the control unit to exit the data recovery mode and perform the normal working mode or the data protection mode.

[0037] Further, any of the above technical solutions or combinations of multiple technical solutions, each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface, wherein the second PCIe input interface is configured to be connected with the output interface of the second PCIe device, and the second PCIe output interface is configured to be connected with the input interface of the first PCIe device;

[0038] The second PCIe input interface is configured to send the response signal sent by the second PCIe device to the data storage unit;

[0039] The data storage unit is configured with multiple independent transmission ports, one of which is connected with the first data selector, and the other is configured to be connected with the second PCIe output interface.

[0040] Further, any one of the technical solutions or the combination of the plurality of technical solutions, each of the PCIe channel modules is further configured with a second data enhancement unit and a second data selector, wherein the second data selector is configured with a third data input end and a fourth data input end;

[0041] The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface, and the second data enhancement unit is configured with two output branches, wherein the first output branch is connected with the data storage unit, and the second output branch is connected with the third data input end of the second data selector;

[0042] The fourth data input end is connected with the another transmission port of the data storage unit, and the output end of the second data selector is connected with the second PCIe output interface.

[0043] Further, any one of the technical solutions or the combination of the plurality of technical solutions, the control unit is further configured to send a selection signal to the selection end of the second data selector, and the selection signal is used to select one of the third data input end and the fourth data input end to output the received data.

[0044] Further, any one of the technical solutions or the combination of the plurality of technical solutions, the data processing device for PCIe link provided by the application further comprises a main controller, an input end of the main controller is connected with a communication interface of a management system outside the data processing device, and an output end of the main controller is connected with an input end of the control unit of each PCIe channel module.

[0045] Further, any one of the technical solutions or the combination of the plurality of technical solutions, the data processing device for PCIe link provided by the application further comprises a power module, and the power module is configured to provide power supply for the main controller and each PCIe channel module.

[0046] Further, any one of the technical solutions or the combination of the plurality of technical solutions, the first data enhancement unit is configured with a re-timer circuit, and the first data enhancement unit is configured to perform clock data recovery, equalization and re-driving operations on the PCIe data.

[0047] According to another aspect of the application, a communication system is provided, comprising at least two PCIe devices and the data processing device for PCIe link as described above.

[0048] The technical solutions provided by the application have the following beneficial effects:

[0049] a. The signal quality, lightweight data backup storage and data recovery function in case of failure are integrated in a single module in the middle node of PCIe physical link, which simplifies the system design and has high integration degree;

[0050] b. The data transmission reliability and fault tolerance of PCIe link are significantly improved by backing up the transmission data in the data protection mode and supplementally sending in case of failure;

[0051] c. The physical layer encoded data stream is directly stored and recovered without complex protocol layer decoding and recoding, so that the response speed is fast and the additional delay is small;

[0052] d. Whether real-time sending or recovery sending from storage, the data is processed by the data enhancement module (processing before storage or existing data enhancement logic on the path after recovery), which ensures the quality of the sending signal;

[0053] e. Through the logical control unit, the working mode can be flexibly switched to adapt to the needs of different application scenarios such as high real-time or low resource consumption. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0055] Figure 1 The conceptual framework diagram of the data processing device suitable for PCIe link is provided for an exemplary embodiment of the present application;

[0056] Figure 2 The composition structure schematic diagram of the PCIe channel module of the data processing device is provided for an exemplary embodiment of the present application;

[0057] Figure 3 The specific composition schematic diagram of the data processing device is provided for an exemplary embodiment of the present application;

[0058] Figure 4 The composition structure schematic diagram of the PCIe channel module of the multi-input / output interface is provided for an exemplary embodiment of the present application;

[0059] Figure 5 The more simplified composition structure schematic diagram of the PCIe channel module of the multi-input / output interface is provided for an exemplary embodiment of the present application; Figure 4

[0060] ​Figure 6 An implementation flowchart of a data recovery mode provided for an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0061] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the protection scope of the present application.

[0062] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or equipment including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0063] In an embodiment of the present application, a data processing device suitable for a PCIe link is provided, comprising at least one PCIe channel module as shown in Figure 2 The PCIe channel module is the core of the data processing device, which needs to be initialized and configured with functional parameters. These configurations can be issued to each PCIe channel module through an internal bus or a special interface. Each PCIe channel module is configured with:

[0064] a first PCIe input interface configured to receive PCIe upstream data of a first PCIe device upstream;

[0065] a first data enhancement unit configured to perform data enhancement on the PCIe upstream data to obtain a physical layer encoded data stream; specifically, the first data enhancement unit is configured with a re-timer circuit, and the function of the first data enhancement unit is to recover and shape the received PCIe signal which may have problems of signal quality such as jitter, attenuation, etc., including clock data recovery (CDR), signal equalization and signal re-driving operation, to output a high-quality serial data stream conforming to the PCIe physical layer specification, to obtain a serial bit stream such as 8b / 10b encoding, 128b / 130b encoding or PAM4 encoding, for example, 8b / 10b encoding symbol stream for PCIe Gen1 / Gen2, 128b / 130b (or PAM4) encoding block stream for PCIe Gen3 and above versions, and possibly in a scrambling state.

[0066] a data storage unit configured to receive and temporarily store the physical layer encoded data stream output by the first data enhancement unit through a first path; the data storage unit can be implemented by a high-speed FIFO or DPRAM, and the capacity thereof is determined according to the expected amount of fault recovery data and the PCIe link rate. In the embodiment, the data storage unit stores the signal-conditioned physical layer encoded data output by the first data enhancement module. To improve the reliability of the stored data, the data storage unit can be integrated with ECC check logic inside.

[0067] a first data selector having a plurality of data input terminals, a first data input terminal of which is configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and a second data input terminal of which is configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; in the embodiment, the first data selector is a MUX (Multiplexer), which is a basic logic unit in digital circuits, used to select one output from multiple input signals to a common channel.

[0068] As can be seen, the first data enhancement unit in the embodiment has two output branches, one of which is connected with the data storage unit, and the other of which is connected with the first data input terminal of the first data selector.

[0069] a control unit configured to send a selection signal to the selection terminal of the first data selector, the selection signal being used to select one of the data received by the first data input terminal and the second data input terminal to be output by the first data selector;

[0070] a first PCIe output interface configured to send the data output by the first data selector to a second PCIe device downstream.

[0071] Continuing to refer toFigure 2 The data storage unit is configured with a write operation enable end and a read operation enable end, and the control unit is connected with the write operation enable end and the read operation enable end;

[0072] If the control unit sends an enable signal (En_write=1) to the write operation enable end, the first path is connected, that is, the enhanced physical layer coded data stream can be written into the data storage unit; if En_write=0, the data storage unit stops receiving and storing data, that is, the data storage unit cannot realize the write operation;

[0073] If the control unit sends an enable signal (En_read=1) to the read operation enable end, the third path is connected, that is, the data read from the data storage unit is sent to the second data input end of the first data selector; if En_read=0, the data storage unit cannot realize the read operation, and further stops sending data to the second data input end of the first data selector.

[0074] In the embodiment, the data storage unit can be realized by a dual-port RAM (DPRAM) and can be configured as a circular buffer, and the data storage unit can integrate an error checking code (ECC) function to ensure the integrity of the stored data.

[0075] The control unit executes different working modes according to preset mode instructions, and in some embodiments, the specific mode instructions are sent to the control unit by a main controller outside the PCIe channel module, for example, through external monitoring and configuration, if the real-time requirement of communication between the first PCIe device and the second PCIe device is high, the control unit is required to control the PCIe channel module to execute a data protection mode, that is, the control unit sends a selection signal (MUX_SEL=1) selecting the first data input end to the first data selector, sends an enable signal (En_write=1) to the write operation enable end, and prohibits sending an enable signal (En_read=0) to the read operation enable end, in this mode, the data flow path is divided into a main path: the first PCIe input interface→the first data enhancement unit→the first data selector→the first PCIe output interface, and a storage path: the first PCIe input interface→the first data enhancement unit→the data storage unit, that is, the copy data is sent and stored at the same time;

[0076] The data protection mode can improve the real-time performance. When a specific condition occurs, such as a communication failure, the second PCIe device fails to successfully receive a data packet, and in the process of waiting for the breakpoint continuation, the data stored in the data storage unit in the data protection mode can be used to resend the data to the second PCIe device. This mode is defined as a data recovery mode, that is, the control unit sends a selection signal (MUX_SEL=0) to the first data selector to select the second data input terminal, and sends an enable signal (En_read=1) to the read operation enable terminal. In the data recovery mode, an enable signal can be sent to the write operation enable terminal, or the sending of the enable signal to the write operation enable terminal can be prohibited (stopping writing new data can protect the stored data to be recovered). The embodiment is not limited specifically, and the case of prohibiting the sending of the enable signal to the write operation enable terminal is taken as an example. The data flow path in the data protection mode is data storage unit→first data selector→first PCIe output interface.

[0077] When the command of external monitoring is that the real-time performance requirement between the first PCIe device and the second PCIe device is not high, even if a failure occurs (the second PCIe device fails to successfully receive a data packet), the first PCIe device can be configured to resend a certain number of data packets. In this configuration, the control unit controls the PCIe channel module to execute a normal working mode, that is, the control unit sends a selection signal (MUX_SEL=1) to the first data selector to select the first data input terminal, and prohibits the sending of the enable signal to the write operation enable terminal and the read operation enable terminal (En_write=0, En_read=0). The data flow path in this mode is first PCIe input interface→first data enhancement unit→first data selector→first PCIe output interface. The normal working mode only executes a standard re-timing function.

[0078] In addition to indicating the control unit to control the PCIe channel module to execute the normal working mode or the data protection mode through external monitoring and configuration, an embodiment of the application also provides a control strategy according to a preset frequency, such as a preset period T. In each period, the first 3T / 4 executes the normal working mode, and the last 1T / 4 executes the data protection mode. The technical solution of the application can also be implemented.

[0079] In an embodiment, whether a failure occurs can be determined by an external triggering mode or an internal monitoring mode, so as to switch to the data recovery mode. The external triggering mode refers to determining whether a failure occurs through external monitoring of link data. If a failure occurs, an external trigger signal is sent, so as to trigger the control unit to set MUX_SEL=0 and En_read=1, that is, the PCIe channel module enters the data recovery mode.

[0080] The following describes in detail another way of internal monitoring to determine whether a fault occurs: the PCIe link layer assigns a continuous sequence number to each data packet of a data stream, and if the second PCIe device receives a data packet corresponding to a continuous sequence number, it returns an ACK response signal to the first PCIe device one-to-one, indicating that the second PCIe device has successfully received the data. Because the sequence numbers of the data packets in the data stream are continuous, if the second PCIe device does not receive a data packet corresponding to the next continuous sequence number within a preset time, it sends a NACK response signal, at which point it is considered that a fault has occurred, and the missing current data packet needs to be retransmitted before the data packet transmission can be resumed.

[0081] As Figure 5 In an embodiment, each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface, wherein the second PCIe input interface is configured to be connected with the output interface of the second PCIe device, and the second PCIe output interface is configured to be connected with the input interface of the first PCIe device.

[0082] The response signals returned by the second PCIe device are all sent through the second PCIe input interface. For an ACK response signal, there are two ways to return it to the first PCIe device: way one is to send the ACK response signal directly to the second PCIe output interface for further sending to the first PCIe device; and way two is to send the ACK response signal to the data storage unit, which is sent to the second PCIe output interface for further sending to the first PCIe device.

[0083] The key of the data recovery mode is to trigger the execution of the data recovery mode based on the NACK response signal: the second PCIe device does not receive a data packet corresponding to the next continuous sequence number and sends a NACK response signal to the data storage unit through the second PCIe input interface.

[0084] The data storage unit attempts to retransmit data to the second PCIe device, and if the retransmission is successful, this NACK response is handled at the PCIe channel module level and does not need to be passed up to the first PCIe device. At this point, the data storage unit will generate a corresponding ACK response signal according to the NACK response signal and send it to the second PCIe output interface for further sending to the first PCIe device. In order to avoid confusion in the data sent by the data storage unit, the data storage unit in this embodiment is configured with multiple independent transmission ports TX1 and TX2, one of which is connected with the first data selector, and the other is configured to be connected with the second PCIe output interface.

[0085] If the NACK response cannot be processed at the PCIe channel module level, it needs to be passed up to the first PCIe device. At this time, the data storage unit will forward the NACK response signal to the second PCIe output interface for further transmission to the first PCIe device, so that the first PCIe device can back up to the breakpoint of the data packet and perform data retransmission.

[0086] The operation of attempting to process the NACK response at the PCIe channel module level is divided into a storage phase and a data recovery phase as shown in Figure 6

[0087] In the storage phase, the physical layer encoded data stream output by the first data enhancement unit is stored by the following method:

[0088] The data storage unit receives the enhanced encoded data stream;

[0089] The physical layer encoded data stream is parsed, including identifying the key layer mark therein to locate the start boundary and end boundary of each data packet, and parsing the sequence number corresponding to each data packet;

[0090] According to the start boundary and the end boundary, the physical layer encoded data stream is divided into a plurality of data packet units, and the corresponding sequence numbers are associated; in this way, subsequent indexing, querying and sending can be facilitated according to the granularity of the "packet";

[0091] The segmented data packet units and their corresponding sequence numbers are associated and written into the memory inside the data storage unit.

[0092] The data recovery phase includes:

[0093] The data storage unit receives the NACK response signal from the second PCIe device;

[0094] The corresponding sequence number is parsed from the NACK response signal, which is the sequence number of the data packet not received by the second PCIe device;

[0095] It is checked whether the same sequence number exists in the data storage unit; if it exists, the code stream of the data packet corresponding to the sequence number is read from the data storage unit and sent to the second PCIe device to complete data retransmission, and an ACK response signal corresponding to the NACK response is generated and returned to the first PCIe device through the second PCIe output interface;

[0096] If the same sequence number does not exist in the data storage unit, the NACK response signal is forwarded to the first PCIe device through the second PCIe output interface.

[0097] ​In the data protection mode, while the normal data is transmitted, a copy of the data with high quality after data enhancement processing is stored in the data storage unit. The data storage unit is usually designed as a circular buffer, when it is full, the newest data will overwrite the oldest data; or the data aging and cleaning mode can be started, that is, when the data storage unit writes a data, a counter is started, when the data life cycle exceeds the preset time threshold, the cleaning is triggered, assuming that the data storage window period is 500 ms and the data life cycle is 1 s, when the data received in these 500 ms is 1 s after the data life cycle, the data stored in these 500 ms is cleaned, so that the storage space can be effectively managed and not filled with outdated data indefinitely.

[0098] The data storage unit is usually implemented as a circular buffer (Circular Buffer / FIFO), which means that when the buffer is full, the newly written data will automatically overwrite the oldest data. In this case, "starting the timer" can be understood as the write / overwrite mechanism of the circular buffer starting to take effect, keeping the data in the storage relatively "fresh", giving priority to retaining the most recent data that is most likely to be needed for fault recovery, and releasing space for new incoming data.

[0099] In the case of finding the same sequence number in the data storage unit, there are two embodiments of data retransmission, the first embodiment is to send only the data packet corresponding to the one to be continued sequence number to the second PCIe device, and then notify the first PCIe device to continue transmitting data from the next sequence number; the second embodiment is that the same sequence number is found in the data storage unit, and there is a subsequent sequence number adjacent to the sequence number, the code stream of the multiple data packets corresponding to the multiple continuous sequence numbers with the starting sequence number is read out from the data storage unit, and the one-to-one corresponding ACK response signal is returned to the first PCIe device; the first PCIe device determines the next sequence number according to the last ACK response signal to continue transmitting data, for example, the multiple data packets from sequence number 100 to 105 are read out from the data storage unit, accordingly, the data storage unit generates the response signals ACK 100 , ACK 101 , ACK 102 , ACK 103 , ACK 104 , ACK 105 and sends them to the first PCIe device, and the first PCIe device continues to transmit data from the sequence number 106.

[0100] As shown in Figure 2 , the data storage unit also feeds back a status signal to the control unit: whether the same sequence number exists in the data storage unit and returns the response signal to the first PCIe device, further comprising:

[0101] The data storage unit feeds back a state signal to the control unit to drive the control unit to exit the data recovery mode and execute the normal working mode or the data protection mode. Whether the NACK response is processed at the PCIe channel module level or not, the control unit needs to be informed that the current data recovery mode has ended and needs to be switched to the normal working mode or the data protection mode.

[0102] In the embodiment shown in Figure 4 In the embodiment shown in

[0103] Each PCIe channel module is further configured with a second data enhancement unit and a second data selector, wherein the second data selector is configured with a third data input end and a fourth data input end;

[0104] The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface, and the second data enhancement unit is configured with two output branches, wherein the first output branch is connected with the data storage unit, and the second output branch is connected with the third data input end of the second data selector;

[0105] The fourth data input end is connected with the other transmission port of the data storage unit, and the output end of the second data selector is connected with the second PCIe output interface.

[0106] The control unit is further configured to send a selection signal to the selection end of the second data selector, and the selection signal selects one of the third data input end and the fourth data input end to output the data received thereby.

[0107] As shown in Figure 4 The data storage unit has two independent transmission ports TX1 and TX2, one of which is connected with the receiving port RX1 at the first data selector, and the other is connected with the receiving port RX2 at the second data selector. The data storage unit has a data analysis function module, which can determine whether to send data to the second PCIe device via the TX1 port or to the first PCIe device via the TX2 port according to the device to which the current data is sent.

[0108] The PCIe channel module is the core of the data processing device suitable for the PCIe link provided by the embodiment of the application. In addition, the data processing device further includes a main controller and a power module, as shown in Figure 1 and Figure 3As shown, the power module is configured to provide power supply to the main controller and each PCIe channel module; the input end of the main controller is connected with the communication interface (such as I2C, SPI, Ethernet, etc.) of the management system (such as BMC, server motherboard, network management system) outside the data processing device, and reports the health status of the entire platform and the state of each channel, and receives the control instructions (such as enabling a certain channel to enter a specific mode, updating firmware, etc.) from the external system; the output end of the main controller is connected with the input end of the control unit of each PCIe channel module, such as Figure 3 As shown.

[0109] In an embodiment of the present application, a communication system is provided, comprising at least two PCIe devices and the data processing device for PCIe link as described above.

[0110] Through the above structure and method, an effective signal conditioning and data protection combined solution is provided at the key node of the PCIe link, which significantly improves the stability and reliability of high-speed data transmission.

[0111] It should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0112] The above description is only a specific embodiment of the present application, and it should be noted that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A data processing device suitable for a PCIe link, characterized in that, The data processing device is a module integrated in a PCIe physical link between nodes to enhance signal quality, store data and recover data in case of failure, and the data processing device comprises at least one PCIe channel module, and each PCIe channel module is configured with: a first PCIe input interface configured to receive PCIe upstream data of an upstream first PCIe device; a first data enhancement unit configured to perform data enhancement on the PCIe upstream data to obtain physical layer encoded data stream; a data storage unit configured to receive and store the physical layer encoded data stream output by the first data enhancement unit through a first path; a first data selector with multiple data input ends, a first data input end of which is configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and a second data input end of which is configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; a control unit configured to send a selection signal to a selection end of the first data selector, and the selection signal is used to select one of the first data input end and the second data input end to output data; a first PCIe output interface configured to send data output by the first data selector to a downstream second PCIe device; the control unit executes different working modes according to preset mode instructions, including: if the mode instruction is to execute a normal working mode, the control unit sends a selection signal selecting the first data input end to the first data selector, and controls the data storage unit to stop receiving and storing data and stop sending data to the second data input end of the first data selector; if a communication failure occurs in the normal working mode, the first PCIe device retransmits a preset number of data packets; if the mode instruction is to execute a data protection mode, the control unit sends a selection signal selecting the first data input end to the first data selector, and controls the first path to remain in an on state and controls the data storage unit to stop sending data to the second data input end of the first data selector; if the mode instruction is to execute a data recovery mode, the control unit sends a selection signal selecting the second data input end to the first data selector, and controls the third path to remain in an on state.

2. The data processing device suitable for a PCIe link according to claim 1, wherein, The data storage unit is configured with a write operation enable end and a read operation enable end, and the control unit is further connected with the write operation enable end and the read operation enable end; if the control unit sends an enable signal to the write operation enable end, the first path is turned on, otherwise the data storage unit stops receiving and storing data; if the control unit sends an enable signal to the read operation enable end, the third path is turned on, otherwise the data storage unit stops sending data to the second data input end of the first data selector.

3. The data processing device suitable for a PCIe link according to claim 1, wherein, The mode instruction to execute the data protection mode is configured to send to the control unit at a preset frequency. The data processing device is a module integrated in a PCIe physical link between nodes to enhance signal quality, store data and recover data in case of failure, and the data processing device comprises at least one PCIe channel module, and each PCIe channel module is configured with: a first PCIe input interface configured to receive PCIe upstream data of an upstream first PCIe device; a first data enhancement unit configured to perform data enhancement on the PCIe upstream data to obtain physical layer encoded data stream; a data storage unit configured to receive and store the physical layer encoded data stream output by the first data enhancement unit through a first path; a first data selector with multiple data input ends, a first data input end of which is configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and a second data input end of which is configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; a control unit configured to send a selection signal to a selection end of the first data selector, and the selection signal is used to select one of the first data input end and the second data input end to output data; a first PCIe output interface configured to send data output by the first data selector to a downstream second PCIe device; the control unit executes different working modes according to preset mode instructions, including: if the mode instruction is to execute a normal working mode, the control unit sends a selection signal selecting the first data input end to the first data selector, and controls the data storage unit to stop receiving and storing data and stop sending data to the second data input end of the first data selector; if a communication failure occurs in the normal working mode, the first PCIe device retransmits a preset number of data packets; if the mode instruction is to execute a data protection mode, the control unit sends a selection signal selecting the first data input end to the first data selector, and controls the first path to remain in an on state and controls the data storage unit to stop sending data to the second data input end of the first data selector; if the mode instruction is to execute a data recovery mode, the control unit sends a selection signal selecting the second data input end to the first data selector, and controls the third path to remain in an on state. The data storage unit is configured with a write operation enable end and a read operation enable end, and the control unit is further connected with the write operation enable end and the read operation enable end; if the control unit sends an enable signal to the write operation enable end, the first path is turned on, otherwise the data storage unit stops receiving and storing data; if the control unit sends an enable signal to the read operation enable end, the third path is turned on, otherwise the data storage unit stops sending data to the second data input end of the first data selector. The mode instruction to execute the data protection mode is configured to send to the control unit at a preset frequency. Alternatively, the mode instruction for executing the normal working mode or the data protection mode is configured to be sent to the control unit by a master controller outside the PCIe channel module.

4. The data processing device suitable for a PCIe link according to claim 1, wherein, The PCIe link layer assigns a continuous sequence number to each data packet of a data stream, and if the second PCIe device receives a data packet corresponding to a continuous sequence number, it returns an ACK response signal to the first PCIe device one-to-one. If the second PCIe device does not receive a data packet corresponding to a continuous next sequence number, it sends an NACK response signal to the PCIe channel module connected thereto to trigger the corresponding control unit to execute the data recovery mode.

5. The data processing device suitable for a PCIe link according to claim 2, wherein, In the PCIe communication, if the second PCIe device sends an NACK response signal, it triggers the corresponding control unit to execute the data recovery mode, including sending a selection signal to the first data selector to select the second data input terminal, and sending an enable signal to the read operation enable terminal.

6. The data processing device suitable for a PCIe link according to claim 4 or 5, characterized in that, The operation of executing the data recovery mode further includes: Resolving the corresponding sequence number from the NACK response signal, which is the sequence number of the data packet not received by the second PCIe device; Looking up whether the same sequence number exists in the data storage unit; if it exists, reading the code stream of the data packet corresponding to the sequence number from the data storage unit, and returning an ACK response signal to the first PCIe device; If not, return an NACK response signal to the first PCIe device.

7. The data processing device suitable for a PCIe link according to claim 6, wherein, The data storage unit is configured to store the physical layer encoded data stream output by the first data enhancement unit by the following means: Resolving the physical layer encoded data stream, including identifying the key layer mark therein to locate the start boundary and end boundary of each data packet, and resolving the sequence number corresponding to each data packet; According to the start boundary and end boundary, the physical layer encoded data stream is divided into a plurality of data packet units, and the corresponding sequence number is associated; The segmented data packet unit and its corresponding sequence number are associatedly written into the memory inside the data storage unit.

8. The data processing device suitable for a PCIe link according to claim 6, wherein, If the same sequence number is found in the data storage unit, and there is a subsequent sequence number adjacent to the sequence number, the code stream of the plurality of data packets corresponding to the plurality of continuous sequence numbers with the sequence number as the start sequence number is read from the data storage unit, and one-to-one ACK response signals are returned to the first PCIe device. The first PCIe device determines the next sequence number according to the last ACK response signal to continue transmitting data.

9. The data processing device suitable for a PCIe link according to claim 6, wherein, After looking up whether the same sequence number exists in the data storage unit and returning the response signal to the first PCIe device, it further includes: The data storage unit feeds back a status signal to the control unit to drive the control unit to exit the data recovery mode and execute the normal working mode or the data protection mode.

10. The data processing device suitable for a PCIe link according to claim 6, wherein, Each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface, wherein the second PCIe input interface is configured to connect with an output interface of the second PCIe device, and the second PCIe output interface is configured to connect with an input interface of the first PCIe device; The second PCIe input interface is configured to send a response signal sent by the second PCIe device to the data storage unit; The data storage unit is configured with multiple independent transmission ports, one of which is connected with the first data selector, and another of which is configured to connect with the second PCIe output interface.

11. The data processing device suitable for a PCIe link according to claim 10, wherein, Each PCIe channel module is further configured with a second data enhancement unit and a second data selector, wherein the second data selector is configured with a third data input and a fourth data input; The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface, and the second data enhancement unit is configured with two output branches, wherein a first output branch is connected with the data storage unit, and a second output branch is connected with the third data input of the second data selector; The fourth data input is connected with the another transmission port of the data storage unit, and an output end of the second data selector is connected with the second PCIe output interface.

12. The data processing device suitable for a PCIe link according to claim 11, wherein, The control unit is further configured to send a selection signal to a selection end of the second data selector, which selects one of the third data input and the fourth data input to output the received data.

13. The data processing device suitable for a PCIe link according to claim 1, wherein, Further comprising a main controller, an input end of which is connected with a communication interface of a management system outside the data processing device, and an output end of which is connected with an input end of the control unit of each PCIe channel module.

14. The data processing device suitable for a PCIe link according to claim 13, wherein, Further comprising a power module configured to provide power supply for the main controller and each PCIe channel module.

15. The data processing apparatus suitable for a PCIe link according to any one of claims 1 to 5 or any one of claims 7 to 14, characterized in that, The first data enhancement unit is configured with a re-timer circuit, and the first data enhancement unit is configured to perform clock data recovery, equalization and re-driving operations on the PCIe data.

16. A communication system, characterized by The data processing device for PCIe link according to any one of claims 1 to 15. The data processing device for PCIe link according to any one of claims 1 to 15.

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