A downsampling method, device, equipment and medium based on LVDS channel

Abstract

The present application provides a downsampling method, apparatus, device, and medium based on an LVDS channel. The method comprises: determining the number of bits of data to be transmitted and the corresponding preamble, and transmitting the data to be transmitted through a SerDes channel to obtain initial data, wherein the data to be transmitted is data acquired through the LVDS channel; determining the number of target data groups and the groups in each target data group based on the number of bits, and determining the target data corresponding to the initial data based on the clock of the SerDes channel and a preset combination rule; extracting the median data in each group for each target data group to obtain downsampled data corresponding to the target data group, and determining the target group in each group that matches the preamble based on a preset check number; determining a target identifier based on the number of target groups and a preset threshold, and determining the target downsampled data based on the target identifier and the downsampled data; thereby improving the accuracy of sampling data at different rates and the quality of the sampling results.

Description

Technical Field

[0001] The present application relates to the field of communication sampling technology, and in particular to a downsampling method, apparatus, device and medium based on an LVDS channel. Background Art

[0002] Many communications devices or the interconnections between chips on their internal circuit boards are connected via low-voltage differential signaling (LVDS) lines, and communication speeds are showing a significant upward trend. While this technological evolution brings efficient data transmission, it also poses higher challenges to signal integrity and reliability.

[0003] Existing downsampling methods generally use a clock recovery circuit to generate a sampling clock, then adjust the phase relationship between the clock edge and the data edge so that the sampling clock edge is aligned with the middle of the sampled data, and then obtain parallel data through a serial-to-parallel conversion circuit.

[0004] However, existing downsampling methods have the problems of low sampling efficiency and low accuracy of sampling results. Summary of the Invention

[0005] The present application provides a downsampling method, apparatus, device and medium based on an LVDS channel, which is used to solve the problems of low sampling efficiency and low accuracy of sampling results in existing downsampling methods.

[0006] In a first aspect, the present application provides a downsampling method based on an LVDS channel, the method comprising:

[0007] Determine the number of bits of data to be transmitted and the corresponding preamble, and transmit the data to be transmitted through the serdes channel to obtain initial data. The data to be transmitted is the data obtained through the lvds channel.

[0008] Determine the number of target data groups and the grouping in each target data group based on the number of bits, and determine the target data corresponding to the initial data based on the clock of the serdes channel and the preset combination rules;

[0009] For each target data group, extract the median data in each group to obtain the downsampled data corresponding to the target data group, and determine the target group in each group that matches the preamble according to the preset number of checks;

[0010] The target identifier is determined according to the number of target groups and a preset threshold, and the target down-sampled data is determined according to the target identifier and the down-sampled data.

[0011] In some embodiments of the present application, determining the number of bits of data to be transmitted and the corresponding preamble, and transmitting the data to be transmitted according to the serdes channel to obtain initial data includes:

[0012] Obtain the data to be transmitted and determine the number of bits corresponding to the data to be transmitted;

[0013] Determine the preamble code and add the preamble code before the data to be transmitted;

[0014] According to the serdes channel, the data to be transmitted with the preamble added is transmitted to obtain the initial data.

[0015] In some embodiments of the present application, the number of target data groups and the corresponding grouping in each target data group are determined based on the number of bits, and the target data corresponding to the initial data is determined based on the clock on the user side of the SerDes channel, the preset combination rule and the initial data, including:

[0016] Determine the number of target data groups and the grouping within the target data groups based on the number of digits;

[0017] According to the clock, the initial data is delayed by one clock cycle to obtain delayed data;

[0018] According to the preset combination rules, the initial data and the delayed data are combined to obtain the target data.

[0019] In some embodiments of the present application, the initial data and the delayed data are combined according to a preset combination rule to obtain the target data, including:

[0020] Determine the target number of groups corresponding to each target data group, and determine the initial high-order data in the initial data that is the same as the data of the target number of groups based on the sequence corresponding to the initial data;

[0021] According to the sequence corresponding to the delayed data, the delayed high-order data having the same number as the target number of groups in the delayed data are determined, and the delayed high-order data are deleted to obtain the delayed low-order data;

[0022] According to the preset combination rules, the initial high-order data and the delayed low-order data are combined to obtain the target data.

[0023] In some embodiments of the present application, for each target data group, the median data in each group is extracted to obtain downsampled data corresponding to the target data group, and the target group matching the preamble in each group is determined based on a preset number of checks, including:

[0024] Extract the median data of the group to obtain downsampled data;

[0025] Determine the target counter corresponding to each group, and determine the group check data of the intermediate sequence based on the data sequence of the group and the preset check number;

[0026] Determine whether the packet check data and the preamble match each other;

[0027] If the packet check data and the preamble match, the corresponding packet is determined to be the target packet, and the count of the target counter corresponding to the packet is increased by 1;

[0028] If the packet check data and the preamble do not match each other, it is determined that the packet corresponding to the packet check data is a non-target packet.

[0029] In some embodiments of the present application, determining a target identifier based on the number of target groups and a preset threshold, and determining target downsampled data based on the target identifier and the downsampled data includes:

[0030] Determine the target counters corresponding to each group and their counts to obtain the number of target groups;

[0031] Compare the number of target groups with the preset threshold to obtain a comparison result;

[0032] If the comparison result shows that the number of target groups is greater than the preset threshold, the counting identifier of the corresponding target counter is determined to obtain the target identifier;

[0033] If the comparison result shows that the target quantity is not greater than the preset threshold, the counting flag of the target counter is determined;

[0034] Target downsampling data is determined according to the target identifier and the downsampling data.

[0035] In some embodiments of the present application, determining target downsampled data according to the target identifier and the downsampled data includes:

[0036] Determine the downsampled data corresponding to each target data group, and determine, based on the target identifier, the target data group corresponding to the target identifier in the target data group as the downsampled data group;

[0037] Determine the down-sampled data corresponding to the down-sampled data group as the target down-sampled data, and output the target down-sampled data.

[0038] In a second aspect, the present application provides a downsampling device based on an LVDS channel, the device comprising:

[0039] The transmission module is used to determine the number of bits of the data to be transmitted and the corresponding preamble, and transmit the data to be transmitted according to the Serdes channel to obtain initial data. The data to be transmitted is the data obtained through the LVDS channel;

[0040] The data determination module is used to determine the number of target data groups and the grouping in each target data group according to the number of bits, and determine the target data corresponding to the initial data according to the clock of the SerDes channel and the preset combination rules;

[0041] A group determination module is used to extract the median data in each group for each target data group to obtain the downsampled data corresponding to the target data group, and determine the target group in each group that matches the preamble according to a preset number of checks;

[0042] The identification determination module is used to determine the target identification according to the number of target groups and a preset threshold, and to determine the target down-sampling data according to the target identification and the down-sampling data.

[0043] In a third aspect, the present application provides a computer device, comprising: a processor, and a memory communicatively connected to the processor;

[0044] Memory stores computer-executable instructions;

[0045] The processor executes the computer-executable instructions stored in the memory to implement the method of the present application.

[0046] In a fourth aspect, the present application provides a computer-readable storage medium, in which program code is stored. When the program code is executed by a processor, it is used to implement the method of the present application.

[0047] The present application provides a downsampling method, apparatus, device and medium based on an LVDS channel. The method determines the number of bits of data to be transmitted and the corresponding preamble code, and transmits the data to be transmitted through a SerDes channel to obtain initial data, where the data to be transmitted is data obtained through the LVDS channel. Based on the number of bits, the method determines the number of target data groups and the groups in each target data group, and determines the target data corresponding to the initial data based on the clock of the SerDes channel and a preset combination rule. For each target data group, the method extracts the median data in each group to obtain downsampled data corresponding to the target data group, and determines the target group in each group that matches the preamble code based on a preset check number. Based on the number of target groups and a preset threshold, the method determines a target identifier, and determines the target downsampled data based on the target identifier and the downsampled data.

[0048] In this way, the regularity of the preamble code can be utilized to locate the stable sampling interval, because the alternating pattern of the preamble code can be detected by the receiving end. Therefore, if the data in the data group matches the pattern, it means that the sampling phase corresponding to the data is in the data stable area (non-jump edge), and the probability of metastable state is significantly reduced; at the same time, the accidental matching of a single group of data with the preamble code pattern will be excluded because the counter has not reached the threshold, and only the continuous and stable preamble code characteristics will be recognized, filtering out accidental interference and improving the accuracy and sampling quality of data at different rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0050] Figure 1 A flowchart of a downsampling method based on an LVDS channel provided in an embodiment of the present application;

[0051] Figure 2 A sampling diagram of a downsampling method based on an LVDS channel provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of the structure of a downsampling device based on an LVDS channel provided in an embodiment of the present application;

[0053] Figure 4 This is a structural block diagram of a device for executing a downsampling method based on an LVDS channel according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0055] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0056] Figure 1 The flowchart of a downsampling method based on LVDS channel provided in the embodiment of the present application is as follows. Figure 1 As shown, the downsampling method based on the LVDS channel may include the following steps:

[0057] S110 , determining the number of bits of data to be transmitted and the corresponding preamble, and transmitting the data to be transmitted through the serdes channel to obtain initial data, where the data to be transmitted is data obtained through the lvds channel.

[0058] Among them, LVDS (low voltage differential signaling) is a differential signal transmission method. As the underlying physical link, it uses low voltage differential signaling technology (LVDS) to achieve high-speed data transmission. It can provide a high-bandwidth, low-noise transmission medium for data, ensuring reliable data transmission at the physical layer.

[0059] The data to be transmitted is the data that needs to be transmitted through the data transmission channel. The number of bits "data bits" refers to the number of binary bits contained in the data, which is used to measure the length or size of the data.

[0060] The preamble is a fixed, regular binary bit sequence added to the header of the original data frame. It is used to identify the starting position of the data frame and synchronize the clock phase, so that metastable interference can be avoided later through regular characteristics. For example, a 1.25g bit stream plus the 122-bit preamble 0101 becomes 1.25g serial data. After being used by a 10g clock, the probability of metastable state is similar to that of other data. Subsequently, by identifying the regular feature 0101 included in the data, stable data without metastable state can be determined, thereby identifying stable downsampled data.

[0061] Serdes is a serializer that can realize the mutual conversion between parallel data and serial data. The serdes channel is based on serdes technology and is responsible for the transmission and processing of high-speed serial data. Its core function is to convert parallel data into serial data (transmitter serializer), transmit it through a high-speed channel, and then deserialize it into parallel data at the receiving end.

[0062] Based on this, metastable state refers to the situation in high-speed communication where, when the sampling clock edge of the receiving end is close to the data transition edge, the trigger may enter an uncertain state (neither a stable "0" nor a "1"), resulting in incorrect or abnormal sampling values. Therefore, when transmitting data at different rates, the data to be transmitted and its corresponding number of data bits and preamble can be determined, and the data to be transmitted can be transmitted according to the transmission channel to obtain the initial data, so that the regularity of the preamble can be used to locate the stable sampling interval, thereby determining stable data that is not in a metastable state to meet the sampling requirements.

[0063] S120 , determining the number of target data groups and the grouping in each target data group according to the number of bits, and determining the target data corresponding to the initial data according to the clock of the serdes channel and a preset combination rule.

[0064] The target data is data obtained by delaying the initial data according to the clock and combining the data according to a preset combination rule.

[0065] The grouping is a data grouping obtained by grouping the data in the target data group according to the number of bits of the data to be transmitted. For example, if the number of bits of the data to be transmitted is 8 bits and the data of the target data group is 64 bits, then the adjacent 8 bits of data in the target data group can be regarded as a corresponding data group according to the data sequence.

[0066] The clock can be the serdes user-side rxclk clock, that is, the clock used by the serdes user-side logic (such as the FPGA internal logic clock), which is used to control operations such as data delay and shift combination. It can delay the parallel data bus by one beat and provide a timing reference for generating multi-phase offset data.

[0067] The preset combination rule is a pre-set rule for combining data according to the number of bits, and may be combining the low-bit data of the initial data and the high-bit data of the data after clock delay.

[0068] For example, 1.25G LVDS data is transmitted from a 10G LVDS channel, which means that the transmitted data needs to be downsampled 8 times. If the data coming out of the Serdes receiving channel is datai[63:0], it is delayed by one beat by the Serdes user-side RXCLK clock to obtain data datai1[63:0]. According to the preset combination rules, it can be shifted and recombined to obtain 8 groups of 64-bit wide data buses data1 to data8 with different bit sequences, which are the target data, respectively:

[0069] data1=datai;

[0070] data2={datai1[62:0],datai

[63] };

[0071] data3={datai1[61:0],datai[63:62]};

[0072] data4={datai1[60:0],datai[63:61]};

[0073] data5={datai1[59:0],datai[63:60]};

[0074] data6={datai1[58:0],datai[63:59]};

[0075] data7={datai1[57:0],datai[63:58]};

[0076] data8={datai1[56:0],datai[63:57]}

[0077] Based on this, the initial data is delayed by the clock, and further according to the preset combination rules, the low-order data of the initial data and the high-order data in the delayed data are correspondingly combined to obtain the target data, so that the data grouping that meets the preamble rule in the target data can be determined subsequently, thereby determining the data that is not in a metastable state and obtaining the downsampled data that meets the sampling requirements.

[0078] S130 , for each target data group, extract the median data in each group to obtain downsampled data corresponding to the target data group, and determine the target group matching the preamble in each group based on a preset number of checks.

[0079] The median data is the data in the middle of the data group. For example, if the data group is [63, 65], the median data is

[59] .

[0080] The preset check number is a pre-set number used to verify whether there is continuous data in the data group that matches the preamble code. The alternating pattern of the preamble code can be detected by the receiving end. The data group that matches this pattern indicates that the sampling phase is in the data stable area (non-jump edge), and the probability of metastable state is significantly reduced.

[0081] For example, the data coming out of the Serdes receiving channel is datai[63:0]. The data is delayed by one beat using the Serdes user-side rxclk clock to obtain data datai1[63:0]. The target data group is:

[0082] data1=datai;

[0083] data2={datai1[62:0],datai

[63] };

[0084] data3={datai1[61:0],datai[63:62]};

[0085] data4={datai1[60:0],datai[63:61]};

[0086] data5={datai1[59:0],datai[63:60]};

[0087] data6={datai1[58:0],datai[63:59]};

[0088] data7={datai1[57:0],datai[63:58]};

[0089] data8={datai1[56:0],datai[63:57]};

[0090] Then, from the above 8 groups of 64-bit wide buses, the middle bit of data is extracted for every 8 bits of data to obtain 8 channels of 8-bit wide data datx, where the range of x is 1~8. For example, dat1 can include {data1

[59] , data2

[51] , data3

[43] , data4

[35] , data5

[27] , data6

[19] , data7

[11] , data8【3】}, that is, according to the number of bits of data to be transmitted, the target data group datai[63:0] is divided into 8 data groups, and the median data of each data group is extracted to obtain the corresponding downsampled data dat1.

[0091] Based on this, the target data group is divided according to the number of bits of the data to be transmitted to obtain data groups, and the intermediate data is extracted according to the data sequence corresponding to the data group to obtain the down-sampled data corresponding to the target data group, so that the data and preamble in each group can be matched according to the check number, thereby determining the target down-sampled data that meets the sampling requirements among multiple groups of down-sampled data.

[0092] S140: Determine a target identifier according to the number of target groups and a preset threshold, and determine target down-sampled data according to the target identifier and the down-sampled data.

[0093] Among them, the preset threshold is a pre-set threshold used to determine whether the number of target groups meets the requirements; a single group of data that accidentally matches the preamble code pattern will be excluded because the counter does not reach the threshold, and only the continuous and stable preamble code features will be recognized to filter out accidental interference.

[0094] The identifier is the identifier of the counter, which is used to record the number of target groups, so that the number of target groups can be determined based on the number recorded in the counter and compared with the preset threshold; the target identifier is the identifier corresponding to the counter whose recorded number is greater than the preset threshold, which is used to characterize the target group including the continuous and stable preamble code characteristics.

[0095] The target downsampled data is the stable data that meets the sampling requirements.

[0096] It is understandable that when a high-frequency clock is used to sample a low-frequency signal, the original one-bit data will become several bits. Since it is not a synchronous clock, metastable states will occur when the data jumps. The original 0 becomes 1, and the original 1 becomes 0. Therefore, the data sampled by the high-frequency clock is random, disordered, and messy. Its regularity only appears in the middle section of the data. For a 1.25g signal, a 10g clock is used to sample, and one bit of data becomes 8 bits. Since it is not a synchronous clock, the 8-bit data is not 8 1s or 8 0s. The data at the double edge of this data is random and unpredictable. At the same time On the user side, a low frequency is required, which 10G logic cannot achieve. Therefore, the frequency must be reduced. This means converting the 1-bit 10G serial data into multi-bit parallel data by reducing the operating clock frequency. For example, a 64-bit data bus actually only contains 8 meaningful data points, each represented by 8 bits. The data that emerges from the SerDes (Serbite-Decoder) undergoes serial-to-parallel conversion. The starting point of the conversion in a long string of data is random. This results in the 64-bit data sometimes containing only 7 complete and meaningful signals, with one signal being incomplete. This occurs when two adjacent 8-bit valid signals have a partial bit of one data point appearing in the previous 64 bits. Therefore, a shift is required to recover the complete 8 valid data points. Because the data is random, it is unknown how many bits are misaligned when a partial bit of data point appears in the previous 64 bits. Therefore, the number of target packets is compared with a preset threshold to determine the target identifier corresponding to the target packet with a value greater than the preset threshold. This allows the target downsampled data corresponding to the target identifier to be determined from multiple sets of downsampled data.

[0097] Based on the feasible implementation of the above S110, the present application further provides a method for determining the number of bits of data to be transmitted and the corresponding preamble, and transmitting the data to be transmitted according to the serdes channel to obtain initial data, including the steps of:

[0098] Obtain the data to be transmitted and determine the number of bits corresponding to the data to be transmitted;

[0099] Determine the preamble code and add the preamble code before the data to be transmitted;

[0100] According to the serdes channel, the data to be transmitted with the preamble added is transmitted to obtain the initial data.

[0101] The data to be transmitted is the data content itself that needs to be transmitted without adding a preamble code, for example, it can be an 8-bit data. By adding a preamble code as a frame header before transmitting the data through the high-speed LVDS bus, these preamble codes are converted into serial data. After sampling, the probability of their metastable state appearing is the same as that of the payload data, so that the receiving end can detect it with the help of the alternating rule of the preamble code. The data group that matches this rule indicates that the sampling phase is in the data stable area (non-jump edge).

[0102] Based on this, a regular preamble code is added before the initial data to be transmitted, so that the initial data after subsequent transmission through the channel includes the regular data corresponding to the preamble code. By identifying the regular data, stable sampling data that is not in a metastable state is determined, and the target down-sampling data that meets the sampling requirements is output.

[0103] Based on the feasible implementation of the above S120, the present application further provides a method for determining the number of target data groups and the corresponding grouping in each target data group according to the number of bits, and determining the target data corresponding to the initial data according to the clock on the user side of the SerDes channel, the preset combination rule and the initial data, including the steps of:

[0104] Determine the number of target data groups and the grouping within the target data groups based on the number of digits;

[0105] According to the clock, the initial data is delayed by one clock cycle to obtain delayed data;

[0106] According to the preset combination rules, the initial data and the delayed data are combined to obtain the target data.

[0107] Based on this, by determining the number of bits of the data to be transmitted, for example, if the data to be transmitted is 8-bit data, it can be determined that according to the preset combination rules, the initial data and the delayed data delayed by one clock cycle are combined, and the resulting target data is 8 groups, and each target data group can include 8 data groups.

[0108] Based on the feasible implementation of the above S120, the present application further provides combining the initial data and the delayed data according to a preset combination rule to obtain target data, including the steps of:

[0109] Determine the target number of groups corresponding to each target data group, and determine the initial high-order data in the initial data that is the same as the data of the target number of groups based on the sequence corresponding to the initial data;

[0110] According to the sequence corresponding to the delayed data, the delayed high-order data having the same number as the target number of groups in the delayed data are determined, and the delayed high-order data are deleted to obtain the delayed low-order data;

[0111] According to the preset combination rules, the initial high-order data and the delayed low-order data are combined to obtain the target data.

[0112] The target group number can be understood as the sequence of the target data group in all target data groups. For example, if all target data groups are data1 to data8, the target group number of data1 is the first group, and the target group number of data8 is the eighth group.

[0113] Sequence can be understood as the order in which data is arranged, for example, from left to right. "High-order data" usually refers to the binary bit with a larger bit number in the parallel data bus, corresponding to the high-significant bit of the data. The parallel data bus uses the "[MSB:LSB]" numbering method, such as datai[63:0] represents a 64-bit bus, where datai

[63] is the highest bit (MSB, Most Significant Bit) and datai[0] is the lowest bit (LSB, Least Significant Bit).

[0114] The initial high-order data is the data of the number of bits in the initial data corresponding to the target group number. For example, if the target group number is the second group, the number corresponding to the target group number is 2, and the initial data is datai[63:0], then the corresponding initial high-order data is datai[63:62].

[0115] The delayed high-order data is the data of the number of bits in the delayed data that corresponds to the target group number. For example, if the target group number is the second group, the number corresponding to the target group number is 2, and the delayed data is datai1[63:0], then the corresponding delayed high-order data is datai1[63:62], and the delayed low-order data is datai1[61:0].

[0116] For example, the initial data coming out of the serdes receiving channel is datai[63:0], the delayed data is datai1[63:0], there are 8 target data groups in total, and the data group corresponding to data2 is selected. The target group number corresponding to data2 is the second group, and the number corresponding to the target group number is 2. According to the binary arrangement of the delayed data, the corresponding 2-bit high-order data in the delayed data is determined to be datai1[63:62], and the delayed low-order data is datai1[61:0]; and the initial high-order data in the initial data is datai[63:62]; by determining the delayed low-order data as the high-order of the target data and the initial high-order data as the low-order of the target data, the target data is data2={datai1[62:0],datai

[63] }.

[0117] Based on this, combined shifting is the core step in generating a multi-phase offset data bus. Through delay and shift operations, eight groups of 64-bit data with different phases are generated, providing redundant candidates for subsequent downsampling. The preset combination rule can be understood as splicing the low bit of the delayed data with the high bit of the initial data. At the same time, the data will be shifted right by 1 bit each time, thereby generating eight groups of 64-bit buses with sequentially offset phases.

[0118] Based on the feasible implementation of the above S130, the present application further provides, for each target data group, extracting the median data in each group to obtain downsampled data corresponding to the target data group, and determining the target group in each group that matches the preamble code based on a preset check number, including the steps of:

[0119] Extract the median data of the group to obtain downsampled data;

[0120] Determine the target counter corresponding to each group, and determine the group check data of the intermediate sequence based on the data sequence of the group and the preset check number;

[0121] Determine whether the packet check data and the preamble match each other;

[0122] If the packet check data and the preamble match, the corresponding packet is determined to be the target packet, and the count of the target counter corresponding to the packet is increased by 1;

[0123] If the packet check data and the preamble do not match each other, it is determined that the packet corresponding to the packet check data is a non-target packet.

[0124] The target counter is used to record the number of target packets that match the preamble.

[0125] The packet check data is the data located in the middle sequence of the data packet and is used to check whether it matches the preamble code. For example, in bits 0 to 63 of the target data group, 7 bits are extracted for every 8 bits. Then the 8-bit data is the data packet corresponding to the target data group, and the 7 bits are the packet check data used for verification.

[0126] Furthermore, the preset check number can be 4, 6 and 7. For example, from bits 0 to 63 of the target data group, 7 bits are extracted for every 8 bits to determine whether the 7-bit data satisfies the alternating change of the preamble code, that is, whether one bit is extracted from the 7 bits and is 01010101 or 10101010 corresponding to the preamble code. If it is satisfied, the selection mark sel7x of the current data is set to 1, otherwise it is set to 0.

[0127] Based on this, by determining whether the group check data in the data group meets the regular alternating characteristics corresponding to the preamble code, the target group that matches the preamble code is determined, and the number of target groups is recorded through a counter, so that the target downsampling data can be determined later based on the number of target groups and their corresponding identifiers.

[0128] Based on the feasible implementation of the above S140, the present application further provides a method for determining a target identifier based on the number of target groups and a preset threshold, and determining target downsampled data based on the target identifier and the downsampled data, including the steps of:

[0129] Determine the target counters corresponding to each group and their counts to obtain the number of target groups;

[0130] Compare the number of target groups with the preset threshold to obtain a comparison result;

[0131] If the comparison result shows that the number of target groups is greater than the preset threshold, the counting identifier of the corresponding target counter is determined to obtain the target identifier;

[0132] If the comparison result shows that the target quantity is not greater than the preset threshold, the counting flag of the target counter is determined;

[0133] Target downsampling data is determined according to the target identifier and the downsampling data.

[0134] Among them, the counting identifier is the identifier corresponding to the counter. For example, from bits 0 to 63 of the target data group, 7 bits are extracted for every 8 bits to determine whether the 7-bit data meets the preamble code rule. The counter corresponds to 1 for each data group, which can be represented by cnt1 to cnt8. It is used to record the number of data groups that meet the preamble code rule. If a counter of cnt1 to cnt8 is greater than the set threshold, such as 6, the corresponding counter identifier is determined. The identifier can be represented by sel_bit7[X]. For example, the identifier corresponding to counter cnt1 is sel_bit7[1]. If cnt1>6, the corresponding identifier sel_bit7[1] is determined so that the target down-sampled data can be determined from multiple groups of down-sampled data based on the identifier.

[0135] Based on the feasible implementation of the above S140, the present application further provides determining target downsampled data according to the target identifier and the downsampled data, including the steps of:

[0136] Determine the downsampled data corresponding to each target data group, and determine, based on the target identifier, the target data group corresponding to the target identifier in the target data group as the downsampled data group;

[0137] Determine the down-sampled data corresponding to the down-sampled data group as the target down-sampled data, and output the target down-sampled data.

[0138] Among them, the downsampled data group is the target data group corresponding to the target identifier in each target data group; for example, the identifier corresponding to the counter cnt1 is sel_bit7[1], the preset threshold is 6, if cnt1>6, then the corresponding target identifier sel_bit7[1] is determined, and the target data group corresponding to the target identifier is data1, and the downsampled data is obtained by extracting the median data from the data group in the target data group, that is, after determining the target data group corresponding to the target identifier, the corresponding target downsampled data group can be determined, and data1 corresponds to The downsampled data group is dat1, dat1 includes {data1

[59] , data2

[51] , data3

[43] , data4

[35] , data5

[27] , data6

[19] , data7

[11] , data8【3】}, then the target downsampled data is dat1 including {data1

[59] , data2

[51] , data3

[43] , data4

[35] , data5

[27] , data6

[19] , data7

[11] , data8【3】}.

[0139] Please refer to Figure 2 , Figure 2 A sampling diagram of a downsampling method based on an LVDS channel provided in an embodiment of the present application; Figure 2 As shown, data of varying rates are preceded by a preamble as a frame header before sharing a high-speed LVDS bus. After these preambles are converted into serial data and sampled, their probability of metastable states is the same as that of the payload data. For N bits of oversampled data, the data is first delayed by one beat, and then two adjacent beats are reassembled into a predictable data bus with N possible bit formats. The middle bit of each possible bit format is extracted to form the corresponding downsampled data. By analyzing and statistically analyzing the regularity of these preambles, metastable states are avoided. The data bus with metastable data occurring precisely at the edge of the bit is selected, and the middle bit is extracted to complete the downsampling. Assuming the initial sampling is N times oversampling, the N-1 and N-2 bits of the resulting data bus are searched for signs of the preamble frame header. For example, a 1.25g code stream plus a 122-bit preamble 0101, these preambles become 1.25g serial data and after being adopted by a 10g clock, the probability of metastable state is similar to that of other data, such as Figure 3This is 1.25G serial data. The lower 24 bits of the 64-bit parallel data coming out of the serdies are oversampled 8x over the 10G channel, requiring 8x downsampling. The waveform shows that sequence numbers 743 to 762 are the preamble. Bits 5 to 12 are identical data, with bits 5, 11, and 12 experiencing metastable states. Bits 13 to 20 are single bits, with bits 13 and 20 experiencing metastable states. Therefore, one bit needs to be extracted from bits 8 or 9, and one bit from bits 16 and 17, completing the 8x downsampling.

[0140] In some embodiments of the present application, a preamble with an alternating pattern is determined, and before data of different rates share a high-speed LVDS bus, the fixed-pattern preamble is first added to the data as a frame header, thereby ensuring that the data oversampled by SERDE still includes regular data corresponding to the preamble. After sampling, the probability of these preambles appearing in a metastable state is the same as that of the payload data, so that they can be detected by the receiving end using the alternating pattern of the preamble. Data groups matching this pattern indicate that the sampling phase is in a data stable region (non-transition edge), thereby determining stable sampled data. Furthermore, by delaying and shifting the transmitted data, target data groups with sequentially shifted phases are generated, each corresponding to a different sampling phase. Multiple groups of downsampled data are determined by extracting intermediate bits from the data packets of each group of data, and each group of data is longitudinally tested to see whether it conforms to the 01 alternating pattern of the preamble to generate a selection mark. A counter is then used to count the continued validity of the mark, thereby locking in a channel of stable data, shielding against metastable interference, and achieving reliable downsampling.

[0141] In this way, through the steps of delay shift bit sequence generation, downsampled data capture, metastable avoidance, frame pattern learning, measurement and search, selection and judgment of multi-channel downsampled data, optimization algorithm in the downsampling selection process, frame header search algorithm, etc., the regularity of the preamble code is used to locate the stable sampling interval, and the alternating pattern of the preamble code can be detected by the receiving end. The data group that matches the pattern indicates that the sampling phase is in the data stable area (non-jump edge), and the probability of metastable state is significantly reduced; at the same time, a single group of data that accidentally matches the preamble code pattern will be excluded because the counter does not reach the threshold, and only the continuously stable preamble code characteristics are recognized, thereby filtering out accidental interference, improving the accuracy of sampling data at different rates and the quality of the sampling results.

[0142] Figure 3 Schematic diagram of a downsampling device 300 based on LVDS channel provided in an embodiment of the present application. Figure 3 As shown, the downsampling device 300 based on the LVDS channel includes: a transmission module 310, a data determination module 320, a group determination module 330, and an identification determination module 340; wherein:

[0143] The transmission module 310 is used to determine the number of bits of the data to be transmitted and the corresponding preamble, and transmit the data to be transmitted through the SerDes channel to obtain initial data. The data to be transmitted is the data obtained through the LVDS channel;

[0144] The data determination module 320 is used to determine the number of target data groups and the grouping in each target data group according to the number of bits, and determine the target data corresponding to the initial data according to the clock of the SerDes channel and the preset combination rule;

[0145] The group determination module 330 is used to extract the median data in each group for each target data group to obtain the downsampled data corresponding to the target data group, and determine the target group in each group that matches the preamble according to a preset number of checks;

[0146] The identifier determination module 340 is configured to determine a target identifier according to the number of target groups and a preset threshold, and to determine target down-sampled data according to the target identifier and the down-sampled data.

[0147] In the embodiment of the present application, the transmission module 310 may also be specifically configured to:

[0148] Obtain the data to be transmitted and determine the number of bits corresponding to the data to be transmitted;

[0149] Determine the preamble code and add the preamble code before the data to be transmitted;

[0150] According to the serdes channel, the data to be transmitted with the preamble added is transmitted to obtain the initial data.

[0151] In the embodiment of the present application, the data determination module 320 may also be specifically configured to:

[0152] Determine the number of target data groups and the grouping within the target data groups based on the number of digits;

[0153] According to the clock, the initial data is delayed by one clock cycle to obtain delayed data;

[0154] According to the preset combination rules, the initial data and the delayed data are combined to obtain the target data.

[0155] In the embodiment of the present application, the data determination module 320 may also be specifically configured to:

[0156] Determine the target number of groups corresponding to each target data group, and determine the initial high-order data in the initial data that is the same as the data of the target number of groups based on the sequence corresponding to the initial data;

[0157] According to the sequence corresponding to the delayed data, the delayed high-order data having the same number as the target number of groups in the delayed data are determined, and the delayed high-order data are deleted to obtain the delayed low-order data;

[0158] According to the preset combination rules, the initial high-order data and the delayed low-order data are combined to obtain the target data.

[0159] In the embodiment of the present application, the group determination module 330 may also be specifically configured to:

[0160] Extract the median data of the group to obtain downsampled data;

[0161] Determine the target counter corresponding to each group, and determine the group check data of the intermediate sequence based on the data sequence of the group and the preset check number;

[0162] Determine whether the packet check data and the preamble match each other;

[0163] If the packet check data and the preamble match, the corresponding packet is determined to be the target packet, and the count of the target counter corresponding to the packet is increased by 1;

[0164] If the packet check data and the preamble do not match each other, it is determined that the packet corresponding to the packet check data is a non-target packet.

[0165] In the embodiment of the present application, the identification determination module 340 may also be specifically configured to:

[0166] Determine the target counters corresponding to each group and their counts to obtain the number of target groups;

[0167] Compare the number of target groups with the preset threshold to obtain a comparison result;

[0168] If the comparison result shows that the number of target groups is greater than the preset threshold, the counting identifier of the corresponding target counter is determined to obtain the target identifier;

[0169] If the comparison result shows that the target quantity is not greater than the preset threshold, the counting flag of the target counter is determined;

[0170] Target downsampling data is determined according to the target identifier and the downsampling data.

[0171] In the embodiment of the present application, the identification determination module 340 may also be specifically configured to:

[0172] Determine the downsampled data corresponding to each target data group, and determine, based on the target identifier, the target data group corresponding to the target identifier in the target data group as the downsampled data group;

[0173] Determine the down-sampled data corresponding to the down-sampled data group as the target down-sampled data, and output the target down-sampled data.

[0174] Figure 4 This is a schematic diagram of the structure of the device provided in the embodiment of this application. Figure 4 As shown, the device 400 includes:

[0175] The device 400 may include one or more processors 401 , one or more computer-readable storage media memories 402 , a communication component 403 , and other components. The processor 401 , the memory 402 , and the communication component 403 are connected via a bus 404 .

[0176] In a specific implementation process, at least one processor 401 executes the computer-executable instructions stored in the memory 402, so that the at least one processor 401 performs the above-mentioned downsampling method based on the LVDS channel.

[0177] The specific implementation process of the processor 401 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0178] Furthermore, the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), or application-specific integrated circuits (ASICs). A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in this application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0179] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0180] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0181] In some embodiments, a computer program product is further provided, including a computer program or instructions, which implement the steps of any of the above-mentioned LVDS channel-based downsampling methods when executed by a processor.

[0182] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0183] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be accomplished by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0184] To this end, an embodiment of the present application provides a computer-readable storage medium, which stores multiple program codes. The program codes can be loaded by a processor to execute the steps of any LVDS channel-based downsampling method provided in the embodiment of the present application.

[0185] The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0186] According to one aspect of the present application, a computer program product or a computer program is provided. The computer program product or the computer program comprises computer instructions stored in a computer-readable storage medium.

[0187] Since the instructions stored in the storage medium can execute the steps of any LVDS channel-based downsampling method provided in the embodiments of the present application, the beneficial effects that can be achieved by any LVDS channel-based downsampling method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0188] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims set forth above.

[0189] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A downsampling method based on LVDS channel, characterized in that, The method comprises: Determine the number of bits of data to be transmitted and the corresponding preamble, and transmit the data to be transmitted according to the serdes channel to obtain initial data, where the data to be transmitted is data obtained through the lvds channel; Determine the number of target data groups and the grouping within each target data group based on the number of bits, and determine the target data corresponding to the initial data based on the clock of the SerDes channel and a preset combination rule; the preset combination rule is to concatenate the low bits of the delayed data with the high bits of the initial data, and simultaneously right-shift the data by 1 bit each time, thereby generating a combination rule for 8 groups of 64-bit buses with sequentially shifted phases; the delayed data is the delayed data obtained by delaying the initial data by one clock cycle based on the clock; For each of the target data groups, extract the median data in each of the groups to obtain downsampled data corresponding to the target data group, and determine the target group in each of the groups that matches the preamble according to a preset number of checks; A target identifier is determined according to the number of the target groups and a preset threshold, and target down-sampled data is determined according to the target identifier and the down-sampled data.

2. The method according to claim 1, characterized in that The step of determining the number of bits of data to be transmitted and the corresponding preamble, and transmitting the data to be transmitted according to the serdes channel to obtain initial data, includes: Acquire the data to be transmitted, and determine the number of bits corresponding to the data to be transmitted; Determine the preamble, and add the preamble to the data to be transmitted; The data to be transmitted with the preamble added thereto is transmitted according to the serdes channel to obtain the initial data.

3. The method according to claim 1, characterized in that The step of determining the number of target data groups and the grouping in each corresponding target data group according to the number of bits, and determining the target data corresponding to the initial data according to the clock on the user side of the serdes channel, a preset combination rule, and the initial data, includes: determining the number of groups of the target data and the grouping of the target data groups according to the number of bits; According to the clock, the initial data is delayed by one clock cycle to obtain delayed data; The initial data and the delayed data are combined according to the preset combination rule to obtain the target data.

4. The method according to claim 3, characterized in that The combining of the initial data and the delayed data according to the preset combination rule to obtain the target data includes: Determine the target number of groups corresponding to each target data group, and determine the initial high-order data in the initial data that is the same as the data of the target number of groups according to the sequence corresponding to the initial data; Determine, according to a sequence corresponding to the delayed data, delayed high-order data having the same number as the target number of groups in the delayed data, and delete the delayed high-order data to obtain delayed low-order data; The initial high-order data and the delayed low-order data are combined according to the preset combination rule to obtain the target data.

5. The method according to claim 1, wherein For each of the target data groups, extracting the median data in each of the groups to obtain downsampled data corresponding to the target data group, and determining a target group in each of the groups that matches the preamble according to a preset check number, including: Extracting the median data of the group to obtain the downsampled data; Determining a target counter corresponding to each of the groups, and determining group check data of an intermediate sequence according to the data sequence of the group and the preset check number; Determining whether the packet check data and the preamble match each other; If the packet check data and the preamble match, determining that the corresponding packet is the target packet, and increasing the count of the target counter corresponding to the packet by 1; If the packet verification data and the preamble do not match each other, it is determined that the packet corresponding to the packet verification data is a non-target packet.

6. The method according to claim 1, characterized in that The determining of a target identifier according to the number of the target groups and a preset threshold, and determining target down-sampling data according to the target identifier and the down-sampling data, includes: Determine the target counters corresponding to the respective groups and the counts thereof to obtain the number of the target groups; Comparing the number of the target groups with the preset threshold to obtain a comparison result; If the comparison result is that the number of the target groups is greater than the preset threshold, determining the corresponding counting identifier of the target counter to obtain the target identifier; If the comparison result shows that the number of the target groups is not greater than the preset threshold, then the counting flag of the target counter is not determined; The target down-sampling data is determined according to the target identifier and the down-sampling data.

7. The method according to claim 6, characterized in that The determining the target down-sampling data according to the target identifier and the down-sampling data includes: Determining the downsampled data corresponding to each of the target data groups, and determining, based on the target identifier, the target data group corresponding to the target identifier among the target data groups as the downsampled data group; The down-sampled data corresponding to the down-sampled data group is determined to be the target down-sampled data, and the target down-sampled data is output.

8. A downsampling device based on LVDS channel, characterized in that: The device is used to perform the LVDS channel-based downsampling method according to any one of claims 1 to 7, and the device includes: A transmission module is used to determine the number of bits of data to be transmitted and the corresponding preamble, and transmit the data to be transmitted according to the SerDes channel to obtain initial data, where the data to be transmitted is the data obtained through the LVDS channel; a data determination module, configured to determine the number of target data groups and the grouping within each target data group based on the number of bits, and determine the target data corresponding to the initial data based on the clock of the SerDes channel and a preset combination rule, wherein the data to be transmitted is data acquired through the LVDS channel; the preset combination rule is to concatenate the low bits of the delayed data with the high bits of the initial data, and simultaneously right-shift the data by 1 bit each time, thereby generating a combination rule for 8 groups of 64-bit buses with sequentially offset phases; the delayed data is the delayed data obtained by delaying the initial data by one clock cycle based on the clock; a group determination module, configured to extract, for each target data group, the median data within each of the groups to obtain downsampled data corresponding to the target data group, and determine, based on a preset number of checks, a target group in each of the groups that matches the preamble; The identifier determination module is used to determine the target identifier according to the number of the target groups and a preset threshold, and determine the target down-sampled data according to the target identifier and the down-sampled data.

9. A computer device, characterized in that: include: one or more processors; Memory; One or more programs, wherein the one or more programs are stored in a memory and configured to be executed by one or more processors, the one or more programs being configured to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 7.

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