FPGA-ASIC (Field Programmable Gate Array-Application Specific Integrated Circuit) hybrid heterogeneous architecture energy consumption optimization method and device

Abstract

The invention relates to the technical field of computers, and provides an FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization method and device, and the method comprises the steps: constructing a plurality of initial virtual models of an FPGA-ASIC hybrid heterogeneous architecture; wherein the FPGA-ASIC hybrid heterogeneous architecture comprises a plurality of hardware accelerators, and the distribution states of all the hardware accelerators in all the initial virtual models are different; each initial virtual model is controlled to execute a target task, and execution efficiency information of each initial virtual model is recorded; determining a target virtual model in the initial virtual models based on the execution efficiency information of the initial virtual models; and adjusting the distribution state of a virtual hardware accelerator in the target virtual model so as to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture. According to the method, the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture is optimized.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to an energy consumption optimization method and device for an FPGA-ASIC hybrid heterogeneous architecture. Background Art

[0002] FPGA (Chinese name: Field Programmable Gate Array) and ASIC (Chinese name: Application Specific Integrated Circuit), as two mainstream hardware accelerators, each have unique advantages. FPGA, with its high flexibility and programmability, can quickly perform hardware customization and optimization for different tasks, while ASIC is a dedicated hardware accelerator for specific applications and can provide higher performance. Combining these two technologies, the FPGA-ASIC hybrid heterogeneous architecture came into being, aiming to improve computing performance and efficiency through the optimal configuration of resources. However, in the design process of the existing FPGA-ASIC hybrid heterogeneous architecture, only the improvement of computing performance and efficiency is concerned, and the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture is not optimized. Summary of the Invention

[0003] This application provides an energy consumption optimization method and device for an FPGA-ASIC hybrid heterogeneous architecture to solve the problems raised in the above background art.

[0004] In a first aspect, this application provides an energy consumption optimization method for an FPGA-ASIC hybrid heterogeneous architecture, including: Constructing a plurality of initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes a plurality of hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; Controlling each of the initial virtual models to execute a target task respectively, and respectively recording the execution efficiency information of each of the initial virtual models; Determining a target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models; Adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0005] In a possible implementation manner, the constructing a plurality of initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture includes: Obtaining the design information of the FPGA-ASIC hybrid heterogeneous architecture; the design information includes integrated carrier information, a plurality of hardware accelerators, and connection information between the hardware accelerators; wherein, the integrated carrier information includes the material and size of the integrated carrier, the functions of the hardware accelerators are different from each other, and the hardware accelerators include FPGA and ASIC; Construct a virtual integrated carrier based on the integrated carrier information, and divide the virtual integrated surface of the virtual integrated carrier according to the number of the hardware accelerators to obtain a plurality of hardware accelerator integration regions; Construct a plurality of the initial virtual models based on each of the hardware accelerator integration regions, each of the hardware accelerators, and the connection information.

[0006] In a possible implementation manner, the constructing a plurality of the initial virtual models based on each of the hardware accelerator integration regions, each of the hardware accelerators, and the connection information includes: Construct a hardware accelerator set corresponding to each of the hardware accelerator integration regions respectively; wherein, each of the hardware accelerator sets is a set composed of each of the hardware accelerators; Perform a Cartesian product operation on each of the hardware accelerator sets to obtain a plurality of initial hardware accelerator combinations; Determine a target hardware accelerator combination among each of the initial hardware accelerator combinations; wherein, the target hardware accelerator combination does not include the same hardware accelerator; For each of the target hardware accelerator combinations, respectively construct a corresponding virtual hardware accelerator in the hardware accelerator integration region corresponding to each of the hardware accelerators in the target hardware accelerator combination, and connect each of the virtual hardware accelerators based on the connection information to obtain the initial virtual model corresponding to the target hardware accelerator combination.

[0007] In a possible implementation manner, the execution efficiency information includes an execution duration and an energy consumption, and the determining a target virtual model among each of the initial virtual models based on the execution efficiency information of each of the initial virtual models includes: Obtain a delay threshold of the target task; Determine an intermediate target virtual model among each of the initial virtual models based on the delay threshold; wherein, the execution duration corresponding to the intermediate target virtual model is less than the delay threshold; Determine the intermediate target virtual model with the minimum energy consumption as the target virtual model.

[0008] In a possible implementation manner, on the virtual integrated surface of the target virtual model, the distance between the center points of any two adjacent virtual hardware accelerators is equal, and the adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture includes: Obtain the computing complexity of each of the virtual hardware accelerators; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the computing complexity of each of the virtual hardware accelerators.

[0009] In a possible implementation, adjusting the distribution state of the virtual hardware accelerators in the target virtual model based on the computational complexity of each of the virtual hardware accelerators includes: Obtain the standard deviation of each of the computational complexities, and compare the standard deviation with a preset standard deviation; If the standard deviation is not greater than the preset standard deviation, determine whether the maximum computational complexity among each of the computational complexities is greater than a preset computational complexity; If the maximum computational complexity among each of the computational complexities is greater than the preset computational complexity, keep the original distribution state of the virtual hardware accelerators in the target virtual model unchanged; If the maximum computational complexity among each of the computational complexities is not greater than the preset computational complexity, shorten the distance between the center points of each adjacent virtual hardware accelerator by a preset percentage; If the standard deviation is greater than the preset standard deviation, determine a target computational complexity among each of the computational complexities; wherein, the target computational complexity is greater than the preset computational complexity; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the virtual hardware accelerators corresponding to each of the target computational complexities.

[0010] In a second aspect, the present application provides an FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization device, including: A construction module, configured to construct a plurality of initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes a plurality of hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; A control module, configured to control each of the initial virtual models to execute a target task respectively, and record the execution efficiency information of each of the initial virtual models respectively; A determination module, configured to determine a target virtual model among each of the initial virtual models based on the execution efficiency information of each of the initial virtual models; An adjustment module, configured to adjust the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0011] The present application provides a method and apparatus for optimizing the energy consumption of an FPGA-ASIC hybrid heterogeneous architecture. The method includes: constructing a plurality of initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes a plurality of hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; controlling each of the initial virtual models to execute a target task respectively, and respectively recording the execution efficiency information of each of the initial virtual models; determining a target virtual model from each of the initial virtual models based on the execution efficiency information of each of the initial virtual models; and adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture. On the one hand, by controlling each of the initial virtual models to execute a target task respectively, respectively recording the execution efficiency information of each of the initial virtual models, and determining a target virtual model from each of the initial virtual models based on the execution efficiency information of each of the initial virtual models, the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture is optimized. On the other hand, by adjusting the distribution state of the virtual hardware accelerators in the target virtual model, it helps to further optimize the energy consumption while improving the FPGA-ASIC hybrid heterogeneous architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a schematic flowchart of the method for optimizing the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture provided by the embodiment of the present application; Figure 2 It is a schematic block diagram of the structure of the apparatus for optimizing the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture provided by the embodiment of the present application; Figure 3 It is a schematic block diagram of the structure of the terminal device provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0015] The flowcharts shown in the accompanying drawings are merely illustrative examples, and do not necessarily include all contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged, so the actual execution order may change based on the actual situation.

[0016] It should also be understood that the terms used in the specification of this application are merely for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0017] It should be further understood that the term "and / or" used in the specification of this application and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0018] The following will describe in detail some embodiments of this application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0019] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of the energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture provided by the embodiment of this application. As Figure 1 shown, the energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture provided by the embodiment of this application includes steps S1 to S4.

[0020] Step S1: Construct multiple initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes multiple hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different.

[0021] Among them, the hardware accelerator includes FPGA and ASIC. Specifically, step S1 includes the following steps: Obtain the design information of the FPGA-ASIC hybrid heterogeneous architecture; the design information includes integrated carrier information, multiple hardware accelerators, and connection information between each hardware accelerator; wherein, the integrated carrier information includes the material and size of the integrated carrier, the functions of each hardware accelerator are different from each other, and the hardware accelerator includes FPGA and ASIC; Construct a virtual integrated carrier based on the integrated carrier information, and divide the virtual integrated surface of the virtual integrated carrier according to the number of the hardware accelerators to obtain a plurality of hardware accelerator integration regions; specifically, first, construct the geometric structure of the virtual integrated carrier based on the size of the integrated carrier, and endow the geometric structure with material properties based on the material of the integrated carrier, and then, evenly divide the virtual integrated surface of the virtual integrated carrier according to the number of the hardware accelerators to obtain a plurality of hardware accelerator integration regions; the areas of the hardware accelerator integration regions are equal; Construct a plurality of the initial virtual models based on the hardware accelerator integration regions, the hardware accelerators and the connection information.

[0022] Wherein, the constructing a plurality of the initial virtual models based on the hardware accelerator integration regions, the hardware accelerators and the connection information includes the following steps: Respectively construct a hardware accelerator set corresponding to each of the hardware accelerator integration regions; wherein, each of the hardware accelerator sets is a set composed of the hardware accelerators; Perform Cartesian product operations on the hardware accelerator sets to obtain a plurality of initial hardware accelerator combinations; Determine a target hardware accelerator combination in each of the initial hardware accelerator combinations; wherein, the target hardware accelerator combination does not include the same hardware accelerator; For each of the target hardware accelerator combinations, respectively construct a corresponding virtual hardware accelerator in the hardware accelerator integration region corresponding to each of the hardware accelerators in the target hardware accelerator combination, and connect the virtual hardware accelerators based on the connection information to obtain an initial virtual model corresponding to the target hardware accelerator combination; specifically, construct a corresponding virtual hardware accelerator at the center position of each of the hardware accelerator integration regions.

[0023] It can be understood that through the method of step S1, various distribution states of the hardware accelerators of the FPGA-ASIC hybrid heterogeneous architecture can be obtained, which helps to effectively optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0024] Step S2, control each of the initial virtual models to execute a target task respectively, and respectively record the execution efficiency information of each of the initial virtual models.

[0025] Wherein, the execution efficiency information includes execution duration and energy consumption.

[0026] Step S3, determine a target virtual model in each of the initial virtual models based on the execution efficiency information of each of the initial virtual models.

[0027] Specifically, step S3 includes the following steps: Obtain the delay threshold of the target task; Based on the delay threshold, determine an intermediate target virtual model among the initial virtual models; wherein, the execution duration corresponding to the intermediate target virtual model is less than the delay threshold; Determine the intermediate target virtual model with the minimum energy consumption as the target virtual model.

[0028] It can be understood that the method provided in step S3 can ensure that the energy consumption during the execution of the target task is minimized when the target virtual model meets the delay threshold of the target task.

[0029] Step S4: Adjust the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0030] Specifically, step S4 includes the following steps: Obtain the computational complexity of each virtual hardware accelerator; wherein, the computational complexity of each hardware accelerator is set by an engineer during the design of the FPGA-ASIC hybrid heterogeneous architecture and recorded in the design information of the FPGA-ASIC hybrid heterogeneous architecture. The design information of the FPGA-ASIC hybrid heterogeneous architecture is stored in a preset database. Specifically, obtain the design information of the FPGA-ASIC hybrid heterogeneous architecture in the preset database, and obtain the computational complexity of each hardware accelerator in the design information. For each virtual hardware accelerator, obtain the computational complexity corresponding to the virtual hardware accelerator based on the hardware accelerator corresponding to the virtual hardware accelerator; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the computational complexity of each virtual hardware accelerator.

[0031] Among them, the adjustment of the distribution state of the virtual hardware accelerators in the target virtual model based on the computational complexity of each virtual hardware accelerator includes the following steps: Obtain the standard deviation of each computational complexity and compare the standard deviation with a preset standard deviation; If the standard deviation is not greater than the preset standard deviation, determine whether the maximum computational complexity among each computational complexity is greater than a pre-designed computational complexity; If the maximum computational complexity among each computational complexity is greater than the pre-designed computational complexity, keep the original distribution state of the virtual hardware accelerators in the target virtual model unchanged; If the maximum computational complexity among the respective computational complexities is not greater than the pre-designed computational complexity, shorten the distance between the center points of adjacent virtual hardware accelerators by a preset percentage; If the standard deviation is greater than the preset standard deviation, determine a target computational complexity among the respective computational complexities; wherein, the target computational complexity is greater than the pre-designed computational complexity; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the virtual hardware accelerators corresponding to the respective target computational complexities; specifically, appropriately increase the distance between the center points of the virtual hardware accelerators corresponding to the respective target computational complexities and the virtual hardware accelerators connected thereto, and appropriately adjust the positions of the remaining virtual hardware accelerators; for example, if the computational complexities of two adjacent virtual hardware accelerators are both very small, the distance between the center points of the two adjacent hardware accelerators can be appropriately reduced.

[0032] It can be understood that the computational complexity of the hardware accelerator is positively correlated with the heat generated by the hardware accelerator during task execution. If the distribution of the hardware accelerators around the hardware accelerator with a higher computational complexity is too concentrated, it is easy for the FPGA-ASIC hybrid heterogeneous architecture to exhibit a heat concentration phenomenon during task execution, thereby affecting the computational performance of the FPGA-ASIC hybrid heterogeneous architecture. The distance between the hardware accelerators is negatively correlated with the duration required for the FPGA-ASIC hybrid heterogeneous architecture to execute tasks. If the distance between the hardware accelerators is relatively far, it is easy to cause computational delays. The method provided in step S4 can prevent the occurrence of heat concentration phenomena as much as possible while ensuring that the computation of the FPGA-ASIC hybrid heterogeneous architecture is not delayed.

[0033] The method provided in this embodiment, on the one hand, optimizes the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture by controlling each of the initial virtual models to execute the target task, respectively recording the execution efficiency information of each of the initial virtual models, and determining the target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models. On the other hand, by adjusting the distribution state of the virtual hardware accelerators in the target virtual model, it helps to further optimize the energy consumption while improving the FPGA-ASIC hybrid heterogeneous architecture.

[0034] Please refer to Figure 2 , Figure 2 which is a schematic structural block diagram of the FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization device 100 provided by an embodiment of the present application. As Figure 2 shown, the FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization device 100 provided by an embodiment of the present application includes: A construction module 110 for constructing multiple initial virtual models of an FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes multiple hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different.

[0035] A control module 120 for controlling each of the initial virtual models to execute a target task respectively and recording the execution efficiency information of each of the initial virtual models respectively.

[0036] A determination module 130 for determining a target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models.

[0037] An adjustment module 140 for adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0038] It should be noted that those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working processes of the above-described device and each module can refer to the processes in the foregoing embodiments of the method for optimizing the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture, and will not be elaborated herein.

[0039] The device 100 for optimizing the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture provided in the above embodiment can be implemented in the form of a computer program, and this computer program can run on a terminal device 200 as shown in Figure 3 Figure.

[0040] Please refer to Figure 3 , Figure 3 which is a schematic block diagram of the structure of the terminal device 200 provided in the embodiment of the present application. The terminal device 200 includes a processor 201 and a memory 202. The processor 201 and the memory 202 are connected through a device bus 203. Among them, the memory 202 may include a non-volatile storage medium and an internal memory.

[0041] The non-volatile storage medium can store a computer program. This computer program includes program instructions. When the program instructions are executed by the processor 201, the processor 201 can be enabled to execute any of the above methods for optimizing the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0042] The processor 201 is used to provide computing and control capabilities to support the operation of the entire terminal device 200.

[0043] The internal memory provides an environment for the operation of a computer program in a non-volatile storage medium. When the computer program is executed by the processor 201, the processor 201 can be caused to execute any of the above-mentioned FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization methods.

[0044] Those skilled in the art can understand that Figure 3 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the terminal device 200 involved in the solution of this application. The specific terminal device 200 may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0045] It should be understood that the processor 201 may be a central processing unit (CPU), and the processor 201 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0046] Among them, in some embodiments, the processor 201 is used to run a computer program stored in the memory to implement the following steps: Construct multiple initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes multiple hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; Control each of the initial virtual models to execute the target task respectively, and record the execution efficiency information of each of the initial virtual models respectively; Determine a target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models; Adjust the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

[0047] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described terminal device 200 can refer to the process of the foregoing FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization method, which will not be elaborated here.

[0048] The embodiment of the present application further provides a computer-readable storage medium storing a computer program, and when the computer program is executed by one or more processors, the one or more processors are caused to implement the FPGA-ASIC hybrid heterogeneous architecture energy consumption optimization method provided by the embodiment of the present application.

[0049] Wherein, the computer-readable storage medium may be an internal storage unit of the terminal device 200 in the foregoing embodiment, such as the hard disk or memory of the terminal device 200. The computer-readable storage medium may also be an external storage device of the terminal device 200, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped with the terminal device 200.

[0050] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An energy consumption optimization method for an FPGA-ASIC hybrid heterogeneous architecture, characterized in that Including: Constructing a plurality of initial virtual models of an FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes a plurality of hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; Controlling each of the initial virtual models to execute a target task respectively, and respectively recording the execution efficiency information of each of the initial virtual models; Determining a target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models; Adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

2. The energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture according to claim 1, wherein The constructing a plurality of initial virtual models of the FPGA-ASIC hybrid heterogeneous architecture includes: Obtaining the design information of the FPGA-ASIC hybrid heterogeneous architecture; the design information includes integrated carrier information, a plurality of hardware accelerators, and connection information between the hardware accelerators; wherein, the integrated carrier information includes the material and size of the integrated carrier, the functions of the hardware accelerators are different from each other, and the hardware accelerators include FPGA and ASIC; Constructing a virtual integrated carrier based on the integrated carrier information, and dividing the virtual integrated surface of the virtual integrated carrier based on the number of the hardware accelerators to obtain a plurality of hardware accelerator integration regions; Constructing a plurality of the initial virtual models based on each of the hardware accelerator integration regions, each of the hardware accelerators, and the connection information.

3. The energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture according to claim 2, wherein The constructing a plurality of the initial virtual models based on each of the hardware accelerator integration regions, each of the hardware accelerators, and the connection information includes: Respectively constructing a hardware accelerator set corresponding to each of the hardware accelerator integration regions; wherein, each of the hardware accelerator sets is a set composed of each of the hardware accelerators; Performing a Cartesian product operation on each of the hardware accelerator sets to obtain a plurality of initial hardware accelerator combinations; Determining a target hardware accelerator combination among each of the initial hardware accelerator combinations; wherein, the target hardware accelerator combination does not include the same hardware accelerator; For each of the target hardware accelerator combinations, respectively constructing a corresponding virtual hardware accelerator in the hardware accelerator integration region corresponding to each of the hardware accelerators in the target hardware accelerator combination, and connecting the virtual hardware accelerators based on the connection information to obtain an initial virtual model corresponding to the target hardware accelerator combination.

4. The energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture according to claim 1, wherein The execution efficiency information includes execution duration and energy consumption. The determining a target virtual model among the initial virtual models based on the execution efficiency information of each of the initial virtual models includes: Obtaining a delay threshold of the target task; Determining an intermediate target virtual model among the initial virtual models based on the delay threshold; wherein, the execution duration corresponding to the intermediate target virtual model is less than the delay threshold; Determining the intermediate target virtual model with the minimum energy consumption as the target virtual model.

5. The energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture according to claim 1, wherein On the virtual integration surface of the target virtual model, the distance between the center points of any two adjacent virtual hardware accelerators is equal. Adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture includes: Obtain the computational complexity of each of the virtual hardware accelerators; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the computational complexity of each of the virtual hardware accelerators.

6. The energy consumption optimization method for the FPGA-ASIC hybrid heterogeneous architecture according to claim 5, characterized in that The adjusting the distribution state of the virtual hardware accelerators in the target virtual model based on the computational complexity of each of the virtual hardware accelerators includes: Obtain the standard deviation of each of the computational complexities and compare the standard deviation with a preset standard deviation; If the standard deviation is not greater than the preset standard deviation, determine whether the maximum computational complexity among each of the computational complexities is greater than a preset computational complexity; If the maximum computational complexity among each of the computational complexities is greater than the preset computational complexity, keep the original distribution state of the virtual hardware accelerators in the target virtual model unchanged; If the maximum computational complexity among each of the computational complexities is not greater than the preset computational complexity, shorten the distance between the center points of each adjacent virtual hardware accelerator by a preset percentage; If the standard deviation is greater than the preset standard deviation, determine a target computational complexity among each of the computational complexities; wherein, the target computational complexity is greater than the preset computational complexity; Adjust the distribution state of the virtual hardware accelerators in the target virtual model based on the virtual hardware accelerators corresponding to each of the target computational complexities.

7. An energy consumption optimization device for an FPGA-ASIC hybrid heterogeneous architecture, characterized in that Includes: A construction module for constructing a plurality of initial virtual models of an FPGA-ASIC hybrid heterogeneous architecture; wherein, the FPGA-ASIC hybrid heterogeneous architecture includes a plurality of hardware accelerators, and the distribution states of the hardware accelerators in each of the initial virtual models are different; A control module for controlling each of the initial virtual models to execute a target task respectively and recording the execution efficiency information of each of the initial virtual models respectively; A determination module for determining a target virtual model among each of the initial virtual models based on the execution efficiency information of each of the initial virtual models; An adjustment module for adjusting the distribution state of the virtual hardware accelerators in the target virtual model to optimize the energy consumption of the FPGA-ASIC hybrid heterogeneous architecture.

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