Design layout splitting method and related product

Abstract

The invention provides a design layout splitting method and a related product. The design layout splitting method comprises the steps of obtaining layout units of a design layout; obtaining a to-be-split graph of the layout unit from all graphs of the layout unit; the number of the to-be-split graphs of the layout unit is smaller than or equal to the number of all graphs of the layout unit; and splitting the to-be-split graph of the layout unit to obtain a splitting scheme of the layout unit. According to the design layout splitting method, due to the fact that the multi-level layout units of the design layout can be obtained, the design layout does not need to be subjected to the planarization process and then window division, in other words, it is avoided that part of computing resources and time consumption are used for carrying out the planarization process, and the usage amount of the computing resources and time consumption are reduced. And the splitting result is excellent.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for splitting a design layout and related products. Background Art

[0002] In the process of semiconductor manufacturing, the lithography process of advanced nodes improves the spatial resolution of a layer of features by using multiple exposures or multi-patterning techniques, thereby realizing the manufacturability of the layer of features. For example, if a feature layer requires N exposures or patterning processes (i.e., N exposures or N-fold patterning), where N is a positive integer not less than 2, then the layout pattern corresponding to the layout design of the feature layer will be split into N different groups for the corresponding exposure or patterning process. The pattern splitting process is performed in a manner similar to solving the coloring problem in graph theory. Therefore, the pattern splitting process is sometimes referred to as the "coloring process", and if the layout pattern of the layout design can be split into N different patterning groups, then the layout design is called "N-colorable". The performance of the pattern splitting process is usually computationally resource-intensive and time-consuming for the layout design of large-scale integrated circuits.

[0003] The specific steps of the existing pattern splitting are as follows: Step 1, obtain the layout design of a large-scale integrated circuit; Step 2, construct an analysis window for all the graphics in the layout design; Step 3, perform the coloring process for all the graphics in each analysis window; Step 4, determine whether all the windows have been analyzed; Step 5, output the graphic coloring results of each window after summarizing. In the existing automatic splitting process for the layout design of large-scale integrated circuits, after reading the layout design, it is necessary to flatten the original hierarchical structure to obtain all the flattened graphics. Therefore, some computational resources and time are required for the flattening process. In addition, since all the constructed windows will perform separate coloring processes, if there is a large graphic spanning multiple windows, it is impossible to perform integral coloring for this graphic, which may lead to splitting failure caused by different colors being applied to some complete graphics. At the same time, if there is a non-colorable structure in the graphics at the window boundary, this process cannot identify it, resulting in poor splitting results. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a method for splitting a design layout that overcomes or at least partially solves the above problems.

[0005] An object of the present invention is to utilize the original hierarchical structure in the design layout to avoid some computational resources and time for the flattening process, and reduce the amount of computational resources used and the time consumed.

[0006] A further object of the present invention is to prevent the existence of large graphics spanning multiple windows, achieve integral coloring of the graphics, and thus prevent the splitting failure caused by different colors being applied to some complete graphics.

[0007] Another further object of the present invention is to prevent the coloring influence between the graphics at the window boundaries and prevent the occurrence of poor splitting results.

[0008] In particular, the present invention provides a method for splitting a design layout, wherein the design layout has multi-level layout units, the lowest-level layout unit is a basic layout unit, and the basic layout unit includes a circuit block; the high-level layout units include at least two low-level layout units;

[0009] The method for splitting the design layout includes:

[0010] Obtaining the layout units of the design layout;

[0011] Obtaining the graphics to be split of the layout unit from all the graphics of the layout unit; the number of the graphics to be split of the layout unit is less than or equal to the number of all the graphics of the layout unit;

[0012] Splitting the graphics to be split of the layout unit to obtain a splitting scheme of the layout unit;

[0013] Obtaining an overall splitting scheme of the design layout according to the splitting schemes of all the layout units.

[0014] Optionally, at least two of the low-level layout units in each high-level layout unit have the same level; or,

[0015] Among at least two of the low-level layout units in each high-level layout unit, at least one of the low-level layout units has a different level from the other low-level layout units.

[0016] Optionally, the step of obtaining the graphics to be split of the layout unit from all the graphics of the layout unit includes:

[0017] When the layout unit is a basic layout unit, taking the graphics of the layout unit as the graphics to be split of the layout unit;

[0018] When the layout unit has low-level layout units, first extracting the edge graphics from the graphics to be split of each low-level layout unit in the layout unit, and then taking the edge graphics extracted from each low-level layout unit in the layout unit as the graphics to be split of the layout unit.

[0019] Optionally, the step of extracting an edge graph from the graph to be split in the layout unit includes:

[0020] Obtain the layout unit boundary region of the layout unit;

[0021] Determine whether each graph to be split has a part located in the layout unit boundary region;

[0022] If so, determine that the graph to be split is an edge graph.

[0023] Optionally, the step of obtaining the layout unit boundary region of the layout unit includes:

[0024] Obtain the unit boundary of the layout unit, and the graph to be split in the layout unit is located inside the unit boundary;

[0025] Generate an edge graph boundary at a preset distance inside the unit boundary, and use the region between the edge graph boundary and the unit boundary as the layout unit boundary region.

[0026] Optionally, when the layout unit has a low-level layout unit, the step of splitting the graph to be split in the layout unit to obtain the splitting scheme of the layout unit includes:

[0027] Obtain the splitting relationship between the edge graphs in each low-level layout unit; the splitting relationship is configured to at least determine whether any two edge graphs in the low-level layout unit are on the same splitting diagram;

[0028] Generate a conflict graph based on the edge graphs extracted from the low-level layout unit, the positions of the edge graphs on the design layout, and the splitting relationship;

[0029] Solve the conflict graph to obtain the splitting scheme of the layout unit.

[0030] Optionally, the step of splitting the graph to be split in the layout unit to obtain the splitting scheme of the layout unit includes:

[0031] Generate a conflict graph based on the graph to be split and the position of the graph to be split on the design layout;

[0032] Solve the conflict graph to obtain the splitting scheme of the layout unit.

[0033] Optionally, the design layout splitting method further includes:

[0034] Performing graphic splitting on the design layout according to the overall splitting scheme to obtain a preset number of graphic sets corresponding to the overall splitting scheme; the graphics in each graphic set are on the same split graph;

[0035] Screening the overall splitting scheme according to the total graphic area of the graphic set to determine the target overall splitting scheme for splitting all the graphics on the design layout.

[0036] According to another aspect of the present invention, there is also provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above design layout splitting methods are implemented.

[0037] According to still another aspect of the present invention, there is also provided a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of any one of the above design layout splitting methods are implemented.

[0038] According to yet another aspect of the present invention, there is also provided a computer device, which includes a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of any one of the above design layout splitting methods.

[0039] In the design layout splitting method of the present invention, since multi-level layout units of the design layout can be obtained, there is no need to perform a planarization process on the design layout and then perform window division, that is, part of the computing resources and time-consuming for the planarization process are avoided, reducing the amount of computing resources used and the time-consuming. Moreover, each basic layout unit includes a complete circuit block, which also prevents the problem that large graphics span multiple windows, and further prevents splitting failure caused by some complete graphics being colored differently, improving the splitting success rate. When targeting non-lowest-level layout units, since non-lowest-level layout units include multiple lower-level layout units, the mutual influence between two lower-level layout units is considered during pattern splitting, which can prevent the coloring influence between graphics at the window boundary and prevent the appearance of poor splitting results. Therefore, the design layout splitting method of the present invention not only has great advantages in terms of computing resources and time-consuming, but also has no fatal defects in terms of splitting results, and the splitting results are excellent.

[0040] Furthermore, in the design layout splitting method of the present invention, when targeting non-lowest-level layout units, the graphics to be split of the non-lowest-level layout units are the edge graphics of the lower-level layout units, rather than all the graphics in the non-lowest-level layout units. Obviously, the number of graphics used is reduced, and the computing resources and running time used for automatic splitting of large-scale integrated circuit layout design can be less.

[0041] Furthermore, in the design layout splitting method of the present invention, the splitting scheme can be further screened using the graphic density of the split diagram. The balance of the graphic density after splitting is usually an index for evaluating the splitting result, which can make the mask (i.e., the split diagram) obtained by splitting have the same total graphic area as much as possible, facilitating the balance of the graphic density and further facilitating subsequent processing such as exposure of the split diagram.

[0042] From the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more clearly aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Some specific embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings in an exemplary but not restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0044] Figure 1 is a schematic tree diagram of a design layout according to an embodiment of the present invention;

[0045] Figure 2 is a schematic flow chart of a design layout splitting method according to an embodiment of the present invention;

[0046] Figure 3 is a hierarchical structure diagram between high-level layout units and low-level layout units in a design layout according to an embodiment of the present invention;

[0047] Figure 4 is a hierarchical structure diagram between high-level layout units and low-level layout units in a design layout according to an embodiment of the present invention;

[0048] Figure 5 is a partial schematic flow chart of a design layout splitting method according to an embodiment of the present invention;

[0049] Figure 6 is a partial schematic flow chart of a design layout splitting method according to an embodiment of the present invention;

[0050] Figure 7 is a schematic flow chart of a design layout splitting method according to an embodiment of the present invention;

[0051] Figure 8 is a schematic diagram of a basic layout unit according to an embodiment of the present invention;

[0052] Figure 9 is a schematic diagram of a conflict graph of a basic layout unit according to an embodiment of the present invention;

[0053] Figure 10 Schematic diagram of a boundary conflict graph of a low-level layout unit according to an embodiment of the present invention;

[0054] Figure 11 Schematic diagram of a conflict graph of a composite layout unit according to an embodiment of the present invention;

[0055] Figure 12 Schematic diagram of the splitting result of a splitting scheme of a basic layout unit according to an embodiment of the present invention;

[0056] Figure 13 Schematic diagram of a conflict graph of a basic layout unit according to an embodiment of the present invention;

[0057] Figure 14 Partial process schematic diagram of a design layout splitting method according to an embodiment of the present invention;

[0058] Figure 15 Partial process schematic diagram of a design layout splitting method according to an embodiment of the present invention;

[0059] Figure 16 Partial process schematic diagram of a design layout splitting method according to an embodiment of the present invention;

[0060] Figure 17 Schematic diagram of a basic layout unit according to an embodiment of the present invention;

[0061] Figure 18 Process schematic diagram of a design layout splitting method according to an embodiment of the present invention;

[0062] Figure 19 Schematic diagram of the splitting result of an overall splitting scheme of a design layout according to an embodiment of the present invention;

[0063] Figure 20 Another process schematic diagram of a design layout splitting method according to an embodiment of the present invention;

[0064] Figure 21 Schematic diagram of a computer program product according to an embodiment of the present invention;

[0065] Figure 22 Schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0066] Figure 23 Schematic diagram of a computer device according to an embodiment of the present invention. Detailed implementation mode

[0067] The embodiment of the present invention provides a solution for a design layout splitting method.

[0068] Figure 1 is a schematic tree diagram of a design layout according to an embodiment of the present invention. As Figure 1 shown, for the layout design of an integrated circuit, the integrated circuit includes a combination of various circuit blocks, and each circuit block is also a combination of other circuit blocks. Therefore, the integrated circuit includes various circuit blocks arranged in a hierarchical manner, that is, various circuit blocks at each level. That is to say, the design layout to be split has layout units at multiple levels. The layout unit at the lowest level is the basic layout unit, and the basic layout unit may include a circuit block; the layout unit at a higher level includes at least two layout units at a lower level.

[0069] Figure 2 is a schematic flowchart of a method for splitting a design layout according to an embodiment of the present invention. As Figure 2 shown, the method for splitting the design layout generally may include:

[0070] Step S100, obtaining the layout units of the design layout. In this embodiment, the respective layout units of the design layout are directly identified and obtained without performing planarization processing on the design layout.

[0071] Step S200, obtaining the graphics to be split of the layout unit from all the graphics of the layout unit; the number of the graphics to be split of the layout unit is less than or equal to the number of all the graphics of the layout unit. After obtaining each layout unit, the graphics to be split of each layout unit can be obtained through the corresponding obtaining rules. Moreover, when targeting a layout unit at a non-lowest level, the graphics to be split of the layout unit at a non-lowest level are not all the graphics in the layout unit at a non-lowest level, obviously reducing the number of graphics used.

[0072] Step S300, splitting the graphics to be split of the layout unit to obtain a splitting scheme of the layout unit. An iterative method can be used to first split the layout units at a lower level, and then split the layout units at a higher level, or the graphics to be split of each layout unit can be split simultaneously.

[0073] Step S400, obtaining an overall splitting scheme of the design layout according to the splitting schemes of all the layout units. Specifically, all the splitting schemes can be combined in one place to obtain multiple overall splitting schemes. Each overall splitting scheme must include the splitting schemes of all the layout units and only include one splitting scheme of each layout unit. One splitting scheme of each layout unit can be used for at least one overall splitting scheme.

[0074] In the design layout splitting method according to the embodiments of the present invention, since multi-level layout units of the design layout can be obtained, there is no need to perform a planarization process on the design layout and then perform window division, that is, some computing resources and time-consuming for the planarization process are avoided, reducing the usage of computing resources and time-consuming. Moreover, each basic layout unit includes a complete circuit block, which also prevents the problem that large graphics span multiple windows, thereby preventing splitting failure caused by some complete graphics being colored differently, and improving the splitting success rate. When targeting non-lowest-level layout units, since non-lowest-level layout units include multiple lower-level layout units, the mutual influence between two lower-level layout units is considered during pattern splitting, which can prevent the coloring influence between graphics at the window boundary and prevent the occurrence of poor splitting results.

[0075] In some embodiments of the present invention, at least two lower-level layout units in each higher-level layout unit have the same level. Or, among at least two lower-level layout units in each higher-level layout unit, at least one lower-level layout unit has a different level from other lower-level layout units. Specifically, as Figure 1 shown, the layout design of the design layout can be used to fabricate a feature layer of an integrated circuit. In view of the hierarchical design of the integrated circuit, the design layout includes layout units 42, 43, 44, 46, 47, 48, 52, 54, 56, 58, 62, 64, 66, 72, and 80 corresponding to various levels and types of circuit blocks arranged in a hierarchical manner. Among them, layout units 42, 43, 44, 46, 47, 48 are at the same level and are basic layout units. Layout units 52, 54, 56, 58 are at another same level. Layout units 62, 64, 66 are at yet another same level. Layout unit 72 is at still another level. Layout unit 80 is at another level and can also be the highest-level layout unit 80. The highest-level layout unit 80 is used to represent the entire layout design, which is composed of a lower-level layout unit 72 and two even lower-level layout units 66 (layout units 661 and 662 respectively), as Figure 3 shown. If further expanded, a more detailed hierarchical structure can be obtained, as Figure 4As shown. Generally speaking, the layout design of the design layout is stored in a non-volatile storage device in a database file format such as GDSII, OASIS or other suitable formats. For the step of obtaining the layout units of the design layout, it is to receive from the storage device the layout design for manufacturing the feature layer of the integrated circuit, the information about the layout units it contains, and the hierarchical arrangement information of these layout units.

[0076] In some embodiments of the present invention, the above step S200, the step of obtaining the to-be-split graphics of the layout unit from all the graphics of the layout unit, includes:

[0077] When the layout unit is a basic layout unit, the graphics possessed by the layout unit are used as the to-be-split graphics of the layout unit.

[0078] When the layout unit has low-level layout units, first extract the edge graphics from the to-be-split graphics of each low-level layout unit in the layout unit, and then use the edge graphics extracted from each low-level layout unit in the layout unit as the to-be-split graphics of the layout unit.

[0079] In the embodiments of the present invention, it is necessary to extract the edge graphics from the to-be-split graphics of each low-level layout unit, and these edge graphics are used as the to-be-split graphics of the high-level layout unit, rather than all the graphics in the high-level layout unit. When splitting the high-level layout unit, obviously the number of used graphics is reduced, and it can make the computing resources and running time used for the automatic splitting of the large-scale integrated circuit layout design less. For the basic layout unit, since it has no low-level layout units, the graphics possessed by the basic layout unit are used as the to-be-split graphics of the basic layout unit.

[0080] It should be noted in the embodiments of the present invention that, in order to improve the acquisition efficiency of the to-be-split graphics, after extracting the edge graphics from the to-be-split graphics of the low-level layout unit, the edge graphics can be immediately extracted from the to-be-split graphics of the layout unit. For example, when the layout unit is a basic layout unit, the graphics possessed by the layout unit are used as the to-be-split graphics of the layout unit, and then the edge graphics are immediately extracted from the to-be-split graphics of the layout unit. When it is determined that the layout unit has low-level layout units, the edge graphics extracted from each low-level layout unit in the layout unit can be directly used as the to-be-split graphics of the layout unit. In some other embodiments of the present invention, since the highest-level layout unit cannot be used as the low-level layout unit of other layout units, in order to simplify the program, after extracting the edge graphics from the to-be-split graphics of each layout unit, the edge graphics can be immediately extracted from the to-be-split graphics of the layout unit for the high-level layout unit with low-level layout units. In this way, when extracting the edge graphics, it is not necessary to judge the level of the layout unit.

[0081] In some embodiments of the present invention, as Figure 5 shown, the above-mentioned step S200, the step of obtaining the to-be-split graphics of the layout unit from all the graphics of the layout unit, may specifically include:

[0082] Step S210, determining whether the layout unit is a basic layout unit.

[0083] If so, go to step S220, take the graphics possessed by the layout unit as the to-be-split graphics of the layout unit; and extract the edge graphics from the to-be-split graphics of this layout unit. That is, when the layout unit is a basic layout unit, take the graphics possessed by the layout unit as the to-be-split graphics of the layout unit.

[0084] If not, go to step S230, take the edge graphics extracted from each low-level layout unit in the layout unit as the to-be-split graphics of the layout unit. That is, when the layout unit has low-level layout units, take the edge graphics extracted from each low-level layout unit in the layout unit as the to-be-split graphics of the layout unit. At the same time, extract the edge graphics from the to-be-split graphics of this layout unit, or, when this layout unit is a low-level layout unit of one or more other layout units, extract the edge graphics from the to-be-split graphics of this layout unit.

[0085] That is to say, after obtaining the to-be-split graphics of each low-level layout unit, it prepares for the obtaining of the to-be-split graphics of the high-level layout unit at the same time, rather than calling the to-be-split graphics of the low-level layout unit again after identifying the high-level layout unit, which significantly improves the splitting efficiency.

[0086] Moreover, in step S230, when it is determined that the layout unit is not a basic layout unit, the level of the layout unit can be obtained at the same time, and processed level by level in ascending order according to the level of the layout unit. That is to say, based on this method, the layout unit can be processed level by level in an iterative manner based on the hierarchy, with strong orderliness and higher efficiency. That is, the design layout splitting method can repeatedly execute the coloring process for each layout unit in the layout based on the hierarchical structure of the large-scale integrated circuit layout design, so as to realize the automatic splitting of the layout.

[0087] Furthermore, when the design layout splitting method is aimed at non-lowest-level layout units, the to-be-split graphics of the non-lowest-level layout units are the edge graphics of the low-level layout units, rather than all the graphics in the non-lowest-level layout units. Obviously, the number of used graphics is reduced, and the computing resources and running time used for the automatic splitting of the large-scale integrated circuit layout design can be less.

[0088] In some embodiments of the present invention, as Figure 6 shown, in step S230 above, the edge graphics extracted from each low-level layout unit in the layout unit are used as the graphics to be split of the layout unit; and when the layout unit is a low-level layout unit of one or more other layout units, the step of extracting edge graphics from the graphics to be split of the layout unit includes:

[0089] Step S231, determine whether the layout unit is a low-level layout unit of one or more other layout units.

[0090] If so, go to step S232, use the edge graphics extracted from each low-level layout unit in the layout unit as the graphics to be split of the layout unit; and extract edge graphics from the graphics to be split of the layout unit.

[0091] If not, go to step S233, use the edge graphics extracted from each low-level layout unit in the layout unit as the graphics to be split of the layout unit.

[0092] In some embodiments of the present invention, as Figure 7 shown, in step S300 above, the step of splitting the graphics to be split of the layout unit to obtain the splitting scheme of the layout unit includes:

[0093] Step S310, generate a conflict graph based on the graphics to be split and the position of the graphics to be split on the design layout;

[0094] Step S320, solve the conflict graph to obtain the splitting scheme of the layout unit.

[0095] That is to say, in order to color the layout design for manufacturing a layer feature of an integrated circuit, it is necessary to repeatedly execute the coloring process for a single layout unit in an iterative manner. In this process, the lower-level layout units in the hierarchical structure will be analyzed first, and then the boundary graphic information (i.e., edge graphics) of the lower-level layout units will be provided to the higher-level layout units in the hierarchical structure. Therefore, the step of splitting the graphics to be split of the layout unit needs to identify which level the current layout unit belongs to: if it is identified as a basic layout unit, that is, the lowest-level layout unit, only the conflict graph of this layout unit needs to be prepared at this time; if it is identified as a composite layout unit, which can also be called a high-level layout unit, that is, a layout unit constructed by basic layout units or other composite layout units lower than the current level, the preparation of the conflict graph of this layout unit depends on the boundary graphic information of its component layout units, such as edge graphics, and the position of the edge graphics on the design layout.

[0096] In some embodiments of the present invention, the step of generating a conflict graph based on the graph to be split and the position of the graph to be split on the design layout may include: obtaining the distance between two graphs to be split, determining whether there is a conflict between the two graphs to be split according to the distance between the two graphs to be split, and identifying whether the graphs to be split conflict according to the conflict result.

[0097] Figure 8 Shows the composition of a basic layout unit, and the basic layout unit includes a border 86 and graphs 81, 82, 83, 84, 85. To ensure the manufacturability of the unit, a minimum distance D0 is usually set to indicate that graphs greater than this value do not need to be assigned to different masks for manufacturing, that is, the same color on the corresponding two graphs, that is, do not need to be split into different split graphs. Of course, during specific splitting, it is also allowed to be split into two different split graphs. The minimum distance D0 is also used to indicate that graphs less than this value need to be assigned to different masks for manufacturing. Of course, during specific splitting, graphs less than this value are preferentially assigned to different masks for manufacturing, and can also be assigned to the same mask according to requirements, or calculation rules, etc. For example, a graph that conflicts with a non-colorable graph may be assigned to the same grinding graph for manufacturing.

[0098] Figure 8 The minimum distances between the graphs are also shown, such as the distance between graph 81 and graph 83 is D7, the distance between graph 81 and graph 82 is D1, etc. Assuming that D7 is greater than D0 and D1 - D6 are less than D0, then the layout unit can be converted into a conflict graph as shown in Figure 9 shown. Among them, D1 - D6 will become the corresponding conflict edges C1 - C6, that is, it identifies whether the graphs to be split conflict. After that, the graph allocation process of the layout unit is converted into a coloring problem of the conflict graph.

[0099] In some embodiments of the present invention, solving the conflict graph to obtain the splitting scheme of the layout unit is mainly to perform a coloring analysis on the conflict graph through a suitable algorithm. For example, a truth table can be established to enumerate possible vertex coloring combinations. Figure 9Vertices 91, 92, 93, 94, and 95 in it respectively correspond to graphics 81, 82, 83, 84, and 85, and one or more solutions can be obtained in the enumerated combinations (i.e., no adjacent vertices have the same color). Generally speaking, in this step, two or more candidate layout units are selected simultaneously for analysis, that is, two or more of them are selected to perform the corresponding analysis in a parallel processing manner. Parallel processing usually means that one or more processors execute multiple analyses through multitasking or multithreading. For the order of analysis, sometimes it is randomly selected, and sometimes it is selected according to one or more factors, including the frequency of selection of the layout unit by other higher-level layout units, the size of the layout unit, the number of conflict edges in the conflict graph, or the number of its adjacent units, etc.

[0100] When the layout unit is not a basic layout unit, generating a conflict graph based on the graph to be split and the position of the graph to be split on the design layout may include: generating a boundary conflict graph of the low-level layout unit based on the edge graph extracted from each low-level layout unit and the position of the edge graph on the design layout, as Figure 10 shown. Merge the boundary conflict graphs of multiple low-level layout units to obtain the conflict graph to be split, that is, obtain the conflict graph of the current unit, such as the conflict graph shown in 11. That is to say, merge the boundary conflict graphs 40 of the low-level layout units into the conflict graph 70 of the current composite layout unit.

[0101] In some embodiments of the present invention, when solving the conflict graph, it is also necessary to identify and remove non-colorable graphs. The graphs on the conflict graph can also be referred to as the structure of the conflict graph. That is, the steps of solving the conflict graph described above include: identifying and removing non-colorable graphs, and solving the remaining graphs in the conflict graph.

[0102] Specifically, when analyzing the current layout unit, no matter what N is, there may be non-colorable structures. For example, when N equals 2, for the Figure 9 conflict graph shown, there will be non-colorable graphs, such as vertices 92, 94, 95 and their conflict edges, which are usually called "odd cycles". For the Figure 9 vertices 92, 94, 95 in it, they are set to need different colors pairwise. Therefore, if vertices 92 and 94 are colored with two different colors, no matter which of the two colors vertex 95 is colored with, it will conflict with the aforementioned "need to be colored with different colors". In some examples, the number of vertices in this odd cycle can also be 5, 7, or any odd number greater than 7. In order to reduce all possible coloring results saved when solving the conflict graph to obtain the splitting scheme of the layout unit, usually such non-colorable structures can be removed.

[0103] In some embodiments of the present invention, after solving the remaining graphs in the conflict graph, the non-colorable structures can be colored based on some splitting rules.

[0104] In some other embodiments of the present invention, when solving the conflict graph, it is also necessary to identify non-colorable graphs and remove some non-colorable graphs. The graphs on the conflict graph can also be referred to as the structures of the conflict graph. That is, the steps of solving the conflict graph described above include: identifying non-colorable graphs, removing some non-colorable graphs, and solving the remaining graphs in the conflict graph. After solving the remaining graphs in the conflict graph, the removed structures can be colored based on some splitting rules to generate the final splitting scheme. For example, obtaining the coloring result of the conflict structure closest to the removed structure and coloring the removed structure with a color different from that of the conflict structure closest to it. Or, coloring the removed structure with the same color as the conflict structure farthest from it. As Figure 12 shown, it shows a schematic diagram of the splitting result of a splitting scheme of a basic layout unit.

[0105] In some preferred embodiments of the present invention, it is also possible to directly solve all the graphs on the conflict graph based on some other algorithms without identifying and removing non-colorable structures. For example, considering the distance factor between two conflicting graphs during the coloring process, etc.

[0106] In some embodiments of the present invention, for the same conflict graph, because only the coloring of adjacent vertices is restricted, there may be multiple different coloring solution sets for the same conflict graph. Figure 13 The conflict graph 400 shown in Figure 9 is similar to the conflict graph shown in. Among them, since vertex 91 has no association with any vertex in the graph, when N = 2, this vertex will have two solutions; for vertices 93, 94, and 95, because vertex 94 has conflict edges with both vertex 93 and vertex 95 (here, the different-color link 96 is used to indicate that vertex 94 and vertex 93 and vertex 94 and vertex 95 must be colored with different colors), so when N = 2, the set composed of vertices 93, 94, and 95 will have two sets of solutions. Finally, for the Figure 12 conflict graph in, there will be a total of 4 different coloring solutions. After obtaining all the solution sets of the conflict graph, the coloring problem of conflict graphs at different levels is equivalent to the problem of merging and then screening various solution sets at different levels.

[0107] In some embodiments of the present invention, as Figure 14 shown, when the layout unit has a low-level layout unit, that is, when the layout unit is not a basic layout unit, the above step S300 of splitting the graph to be split of the layout unit to obtain the splitting scheme of the layout unit includes:

[0108] S330, obtain the splitting relationships between the edge graphics in each low-level layout unit; the splitting relationships are configured to at least determine whether any two edge graphics in the low-level layout unit are on the same splitting diagram;

[0109] S340, generate a conflict graph based on the edge graphics extracted from the low-level layout unit, the positions of the edge graphics on the design layout, and the splitting relationships;

[0110] S320, solve the conflict graph to obtain the splitting scheme of the layout unit.

[0111] In some cases, Figure 10 certain details within the low-level layout unit are ignored when forming the boundary conflict graph of the layout unit. For example, taking the boundary conflict graph of the low-level layout unit shown in Figure 10 as an example, when N = 2, both vertex 91 and 95 can be either of the two colors, so there are 4 sets of solutions. However, considering the graphic 82 in the low-level layout unit, since both vertex 91 and vertex 95 conflict with vertex 92, when N = 2, vertex 91 and vertex 95 must be colored with the same color. Then, there are only 2 sets of solution sets for the boundary conflict graph of the low-level layout unit that the high-level layout unit needs to refer to. As shown in Figure 14 , the vertices 91 and 95 of the boundary conflict graph can be connected by a same-color link 97 to indicate that vertex 91 and 95 can only be colored with the same color.

[0112] That is to say, when the layout unit is not a basic layout unit, generating a conflict graph based on the graphics to be split and the positions of the graphics to be split on the design layout may include: generating a boundary conflict graph 40 of the low-level layout unit based on the edge graphics extracted from each low-level layout unit, the positions of the edge graphics on the design layout, and the splitting relationships between the edge graphics, as shown in Figure 10 . Merge the boundary conflict graphs of multiple low-level layout units to obtain the conflict graph to be split, that is, obtain the conflict graph of the current unit, such as the conflict graph shown in 11. That is to say, merge the boundary conflict graphs 40 of the low-level layout units into the conflict graph 70 of the current composite layout unit.

[0113] For a layout unit, such as a basic layout unit, like layout unit 42, layout unit 43, layout unit 44, layout unit 46, layout unit 47, layout unit 48, or a high-level layout unit, like layout unit 52, layout unit 54, layout unit 56, layout unit 58, layout unit 62, layout unit 64, layout unit 66, layout unit 72, a corresponding boundary conflict graph of the layout unit is derived and provided to another layout unit at a higher level in some cases. Thus, the information processed by the higher level is correspondingly reduced. That is, as Figure 15 shown, in some embodiments of the present invention, the above step of extracting the edge graph from the graph to be split of the layout unit includes:

[0114] Step S240, obtaining the layout unit boundary region 88 of the layout unit;

[0115] Step S250, determining whether each graph to be split has a part in the layout unit boundary region 88;

[0116] If so, enter step S260 to determine that the graph to be split is an edge graph.

[0117] In some embodiments of the present invention, as Figure 16 shown, the above step S240, the step of obtaining the layout unit boundary region 88 of the layout unit includes:

[0118] Step S241, obtaining the unit boundary of the layout unit, and the graph to be split of the layout unit is inside the unit boundary; the unit boundary of the layout unit can also be said to be the border 86 of the layout unit.

[0119] Step S242, generating an edge graph boundary 87 at a preset distance inside the unit boundary, and taking the region between the edge graph boundary 87 and the unit boundary as the layout unit boundary region 88.

[0120] For example, in Figure 17 , the layout unit boundary region 88 is a region formed by moving the unit boundary of the layout unit inward by a predetermined distance W. Among them, the predetermined distance W is greater than or equal to D0 plus the possible layout unit overlap amount. Then, if a graph is inside the inner boundary of this region, that is, inside the edge graph boundary 87, it is impossible for it to have a conflict edge with the graph in other adjacent layout units. As described above, the vertices inside the inner boundary, such as the vertices 92, 93, 94 representing the graphs 82, 83, 84, will not form additional conflict edges with the vertices of the graphs representing adjacent layout units. In addition, as Figure 17As shown, the vertices of the graphics that at least partially fall within the layout unit boundary area 88, such as graphics 81 or 85, and their corresponding vertices 91 or 95 will appear in the boundary conflict graph of the layout unit, such as Figure 10 shown.

[0121] In some embodiments of the present invention, in the above-mentioned step S400, the overall splitting scheme of the design layout is obtained according to the splitting scheme of all layout units. Before: when all the layout units of a certain level are executed, if there are layout units higher than the current level, it is necessary to check the higher-level units that reference the layout units currently analyzed again; if there are no higher-level layout units, it will proceed to step S400. In some cases, when a part of the layout units is executed, the higher-level layout units corresponding to the layout unit can be checked immediately without waiting for all the layout units of the level to be analyzed. Finally, through iterative execution, all layout units of the design layout will be processed.

[0122] In the above-mentioned step S400, an overall splitting scheme of the design layout is obtained according to the splitting schemes of all layout units. Specifically, a merging operation is performed to merge all possible coloring results of the composite layout unit with all possible coloring results of the basic layout unit. The merging operation is iteratively performed starting from the highest-level composite layout unit until all possible coloring results of all layout units are merged.

[0123] In some embodiments of the present invention, Figure 18 As shown, the design layout splitting method also includes:

[0124] Step S500, splitting the graphics of the design layout according to the overall splitting scheme to obtain a preset number of graphic sets corresponding to the overall splitting scheme; the graphics in each graphic set are on the same splitting graph;

[0125] Step S600 , screening the overall splitting schemes according to the total area of the graphics in the graphic set to determine a target overall splitting scheme for splitting all the graphics on the design layout.

[0126] In the process of design layout splitting, in addition to obtaining the correct splitting result, it is also hoped that each split diagram obtained by splitting, that is, each mask, has the same total graphic area. Therefore, after merging all levels of possible solution sets, a better splitting result can be obtained based on the ratio of the total graphic areas corresponding to the N colors in each possible path. That is to say, in the design layout splitting method of the present invention, the graphic density of the split diagram can be used to further screen the splitting scheme. The balance of the graphic density after splitting is usually an indicator for evaluating the splitting result, which can try to make the mask (i.e., split diagram) obtained by splitting have the same total graphic area, such as Figure 19As shown, it is conducive to achieving the balance of graphic density, and further conducive to subsequent processing such as exposure of the split diagrams.

[0127] In some embodiments of the present invention, as Figure 20 shown, the layout splitting method may specifically include:

[0128] Step S101, read the design layout.

[0129] Step S102, obtain the layout units of the design layout. In this embodiment, directly identify and obtain each layout unit of the design layout without performing planarization processing on the design layout.

[0130] Step S103, obtain the layout units at the same level, and obtain the graphics to be split of the layout unit from all the graphics of one or more of the layout units.

[0131] Step S104, generate a conflict graph at least based on the graphics to be split and the positions of the graphics to be split on the design layout; solve the conflict graph to obtain the splitting scheme of the layout unit.

[0132] Step S105, extract the edge graphics from the graphics to be split of the layout unit.

[0133] Step S106, determine whether there are other layout units at the same level as the current layout unit.

[0134] If so, return to step S103 to loop and execute steps S103 to S106 until all the layout units at the same level are executed, and obtain the splitting scheme of each layout unit at the same level; if not, enter step S107.

[0135] Step S107, determine whether there are other layout units at a level higher than the level of the current layout unit.

[0136] If so, return to step S102 to obtain other layout units at a level higher than the level of the current layout unit; if not, enter step S108.

[0137] Step S108, obtain the overall splitting scheme of the design layout according to the splitting schemes of all the layout units. Specifically, it can be to perform a merging operation to merge all possible coloring results of the composite layout units with all possible coloring results of the basic layout units. The merging operation is iteratively executed starting from the composite layout units at the highest level until all possible coloring results of all the layout units are merged.

[0138] Step S109, split the graphics of the design layout according to the overall splitting scheme to obtain a preset number of graphic sets corresponding to the overall splitting scheme;

[0139] Step S110, screen the overall splitting scheme according to the total graphic area of the graphic set to determine the target overall splitting scheme for splitting all the graphics on the design layout.

[0140] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any specific order, or that all the operations of the method are included in every case. In addition, the method may include additional operations. Within the scope of the technical concept provided by the method in this embodiment, additional changes can be made to the above method.

[0141] It should be understood that in some embodiments, each part can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0142] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 21 is a schematic diagram of a computer program product 10 according to an embodiment of the present invention, Figure 22 is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention, Figure 23 is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, and when the computer program 11 is executed by a processor 32, the steps of any of the above design layout splitting methods are implemented. The computer-readable storage medium 20 stores the above computer program 11, and when the computer program 11 is executed by the processor 32, the steps of the design layout splitting method of any of the above embodiments are implemented. The computer device 30 may include a memory 31, a processor 32, and a computer program 11 stored on the memory 31 and running on the processor 32.

[0143] The computer program 11 for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, status setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer program 11 may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer. In some embodiments, to perform aspects of the present invention, an electronic circuit, including, for example, a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer - readable program instructions by using the status information of the computer - readable program instructions to personalize the electronic circuit.

[0144] For the description of this embodiment, the computer program product 10 is a related product containing the computer program 11.

[0145] For the description of this embodiment, the computer - readable storage medium 20 is a tangible device capable of retaining and storing the computer program 11, which can be any device that can contain, store, communicate, propagate, or transport the computer program 11 for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (a non - exhaustive list) of the computer - readable storage medium 20 include the following: portable computer disks, hard disks, random access memory (RAM), read - only memory (ROM), erasable programmable read - only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read - only memory (CD - ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device, and any suitable combination of the above.

[0146] The computer device 30 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smart phone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0147] The computer device 30 can include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of the instructions during operation. The processor 32 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 can include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0148] The computer device 30 can also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data to be input and output with external devices that can be connected to the computer device. The network adapter / interface can provide communication between the computer device and a network, which is generally shown as a communication network.

[0149] Up to this point, those skilled in the art should recognize that although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived from the content disclosed in the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and recognized as covering all these other variations or modifications.

Claims

1. A design layout splitting method, characterized in that, The design layout has multi-level layout units. The layout unit at the lowest level is a basic layout unit with one circuit block, and the layout units at higher levels include at least two layout units at lower levels; The method for splitting the design layout includes: Obtaining the layout units of the design layout; Obtaining the graphics to be split of the layout unit from all the graphics of the layout unit; the number of the graphics to be split of the layout unit is less than or equal to the number of all the graphics of the layout unit; Splitting the graphics to be split of the layout unit to obtain a splitting scheme of the layout unit; Obtaining an overall splitting scheme of the design layout according to the splitting schemes of all the layout units; the overall splitting scheme includes the splitting schemes of all the layout units and only includes one splitting scheme of each layout unit.

2. The method for splitting the design layout according to claim 1, wherein at least two of the lower-level layout units in each higher-level layout unit have the same level; or, among at least two of the lower-level layout units in each higher-level layout unit, at least one of the lower-level layout units has a different level from the other lower-level layout units.

3. The method for splitting the design layout according to claim 1, wherein the step of obtaining the graphics to be split of the layout unit from all the graphics of the layout unit includes: when the layout unit is a basic layout unit, taking the graphics possessed by the layout unit as the graphics to be split of the layout unit; when the layout unit has lower-level layout units, first extracting edge graphics from the graphics to be split of each lower-level layout unit in the layout unit, and then taking the edge graphics extracted from each lower-level layout unit in the layout unit as the graphics to be split of the layout unit.

4. The method for splitting the design layout according to claim 3, wherein the step of extracting edge graphics from the graphics to be split of the layout unit includes: Obtaining the layout unit boundary region of the layout unit; Judging whether each graphics to be split has a part located in the layout unit boundary region; If so, determining that the graphics to be split is an edge graphic.

5. The method for splitting the design layout according to claim 4, wherein the step of obtaining the layout unit boundary region of the layout unit includes: Obtaining the unit boundary of the layout unit, and the graphics to be split of the layout unit are located inside the unit boundary; Generating an edge graphic boundary at a preset distance inside the unit boundary, and taking the region between the edge graphic boundary and the unit boundary as the layout unit boundary region.

6. The method for splitting the design layout according to claim 1, wherein when the layout unit has lower-level layout units, the step of splitting the graphics to be split of the layout unit to obtain a splitting scheme of the layout unit includes: Obtain the splitting relationship between the edge graphics in each of the low-level layout units; the splitting relationship is configured to at least determine whether any two edge graphics in the low-level layout unit are on the same splitting diagram; Generate a conflict graph based on the edge graphics extracted from the low-level layout unit, the positions of the edge graphics on the design layout, and the splitting relationship; Solve the conflict graph to obtain the splitting scheme of the layout unit.

7. The design layout splitting method according to claim 1, wherein The step of splitting the graphics to be split of the layout unit to obtain the splitting scheme of the layout unit includes: Generate a conflict graph based on the graphics to be split and the positions of the graphics to be split on the design layout; Solve the conflict graph to obtain the splitting scheme of the layout unit.

8. The design layout splitting method according to claim 1, wherein It further includes: Split the graphics of the design layout according to the overall splitting scheme to obtain a preset number of graphic sets corresponding to the overall splitting scheme; the graphics in each graphic set are on the same splitting diagram; Screen the overall splitting scheme according to the total graphic area of the graphic sets to determine the target overall splitting scheme for splitting all the graphics on the design layout.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the design layout splitting method according to any one of claims 1 to 8.

10. A computer device, characterized in that, It includes a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the design layout splitting method according to any one of claims 1 to 8.

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