Layout routing optimization method and device, computer equipment and storage medium

Abstract

The application provides a layout wiring optimization method and device, computer equipment and a storage medium, and belongs to the technical field of electronic design automation. The method comprises the following steps: receiving an architecture update instruction, wherein the architecture update instruction carries at least an optimization index of a target circuit region; obtaining a preset architecture model, wherein the architecture model stores a plurality of basic algorithms, a plurality of scheduling logics and packaging logics; filtering at least one scheduling logic according to the optimization index and the packaging logic; iteratively optimizing the basic algorithm called by each scheduling logic based on the optimization index, and judging whether to continue iteration according to the change value of the optimization index or the algorithm result; when it is judged to stop iteration, the optimized scheduling logic and the basic algorithm are packaged, and the layout wiring corresponding to the target circuit region is generated and output. Through the processing scheme, the adaptability to different circuits is greatly improved, the maintenance cost is reduced, and the ability to improve the circuit function design in the later period is enhanced.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) technology, and more specifically to a layout and routing optimization method, apparatus, computer equipment, and storage medium. Background Technology

[0002] After placement or routing, multiple circuit metrics need to be optimized based on the results of static timing analysis. These typically include fixing timing constraint violations and achieving convergence timing, reducing circuit power consumption and cell footprint, and reducing signal crosstalk and noise after routing. In this process, automated circuit design tools repeatedly call various algorithms to optimize each metric one by one to find the optimal solution for the circuit. When a single algorithm converges in optimizing a single metric, the tool switches to the next algorithm to continue optimizing the current metric, iterating in this way for multiple rounds until each algorithm can no longer further optimize the current metric.

[0003] The current tool design methodology has the following problems:

[0004] First, each algorithm applies to the entire layout, without breaking it down to a more microscopic level, such as the inability to optimize for the pins of a specific cell. From a macroscopic perspective, this approach can optimize placement and routing to the limit achievable by a single algorithm; from a microscopic perspective, repeatedly iterating through a single algorithm to optimize a particular metric of placement and routing can cause the metric to get stuck in a local optimum, preventing further convergence.

[0005] Second, the traversal logic and optimization objective of each algorithm within the layout are fixed, making adjustments costly. However, for each optimization stage of each metric, the algorithm's traversal logic and optimization objective within the layout should be different. For example, compared to optimizing all cells leniently at the beginning of the optimization stage and then optimizing cells with serious violations, directly optimizing all cells to convergence when far from convergence would significantly increase the number of iterations (running time) required due to the poor initial state of all cells.

[0006] Third, when optimizing circuit functions, it is impossible to combine multiple algorithms or adjust their order for automatic optimization. Currently, when fixing design defects or improving the function of a circuit, engineers need to manually adjust the cell positions or insert buffers. They cannot use tools to call a specified set of algorithms to optimize a specific part of the circuit, resulting in significant time and manpower costs. Summary of the Invention

[0007] Therefore, in order to overcome the shortcomings of the prior art, the present invention provides a layout and routing optimization method, apparatus, computer equipment and storage medium, which can flexibly adjust each basic algorithm, scheduling logic and encapsulation logic according to the requirements of the indicators, greatly improve the adaptability to different circuits, reduce maintenance costs and enhance the ability to improve the circuit function design in the later stage.

[0008] To achieve the above objectives, the present invention provides a placement and routing optimization method, comprising: receiving an architecture update instruction, the architecture update instruction carrying at least an optimization index for a target circuit region; acquiring a preset architecture model, the architecture model storing multiple basic algorithms, multiple scheduling logics, and encapsulation logic, wherein the basic algorithms are used to optimize a certain parameter index of a specific region, the scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit region, the encapsulation logics contain a mapping relationship between the optimization index and the scheduling logics, and the target circuit region is not smaller than the specific region; selecting at least one scheduling logic based on the optimization index and the encapsulation logics; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue iterating based on the change value of the optimization index or the algorithm result; when it is determined to stop iterating, encapsulating the optimized scheduling logic and the basic algorithm, generating and outputting the placement and routing corresponding to the target circuit region.

[0009] In one embodiment, the iterative optimization of the basic algorithm for each scheduling logic call based on the optimization index includes: determining the calling method of the basic algorithm in each scheduling logic; obtaining the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine the candidate pin, and using the candidate pin traversal method to traverse the candidate pin; and calling the basic algorithm to optimize the candidate pin based on the calling method to obtain the change value or algorithm result corresponding to the optimization index.

[0010] In one embodiment, the candidate pin acquisition method includes: screening all data paths in the target circuit region where the timing margin is less than the target timing margin as critical paths, and using the terminating pin of the critical path as a candidate pin; or, selecting bottleneck pins with timing margins less than the target timing margin as candidate pins in all data paths of the target circuit region; or, after layering the data paths of the target circuit region, selecting pins with timing margins less than the target timing margin in each layer as candidate pins.

[0011] In one embodiment, the candidate pin traversal method includes: dividing the data paths in the target circuit region into multiple complementary and interleaved regions, using the critical path corresponding to the terminating pin in its region as the optimization object, traversing from the starting pin of the critical path from top to bottom, and calling the basic algorithm to optimize the critical path; or, dividing the data paths in the target circuit region into multiple non-interleaved regions, traversing the bottleneck pins in each region and calling the basic algorithm to perform optimization; or, layering the data paths in the target circuit region, assigning the candidate pins of each layer to multiple non-interleaved regions, traversing each layer from the starting pin to the terminating pin or in reverse, and calling the basic algorithm to perform optimization.

[0012] In one embodiment, determining whether to continue iteration based on the change value of the optimization index or the algorithm result includes: after each iteration, multiplying the difference between the change value of the optimization index or the algorithm result after the previous optimization and the target value of the optimization index by a fixed coefficient to estimate the target of the current optimization; terminating the iteration when the difference between the change value of the optimization index or the algorithm result and the target value is greater than the estimated result or the number of iterations exceeds the upper limit; or, after each iteration, calculating the average difference of each optimization based on the change value of the optimization index or the algorithm result, terminating the iteration when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit.

[0013] In one embodiment, the optimization metric is at least one of optimizing total negative margin, optimizing worst-case negative margin, and optimizing power and area.

[0014] In one embodiment, the step of selecting at least one scheduling logic based on the optimization metric and the encapsulation logic includes: obtaining at least one scheduling logic; modifying at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0015] A layout and routing optimization device includes: an instruction receiving module for receiving an architecture update instruction, the instruction carrying at least an optimization index for a target circuit region; an acquisition module for acquiring a preset architecture model, the model storing multiple basic algorithms, multiple scheduling logics, and encapsulation logic, wherein the basic algorithms are used to optimize a parameter index of a specific region, the scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit region, and the encapsulation logics contain a mapping relationship between the optimization index and the scheduling logics, and the target circuit region is not smaller than the specific region; a filtering module for filtering at least one scheduling logic based on the optimization index and the encapsulation logics; an optimization module for iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue iteration based on the change value of the optimization index or the algorithm result; and an encapsulation module for encapsulating the optimized scheduling logic and the basic algorithm when it is determined to stop iteration, generating and outputting the layout and routing corresponding to the target circuit region.

[0016] A computer device includes a memory and a processor, the memory storing a computer program, characterized in that the processor executes the computer program to implement the steps of the above-described method.

[0017] A computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the above-described method.

[0018] Compared with existing technologies, the advantages of this invention are as follows: Scheduling logic is selected based on optimization metrics and encapsulation logic, resulting in targeted improvements in adaptability. It not only allows for iterative optimization and parameter control of the basic algorithms called by each scheduling logic based on optimization metrics, but also enables adjustments to the scheduling methods and algorithm organization logic within the architecture model. Starting from the structure of the architecture model, a new optimization algorithm is reconstructed, and this modular approach enhances the tool's adaptability. Maintenance costs are also reduced. For optimization metrics, only new encapsulation logic needs to be added, or the scheduling logic adjusted individually; other logic processing modules can still be reused. Therefore, the scope of adjustments during maintenance is smaller, resulting in lower maintenance costs. Furthermore, the ability to improve circuit functional design is enhanced. Even when circuit design needs to be changed or circuit defects need to be repaired, users do not need to manually adjust unit positions or insert new units. Instead, suitable scheduling logic and basic algorithms are encapsulated to form new encapsulation logic for the area requiring optimization, enabling automatic post-processing of the circuit. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the layout and routing optimization method in an embodiment of the present invention;

[0021] Figure 2 This is a flowchart of the architecture model in an embodiment of the present invention;

[0022] Figure 3 This is a flowchart illustrating the iterative optimization steps in an embodiment of the present invention;

[0023] Figure 4 This is a flowchart of a path-based scheduling method in an embodiment of the present invention;

[0024] Figure 5 This is a structural block diagram of a layout and routing optimization device in one embodiment;

[0025] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0026] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0027] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] It should be noted that the following description covers various aspects of embodiments within the scope of protection of this invention. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0029] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0030] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0031] like Figure 1 As shown, this application embodiment provides a layout and wiring optimization method. This method can be applied to a terminal or a server. The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable smart devices. The server 104 can be implemented using a standalone server or a server cluster composed of multiple servers. Taking the application of this method to a server as an example, the steps include:

[0032] Step 101: Receive architecture update instruction, which carries at least the optimization metrics for the target circuit region.

[0033] An architecture update command carries at least the optimization metrics for the target circuit area. The server receives the architecture update command. The architecture update command can be issued by a user terminal.

[0034] In one embodiment, the optimization metrics are at least one of total negative slack (TNS), worst-case negative slack, and power and area optimization. Total negative slack (TNS) is the sum of negative slack across all timing paths. Negative slack indicates that a signal cannot reach its destination within the specified time, resulting in a timing violation. Worst-case negative slack (WNS) is the worst negative slack across all timing paths, i.e., the path with the greatest delay. Power optimization: reducing the dynamic and static power consumption of the circuit. Area optimization: minimizing the area of ​​the chip or PCB while meeting performance requirements.

[0035] When the optimization metrics simultaneously include total negative margin, worst-case negative margin, and power and area optimization, such as Figure 2 As shown, the server can simultaneously optimize total negative margin, worst-case negative margin, and power and area without having to optimize them one by one, thus shortening the processing time. Furthermore, the architecture model is abstracted into three layers, each of which is implemented independently and is not dependent on each other, resulting in high reusability.

[0036] The target circuit region can include at least one of the pre-designed layout and routing relationships within a specific area, and it can also include pin arrangements within a specific area. Layout and routing are critical steps in electronic design automation (EDA), directly affecting circuit performance, power consumption, and area.

[0037] Step 102: Obtain a preset architecture model. The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logic. The basic algorithms are used to optimize a certain parameter index of a specific region. The scheduling logic is used to call at least one basic algorithm to optimize the parameter index of the target circuit region. The encapsulation logic contains the mapping relationship between the optimization index and the scheduling logic. The target circuit region is not smaller than the specific region.

[0038] The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logics, also divided into three levels: encapsulation logic, scheduling logic, and basic algorithms. Encapsulation logic can encapsulate multiple scheduling logics, and scheduling logic can call a single basic algorithm or a combination of multiple basic algorithms. When the target circuit area is not smaller than a specific area, encapsulation logic can encapsulate a combination of multiple scheduling logics. The architecture model can be used for advanced process sizes such as 7nm, as well as 14nm and above, supporting layout and routing optimization for circuits with up to millions of cells. The basic algorithms included in the architecture model are not limited, and include, but are not limited to, relocation cells, copy cells, insertion buffers, and resynthesis.

[0039] The basic algorithm is used to optimize a specific parameter in a particular region. It is the smallest unit of the architectural model, used to implement algorithms that optimize input pins from higher layers. From simple moving units or inserting buffers to complex resynthesizing of a region, everything can be packaged within a basic algorithm. Essentially, a basic algorithm is a microscopic single operator; its specific behavior only includes optimizing the region it covers and determining whether the change improves the circuit's performance. The method of acquiring pins and traversing the circuit are behaviors of the higher layer (scheduling logic), therefore, this layer can achieve different optimization effects through arbitrary combinations with higher layers.

[0040] The scheduling logic is used to invoke at least one basic algorithm to optimize the parameter indicators of the target circuit region. The server can select a suitable group or combination of algorithms as the basic algorithm based on the characteristics of the scheduling logic itself, and the scheduling logic will then invoke it. The scheduling logic is responsible for obtaining candidate pins from the circuit, traversing the candidate pins, and invoking a single algorithm or a group of algorithms for each pin. The scheduling logic is not associated with the basic algorithm and can be combined with any reasonable basic algorithm.

[0041] The encapsulation logic contains the mapping relationship between optimization metrics and scheduling logic, and the target circuit region is no smaller than a specific region. Guided by the metrics to be optimized, the encapsulation logic selects the scheduling method that is beneficial to the optimization metrics as the scheduling logic. The main function of the encapsulation logic is to declare the combination of scheduling logic and basic algorithm to the tool, encapsulate them into a whole, and then execute each combination of scheduling logic and basic algorithm in the encapsulation order.

[0042] Step 103: Select at least one scheduling logic based on optimization metrics and encapsulation logic.

[0043] The server selects at least one scheduling logic based on optimization metrics and encapsulation logic. The server can select at least one scheduling logic, then retrieve its parameter data stored in the architecture model and optimize it; alternatively, the server can select at least one scheduling logic and send it to the user terminal (which can be the terminal issuing the architecture update command or a third-party terminal), and the user terminal will provide feedback on the parameter settings and corresponding parameter data in the custom scheduling logic.

[0044] Step 104: Iteratively optimize the basic algorithm of each scheduling logic call based on the optimization index, and determine whether to continue iterating based on the change value of the optimization index or the algorithm result.

[0045] The server iteratively optimizes the basic algorithms invoked by each scheduling logic based on optimization metrics, and determines whether to continue iterating based on changes in the optimization metrics or algorithm results. In each iteration, the server first calls the candidate pin acquisition method to obtain the pins to be optimized, then it iterates through the candidate pins using the candidate pin traversal method bound to the scheduling logic, and calls the basic algorithm to optimize the candidate pins. After the traversal is complete, the server determines whether to proceed to the next round of scheduling logic iteration based on changes in the optimization metrics or the returned algorithm results.

[0046] Step 105: When it is determined that the iteration should stop, encapsulate the optimized scheduling logic and basic algorithm, and generate and output the layout and routing corresponding to the target circuit area.

[0047] When the iteration is stopped, the server encapsulates the optimized scheduling logic and basic algorithm, generates and outputs the layout and routing corresponding to the target circuit region. Finally, the server can restore the parameter data set in step 103, exit the scheduling and encapsulation logic, and enter the next encapsulation logic to continue optimization. Each type of scheduling logic is decoupled from the basic algorithm, therefore, the scheduling logic and basic algorithm can be maintained independently, or new scheduling logic and basic algorithms can be added, resulting in strong sustainability. Figure 2 As shown, when the server optimizes the total negative margin, each type of basic algorithm is only responsible for optimizing a single pin passed to the scheduling logic. The acquisition of candidate pins and the traversal of candidate pins are implemented by the scheduling logic. Therefore, different scheduling logics and basic algorithms can be combined and encapsulated into encapsulation logic to flexibly optimize different indicators.

[0048] The above method, by selecting scheduling logic based on optimization metrics and encapsulation logic, improves adaptability in a targeted manner. It not only iteratively optimizes the basic algorithms called by each scheduling logic based on optimization metrics and adds parameter control, but also adjusts the scheduling methods and algorithm organization logic in the architecture model. Starting from the structure of the architecture model, a new optimization algorithm is reconstructed. This modular approach enhances the tool's adaptability. Maintenance costs are also reduced. For optimization metrics, only new encapsulation logic needs to be added, or the scheduling logic adjusted individually; other logic processing modules can still be reused. Therefore, the scope of adjustments during maintenance is small, and maintenance costs are low. Furthermore, the ability to improve circuit functional design is enhanced. Even when circuit design needs to be changed or circuit defects need to be repaired, users do not need to manually adjust unit positions or insert new units. Instead, appropriate scheduling logic and basic algorithms are encapsulated to form new encapsulation logic for the area requiring optimization, automatically post-processing the circuit.

[0049] like Figure 3 As shown, in one embodiment, the basic algorithm for each scheduling logic call is iteratively optimized based on optimization metrics, including the following steps:

[0050] Step 301: Determine the calling method of the basic algorithm in each scheduling logic.

[0051] The server determines the invocation method of the basic algorithms in each scheduling logic. The invocation methods of multiple basic algorithms are divided into combined and sequential. In the combined method, multiple basic algorithms are treated as a group, and the optimization result is evaluated after each basic algorithm is executed. In the sequential method, they are executed in the order they are added. When an algorithm successfully optimizes the circuit, the next algorithm is not executed, but the optimization of the next pin is continued.

[0052] Step 302: Obtain the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic.

[0053] The server uses scheduling logic to obtain the corresponding candidate pin acquisition method and candidate pin traversal method. The main differences between different scheduling logics lie in the selection method of candidate pins, the traversal method when optimizing candidate pins, and the optimization iteration logic.

[0054] Step 303: Call the candidate pin acquisition method to determine the candidate pins, and use the candidate pin traversal method to traverse the candidate pins.

[0055] The server calls a candidate pin acquisition method to determine candidate pins and then uses a candidate pin traversal method to traverse the candidate pins. In one embodiment, the candidate pin acquisition method includes: i) using the terminal pin of the critical path as a candidate: filtering all data paths in the target circuit region where the timing margin is less than the target timing margin as critical paths, and using the terminal pin of the critical path as a candidate pin; or ii) using the bottleneck pin as a candidate: selecting bottleneck pins with timing margins less than the target timing margin on all data paths in the target circuit region as candidate pins; or iii) using pins of a single layer as candidates: dividing the data paths in the target circuit region into layers, and selecting pins with timing margins less than the target timing margin in each layer as candidate pins. Timing margin (Slack) refers to the difference between the actual signal arrival time and the theoretically required time in timing analysis.

[0056] Step 304: Based on the calling method, call the basic algorithm to optimize the candidate pins and obtain the change value or algorithm result corresponding to the optimization index.

[0057] The server uses a call-based approach to invoke a basic algorithm to optimize candidate pins, obtaining the corresponding changes in the optimized metrics or the algorithm results. The iterative logic of the server optimization refers to the conditions for determining whether to re-acquire candidate pins for the next iteration after optimization is complete.

[0058] In one embodiment, the server invokes a basic algorithm to optimize the candidate pins, including the following optimization methods:

[0059] i. Path-based optimization: This iterative logic uses the terminal pin of the critical path as a candidate, the critical path as the traversal object, and the convergence index as the target. It is suitable for optimizing indices such as worst-case negative margin.

[0060] ii. Optimization method based on bottleneck pin: The bottleneck pin is used as a candidate and the bottleneck pin is used as the traversal object. The iterative logic with the convergence index as the target is suitable for calling when the index is close to convergence.

[0061] iii. Pin-based optimization: This iterative logic uses single-layer pins as candidates, data path levels as traversal objects, and convergence metrics as the target. It is suitable for algorithms with strong dependencies on the hierarchical order, such as when replicating driver units to solve the fan-out problem, requiring traversal from the termination pin to the starting pin level. This optimization method can perform forward traversal from lower to higher levels, or reverse traversal.

[0062] iv. Optimization method based on hierarchical bottleneck pins: The iterative logic uses bottleneck pins as candidates, data path hierarchy as traversal objects, and estimation results as the target. It is suitable for calls when the indicators are poor, but the algorithm depends on the hierarchical order.

[0063] v. Optimization method based on estimation target bottleneck: The iterative logic uses the bottleneck pin as a candidate, the bottleneck pin as the traversal object, and the estimation result as the target. It is suitable for use when the current indicator is close to convergence but far away and a significant optimization of the indicator is required.

[0064] For example, in one embodiment, the server is based on path pairs Figure 4The circuit layout shown is optimized. Initially, path one is the worst critical path, followed by path two. When the server obtains candidate termination pins through scheduling logic, the D pin of flip-flop 6 is one of them (the other candidate termination pins are not shown in the diagram; this diagram only shows all paths corresponding to a single termination pin). After traversing to flip-flop 6, the server first obtains the worst critical path (path one) related to the D pin of flip-flop 6 through scheduling logic. Then, the server, through scheduling logic, will optimize the path from the top of the data path downwards, i.e., from flip-flop 1 to flip-flop 6, by calling the first basic algorithm in the basic algorithm combination. If all basic algorithms fail to optimize (no improvement to the target metric, or a significant decrease in other metrics), the server continues to optimize the path by calling the next basic algorithm in the basic algorithm combination through scheduling logic. When a basic algorithm successfully optimizes a unit on the path, the server will update the static timing through scheduling logic to obtain a new worst critical path, which may be path two or still path one, and then repeat the above steps to optimize the path. Until each of the basic algorithms in the combination fails to optimize any unit on the path, the server will continue to optimize the next termination pin among the candidate termination pins through scheduling logic. When optimization is complete, the server can store the scheduling logic and the optimized basic algorithm accordingly to obtain a new encapsulation logic.

[0065] In one embodiment, the candidate pin traversal method includes the following:

[0066] i. Using the critical path as the traversal object: The data paths in the target circuit area are divided into multiple complementary and interleaved regions. The critical path corresponding to the terminating pin in its respective region is used as the optimization object. Traversing from the starting pin of the critical path from top to bottom, the basic algorithm is called to optimize the critical path. When a signal indicating successful pin optimization is received, the critical path corresponding to the terminating pin is retrieved again and optimized in the same way. If the basic algorithm still does not return a signal indicating successful optimization after the entire path traversal is completed, the server determines that the critical path corresponding to the terminating pin has reached the optimization bottleneck.

[0067] ii. Using bottleneck pins as traversal objects: Divide the data paths in the target circuit area into multiple non-overlapping regions, traverse the bottleneck pins in each region, and call the basic algorithm to perform optimization.

[0068] iii. Use data path hierarchy as the traversal object: Divide the data path in the target circuit area into layers, assign the candidate pins of each layer to multiple non-overlapping areas, traverse each layer from the starting pin to the ending pin or in reverse, and call the basic algorithm to perform optimization.

[0069] In one embodiment, determining whether to continue iteration based on changes in the optimization metric or algorithm results includes the following methods:

[0070] i. Iterative logic with estimation results as the target: After each iteration, the difference between the change in the optimized metric or algorithm result after the previous optimization and the target metric is multiplied by a fixed coefficient to estimate the target for the current optimization. The iteration terminates when the difference between the change in the optimized metric or algorithm result and the target is greater than the estimated result or the number of iterations exceeds the upper limit. This method is suitable when the metric and the target are far apart, and it calls algorithms that can significantly optimize the metric, such as optimizing fan-out violations, to quickly bring the metric closer to the target.

[0071] ii. Iterative logic targeting convergence metrics: After each iteration, the average difference for each optimization is calculated based on the change in the optimization metric or the algorithm result. The iteration terminates when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit. This method is suitable for using small-amplitude optimization algorithms when converging towards the metric.

[0072] In one embodiment, selecting at least one scheduling logic based on optimization metrics and encapsulation logic includes: obtaining at least one scheduling logic; modifying at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0073] The server selects at least one scheduling logic, and then modifies at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate a new scheduling logic. Alternatively, the server can assemble all the obtained scheduling logic to generate a new scheduling logic.

[0074] In one embodiment, such as Figure 5 As shown, a layout and routing optimization device is provided, which includes an instruction receiving module 501, an acquisition module 502, a filtering module 503, an optimization module 504, and an encapsulation module 505.

[0075] The instruction receiving module 501 is used to receive architecture update instructions, which carry at least the optimization parameters of the target circuit region.

[0076] The acquisition module 502 is used to acquire a preset architecture model. The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logic. The basic algorithms are used to optimize a certain parameter index of a specific region. The scheduling logic is used to call at least one basic algorithm to optimize the parameter index of the target circuit region. The encapsulation logic contains the mapping relationship between the optimization index and the scheduling logic. The target circuit region is not smaller than the specific region.

[0077] The filtering module 503 is used to filter at least one scheduling logic based on optimization metrics and encapsulation logic.

[0078] The optimization module 504 is used to iteratively optimize the basic algorithm of each scheduling logic call based on the optimization index, and to determine whether to continue iterating based on the change value of the optimization index or the algorithm result.

[0079] The encapsulation module 505 is used to encapsulate the optimized scheduling logic and basic algorithm when it is determined that the iteration has stopped, and to generate and output the layout and routing corresponding to the target circuit area.

[0080] In one embodiment, the optimization module 504 includes:

[0081] The invocation method determination unit is used to determine the invocation method of the basic algorithm in each scheduling logic.

[0082] The method acquisition unit is used to acquire the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic.

[0083] The pin traversal unit is used to call the candidate pin acquisition method to determine the candidate pins, and then use the candidate pin traversal method to traverse the candidate pins.

[0084] The optimization unit is used to call the basic algorithm to optimize the candidate pins based on the calling method, and obtain the change value or algorithm result corresponding to the optimization index.

[0085] In one embodiment, the optimization module 504 includes:

[0086] The estimation unit is used after each iteration to multiply the difference between the change value of the optimization index or the algorithm result after the previous round of optimization and the target value of the optimization index by a fixed coefficient to estimate the target value of the current round of optimization. When the difference between the change value of the optimization index or the algorithm result and the target value is greater than the estimation result or the number of iterations exceeds the upper limit, the iteration is terminated.

[0087] Alternatively, the calculation unit is used to calculate the average difference of each optimization based on the change in the optimization index or the algorithm result after each iteration. When the average difference is less than a preset threshold or the number of iterations exceeds the upper limit, the iteration is terminated.

[0088] In one embodiment, the filtering module 503 includes:

[0089] The scheduling logic acquisition unit is used to acquire at least one scheduling logic.

[0090] The scheduling logic generation unit is used to modify at least one of the candidate pin acquisition method, candidate pin traversal method and optimized iteration method in the scheduling logic to generate new scheduling logic; or to assemble all the acquired scheduling logic to generate new scheduling logic.

[0091] Specific limitations regarding the layout and routing optimization device can be found in the limitations of the layout and routing optimization method described above, and will not be repeated here. Each module in the aforementioned layout and routing optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0092] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores architectural model data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a layout and routing optimization method.

[0093] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: receiving an architecture update instruction, the architecture update instruction carrying at least an optimization index for a target circuit region; obtaining a preset architecture model, the architecture model storing multiple basic algorithms, multiple scheduling logics, and encapsulation logic, the basic algorithms being used to optimize a certain parameter index of a specific region, the scheduling logics being used to call at least one basic algorithm to optimize the parameter index of the target circuit region, and the encapsulation logic containing a mapping relationship between the optimization index and the scheduling logic, the target circuit region being no smaller than the specific region; selecting at least one scheduling logic based on the optimization index and the encapsulation logic; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue iterating based on the change value of the optimization index or the algorithm result; when it is determined to stop iterating, encapsulating the optimized scheduling logic and the basic algorithm, generating and outputting the layout and routing corresponding to the target circuit region.

[0094] In one embodiment, when the processor executes a computer program, iteratively optimizes the basic algorithm for each scheduling logic call based on optimization metrics, including: determining the calling method of the basic algorithm in each scheduling logic; obtaining the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine candidate pins, and using the candidate pin traversal method to traverse the candidate pins; and calling the basic algorithm to optimize the candidate pins based on the calling method, thereby obtaining the change value or algorithm result corresponding to the optimization metrics.

[0095] In one embodiment, the candidate pin acquisition method implemented by the processor when executing a computer program includes: screening all data paths in the target circuit region where the timing margin is less than the target timing margin as critical paths, and using the terminating pin of the critical path as a candidate pin; or, selecting bottleneck pins with timing margins less than the target timing margin as candidate pins in all data paths of the target circuit region; or, after layering the data paths of the target circuit region, selecting pins with timing margins less than the target timing margin in each layer as candidate pins.

[0096] In one embodiment, the candidate pin traversal method implemented by the processor when executing a computer program includes: dividing the data path in the target circuit region into multiple complementary and interleaved regions, taking the critical path corresponding to the terminating pin in its region as the optimization object, traversing from the starting pin of the critical path from top to bottom, and calling a basic algorithm to optimize the critical path; or, dividing the data path in the target circuit region into multiple non-interleaved regions, traversing the bottleneck pins in each region and calling a basic algorithm to perform optimization; or, layering the data path in the target circuit region, assigning the candidate pins of each layer to multiple non-interleaved regions, traversing each layer from the starting pin to the terminating pin or in reverse, and calling a basic algorithm to perform optimization.

[0097] In one embodiment, the processor, when executing a computer program, determines whether to continue iteration based on the change value of the optimization index or the algorithm result, including: after each iteration, multiplying the difference between the change value of the optimization index or the algorithm result after the previous optimization and the target value of the optimization index by a fixed coefficient to estimate the target of the current optimization; terminating the iteration when the difference between the change value of the optimization index or the algorithm result and the target value is greater than the estimated result or the number of iterations exceeds the upper limit; or, after each iteration, calculating the average difference of each optimization based on the change value of the optimization index or the algorithm result, terminating the iteration when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit.

[0098] In one embodiment, when the processor executes a computer program, it implements the selection of at least one scheduling logic based on optimization metrics and encapsulation logic, including: acquiring at least one scheduling logic; modifying at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the acquired scheduling logic to generate a new scheduling logic.

[0099] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program performs the following steps: receiving an architecture update instruction, the architecture update instruction carrying at least an optimization index for a target circuit region; obtaining a preset architecture model, the architecture model storing multiple basic algorithms, multiple scheduling logics, and encapsulation logic, the basic algorithms being used to optimize a certain parameter index of a specific region, the scheduling logics being used to call at least one basic algorithm to optimize the parameter index of the target circuit region, and the encapsulation logic containing a mapping relationship between the optimization index and the scheduling logic, the target circuit region being no smaller than the specific region; selecting at least one scheduling logic based on the optimization index and the encapsulation logic; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue iterating based on the change value of the optimization index or the algorithm result; when it is determined to stop iterating, encapsulating the optimized scheduling logic and the basic algorithm, and generating and outputting the layout and routing corresponding to the target circuit region.

[0100] In one embodiment, when a computer program is executed by a processor, iterative optimization of the basic algorithm for each scheduling logic call based on optimization metrics is performed, including: determining the calling method of the basic algorithm in each scheduling logic; obtaining the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine candidate pins, and using the candidate pin traversal method to traverse the candidate pins; and calling the basic algorithm to optimize the candidate pins based on the calling method, thereby obtaining the change value or algorithm result corresponding to the optimization metrics.

[0101] In one embodiment, the candidate pin acquisition method implemented when the computer program is executed by the processor includes: screening all data paths in the target circuit region where the timing margin is less than the target timing margin as critical paths, and using the terminating pin of the critical path as a candidate pin; or, selecting bottleneck pins with timing margins less than the target timing margin as candidate pins in all data paths of the target circuit region; or, after layering the data paths of the target circuit region, selecting pins with timing margins less than the target timing margin in each layer as candidate pins.

[0102] In one embodiment, the candidate pin traversal method implemented when the computer program is executed by the processor includes: dividing the data path in the target circuit region into multiple complementary and interleaved regions, taking the critical path corresponding to the terminating pin in its region as the optimization object, traversing from the starting pin of the critical path from top to bottom, and calling the basic algorithm to optimize the critical path; or, dividing the data path in the target circuit region into multiple non-interleaved regions, traversing the bottleneck pins in each region and calling the basic algorithm to perform optimization; or, layering the data path in the target circuit region, assigning the candidate pins of each layer to multiple non-interleaved regions, traversing each layer from the starting pin to the terminating pin or in reverse, and calling the basic algorithm to perform optimization.

[0103] In one embodiment, when the computer program is executed by the processor, the function of determining whether to continue iteration based on the change value of the optimization index or the algorithm result includes: after each iteration, multiplying the difference between the change value of the optimization index or the algorithm result after the previous optimization and the target value of the optimization index by a fixed coefficient to estimate the target of the current optimization; terminating the iteration when the difference between the change value of the optimization index or the algorithm result and the target value is greater than the estimated result or the number of iterations exceeds the upper limit; or, after each iteration, calculating the average difference of each optimization based on the change value of the optimization index or the algorithm result, terminating the iteration when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit.

[0104] In one embodiment, when a computer program is executed by a processor, it implements the selection of at least one scheduling logic based on optimization metrics and encapsulation logic, including: acquiring at least one scheduling logic; modifying at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the acquired scheduling logic to generate a new scheduling logic.

[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for optimizing layout and routing, characterized in that, include: Receive architecture update instructions, which at least carry optimization metrics for the target circuit region; Obtain a preset architecture model, which stores multiple basic algorithms, multiple scheduling logics, and encapsulation logic. The basic algorithms are used to optimize a certain parameter index of a specific region. The scheduling logic is used to call at least one basic algorithm to optimize the parameter index of the target circuit region. The encapsulation logic contains the mapping relationship between the optimized index and the scheduling logic. The target circuit region is not smaller than the specific region. At least one scheduling logic is selected based on the optimization metrics and the encapsulation logic; Based on the optimization index, the basic algorithm for each scheduling logic call is iteratively optimized, and whether to continue iterating is determined based on the change value of the optimization index or the algorithm result. When it is determined that the iteration should stop, the optimized scheduling logic and basic algorithm are encapsulated, and the layout and routing corresponding to the target circuit area are generated and output.

2. The optimization method according to claim 1, characterized in that, The iterative optimization of the basic algorithm for each scheduling logic call based on the optimization index includes: Determine the invocation method of the basic algorithm described in each scheduling logic; Based on the scheduling logic, obtain the corresponding candidate pin acquisition method and candidate pin traversal method; The candidate pin acquisition method is called to determine the candidate pins, and the candidate pin traversal method is used to traverse the candidate pins. Based on the aforementioned invocation method, the basic algorithm is invoked to optimize the candidate pin, thereby obtaining the change value or algorithm result corresponding to the optimization index.

3. The optimization method according to claim 2, characterized in that, The method for obtaining candidate pins includes: Paths with timing margins less than the target timing margin in all data paths on the target circuit region are selected as critical paths, and the termination pin of the critical path is selected as the candidate pin. Alternatively, bottleneck pins with timing margins smaller than the target timing margin can be selected as candidate pins across all data paths in the target circuit region. Alternatively, after layering the data paths of the target circuit region, select the pins in each layer whose timing margin is less than the target timing margin as candidate pins.

4. The optimization method according to claim 2, characterized in that, The candidate pin traversal method includes: The data paths in the target circuit area are divided into multiple complementary and interleaved regions. The critical path corresponding to the termination pin in its region is taken as the optimization object. The critical path is traversed from top to bottom from the starting pin of the critical path, and the basic algorithm is called to optimize the critical path. Alternatively, the data path in the target circuit area can be divided into multiple non-overlapping areas, and the bottleneck pins in each area can be traversed and the basic algorithm can be called to perform optimization. Alternatively, the data paths in the target circuit region can be layered, and the candidate pins of each layer can be assigned to multiple non-overlapping regions. The optimization can be performed by traversing each layer from the starting pin to the ending pin or in reverse.

5. The optimization method according to claim 1, characterized in that, The step of determining whether to continue iteration based on the change in the optimization index or the algorithm result includes: After each iteration, the difference between the change value or algorithm result of the optimization index after the previous optimization and the target value of the optimization index is multiplied by a fixed coefficient to estimate the target of the current optimization; the iteration is terminated when the difference between the change value or algorithm result of the optimization index and the target value is greater than the estimated result or the number of iterations exceeds the upper limit. Alternatively, after each iteration, the average difference of each optimization is calculated based on the change in the optimization index or the algorithm result. When the average difference is less than a preset threshold or the number of iterations exceeds the upper limit, the iteration is terminated.

6. The optimization method according to claim 1, characterized in that, The optimization index is at least one of the following: optimized total negative margin, optimized worst negative margin, and optimized power and area.

7. The optimization method according to claim 1, characterized in that, The step of selecting at least one scheduling logic based on the optimization metric and the encapsulation logic includes: Obtain at least one scheduling logic; Modify at least one of the candidate pin acquisition method, candidate pin traversal method, and optimized iteration method in the scheduling logic to generate new scheduling logic; or assemble all the acquired scheduling logic to generate new scheduling logic.

8. A layout and wiring optimization device, characterized in that, The device includes: The instruction receiving module is used to receive architecture update instructions, which carry at least the optimization metrics of the target circuit region. The acquisition module is used to acquire a preset architecture model. The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logic. The basic algorithms are used to optimize a certain parameter index of a specific region. The scheduling logic is used to call at least one basic algorithm to optimize the parameter index of the target circuit region. The encapsulation logic contains the mapping relationship between the optimized index and the scheduling logic. The target circuit region is not smaller than the specific region. The filtering module is used to filter at least one scheduling logic based on the optimization index and the encapsulation logic; The optimization module is used to iteratively optimize the basic algorithm of each scheduling logic call based on the optimization index, and determine whether to continue iterating based on the change value of the optimization index or the algorithm result. The encapsulation module is used to encapsulate the optimized scheduling logic and basic algorithm when it is determined that the iteration should stop, and to generate and output the layout and routing corresponding to the target circuit area.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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