Silicon-erbium-doped lithium niobate photon calculation chip and photon convolutional neural network system thereof

Abstract

The invention provides a silicon-erbium-doped lithium niobate photon calculation chip, which adopts a wafer-to-wafer bonding mode, realizes heterogeneous integration of silicon and erbium-doped lithium niobate, and integrates devices such as a gain type delay array, a gain type electro-optical modulator, an interlayer coupler, a waveguide cross junction, a silicon-based phase shift array and an end face coupler in a monolithic manner. Complicated inter-chip coupling technology and optical interconnection steps are not needed, and inter-chip coupling loss is effectively avoided. The advantages of optical amplification on an erbium-doped lithium niobate sheet are fully exerted, so that the gain type electro-optical modulator and loss type devices such as a waveguide gain type delay line have gain performance, optical loss on the sheet is further compensated, and meanwhile, the signal processing speed and the capacity of executing complex calculation tasks are remarkably improved. Meanwhile, the advantages of high integration level and mature process of silicon are exerted; the advantage of high-speed electro-optical modulation of lithium niobate is exerted, the limitation of a single material platform on the integration scale is broken through, and high-density integration of devices is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photonic heterogeneous integration, and particularly relates to a silicon- erbium-doped lithium niobate photonic computing chip and its photonic convolutional neural network system. Technical Background

[0002] Microelectronic technology has promoted the integration of electronic devices. From the initial discrete components to today's complex integrated circuits, significant progress has been made in terms of cost, reliability, power consumption, and volume. However, with the continuous improvement of chip integration, traditional electronic computing architectures face numerous challenges, especially the bottlenecks in bandwidth, energy efficiency, and processing speed are becoming increasingly apparent. As Moore's Law gradually slows down, integrated circuit technology can no longer rely solely on transistor miniaturization to improve computing performance, and the progress of electronic information technology has gradually encountered physical limitations. This has led people to seek new computing paradigms, and optical computing has emerged as a potential breakthrough to solve this dilemma.

[0003] Optical computing utilizes the characteristics of light, including high-speed transmission, low power consumption, and high parallelism, to provide a new solution for computing tasks. Different from traditional electronic computing, optical computing architectures can process large-scale data parallel tasks on a single chip. At the same time, due to the propagation speed of light being close to the speed of light in a vacuum, optical computing systems have a natural low-latency advantage. In addition, photons have low losses during signal transmission and can transmit information at higher frequencies and over longer distances, thus greatly improving the bandwidth and rate of data processing.

[0004] However, despite the significant advantages of optical computing in terms of computing speed and energy efficiency, current optical computing technologies still face a series of challenges. In particular, as the integration scale increases, the computing power growth of optical computing systems generally follows a square relationship, which means that to leverage the advantages of optical computing in larger-scale integrated systems, it is necessary to expand the scale of the hardware. Larger-scale integration often requires more optical devices and optical path cascades to achieve more complex computing tasks. However, during this process, a certain degree of loss and distortion may be introduced in each stage of signal processing, especially when optical signals go through multiple cascades and conversions, their quality will gradually decline.

[0005] The root of this problem lies in the inherent characteristics of analog domain computing. Unlike digital computing, optical computing usually relies on the analog properties of light for signal processing. In 2024, Oxford University (Bowei D., et al., Partial coherence enhances parallelized photonic computing, Nature, 632, 55-62, 2024), through principle derivation and experimental verification, found that partially incoherent optical computing can achieve higher computing accuracy, and the computing accuracy can be increased to 5bit, but its application range is limited to a scale of 3×3. This shows that the problem of multi-level signal processing has not been fundamentally solved. Signal distortion will not only accumulate during transmission, but also couple with each other and be exponentially amplified in multi-level cascades, which will eventually lead to inaccurate calculation results, thereby limiting the calculation accuracy and stability of the system.

[0006] Therefore, how to effectively control signal distortion in optical systems and maintain high-quality signal transmission has become a major technical challenge that needs to be overcome in optical computing systems. Summary of the invention

[0007] In order to overcome the problems of low precision and large insertion loss of current photonic computing chips, the present invention proposes a photonic convolutional neural network chip based on silicon-erbium-doped lithium niobate heterogeneous integration, which adopts chip-to-wafer bonding to realize heterogeneous integration of silicon and erbium-doped lithium niobate, and integrates gain-type delay arrays, gain-type electro-optic modulators, interlayer couplers, waveguide cross junctions, silicon-based phase shift arrays, and end couplers on a single chip, without the need for complex inter-chip coupling processes and optical interconnection steps, effectively avoiding inter-chip coupling losses. Give full play to the advantages of on-chip optical amplification of erbium-doped lithium niobate, so that lossy devices such as electro-optic modulators and waveguide delay lines have gain performance, thereby compensating for on-chip optical losses, and significantly improving the speed of signal processing and the ability to perform complex computing tasks. At the same time, the advantages of high integration and mature technology of silicon are brought into play; the advantages of high-speed electro-optic modulation of lithium niobate are brought into play, breaking through the limitations of a single material platform on the scale of integration, and realizing high-density integration of devices.

[0008] The technical solution of the present invention is as follows:

[0009] A silicon-erbium-doped lithium niobate photonic computing chip is characterized in that the chip realizes heterogeneous integration of silicon and erbium-doped lithium niobate by bonding, and the overall structure is divided into a bonding area and a non-bonding area, and optical signal transmission is realized between the bonding area and the non-bonding area through an interlayer coupler. In the chip, an end coupler, a gain-type electro-optical modulator, and a photonic computing network are connected in sequence, the end coupler is used to couple the signal light and the pump light outside the chip to the waveguide inside the chip, the gain-type electro-optical modulator loads the radio frequency signal on the optical signal and inputs it into the photonic computing network, and the photonic computing network is used to process the on-chip optical signal.

[0010] The first - stage gain - type delay array. The photonic computing network is successively divided into M paths by a silicon - based optical splitter, and the delay of each path from top to bottom increases step - by - step, forming the first - stage gain - type delay array. The gain - type delay array is used for data shifting in the optical computing system. Optionally, the number of splitting paths of the silicon - based optical splitter is greater than or equal to four. Part of the optical power is distributed to a silicon - based phase shifter. The output port of the (M - 1)th first delay line is used as the Mth optical output port. Assuming the delay of each first delay line is t1, according to the above connection method, the signals at the M output ports of the first - stage delay and optical splitting module are respectively delayed by 0, t1, 2t1, …, (M - 1)×t1.

[0011] The silicon - based phase - shifter array. The silicon - based phase - shifter array is used to achieve weight control in the optical computing system. Optionally, the number of splitting paths of the silicon - based optical splitter is greater than or equal to four. Each optical input port is connected to the output port of the first - stage gain - type delay array, and a silicon - based beam splitter is connected after each optical input port, which is divided into M paths horizontally. The M - path outputs of different gain - type delay lines are combined vertically, thus forming a fully - connected topological structure. The optical signals output from each gain - type delay line are successively connected to M phase shifters through a silicon - based optical splitter, forming a phase - shifter array of MxM. Part of the silicon - based phase - shifter array uses waveguide cross - junctions to achieve low - crosstalk cross - transmission of optical signals. The waveguide cross - junctions do not change the transmission direction of optical signals, and the input and output waveguides of the waveguide cross - junctions are all in the same plane.

[0012] The second - stage gain - type delay array. After the optical signals are processed by the silicon - based phase - shifter array, the M silicon - based phase shifters in the vertical direction are connected to a photonic combiner and input into the second - stage optical gain - type delay lines. The signals are combined successively from left to right, and the gain - type delay lines decrease step - by - step to achieve data shifting of MxM - path signals. The delay of each delay line is t2. When the signals corresponding to each input port reach the output port, the delays they pass through are (M - 1)×t2, (M - 2)×t2, …, t2, 0. Optionally, the number of splitting paths of the silicon - based optical splitter is greater than or equal to four. Finally, the optical signals are output to the outside of the chip through an end - face coupler to complete the optical - domain calculation of data.

[0013] In the wafer bonding region of the silicon- erbium-doped lithium niobate photonic computing chip, the waveguide cross-section from bottom to top is successively a silicon substrate layer, a silicon oxide isolation layer, a silicon waveguide layer, a silicon oxide buffer layer, an erbium-doped lithium niobate layer, a silicon oxide cladding layer, and a metal electrode layer. In the non-wafer bonding region, the waveguide cross-section from bottom to top is successively a silicon substrate layer, a silicon oxide isolation layer, a silicon waveguide layer, and a silicon oxide buffer layer. The devices in the wafer bonding region include a gain-type delay array, a gain-type electro-optic modulator, and a silicon- erbium-doped lithium niobate interlayer coupler. The devices are mainly located in the erbium-doped lithium niobate layer, and the optical mode field is mainly distributed in the erbium-doped lithium niobate waveguide. Optical interconnection is achieved between the erbium-doped lithium niobate layer and the silicon waveguide layer through the interlayer coupler. The devices in the non-wafer bonding region include waveguide crossings, silicon-based phase-shift arrays, and end-face couplers. The devices are located in the silicon waveguide layer, and the optical mode field is mainly distributed in the silicon waveguide.

[0014] Since erbium-doped lithium niobate has the characteristic of stimulated emission optical amplification, the gain-type electro-optic modulator and the gain-type delay array have gain performance. The signal light and the pump light of the excitation source interact in this region, and high-linear amplification of the optical signal can be achieved. The gain generated in this region can compensate for the losses of the photonic computing network devices and the splitting losses. Therefore, the scale number of the silicon-based phase shifter array can be further expanded, and the signal quality received at the backend is synchronously improved.

[0015] The principle of realizing optical computing by the above technical solution is as follows:

[0016] Optical computing is a kind of analog-domain computing. The discrete input sequence x(n) can be expressed by the continuous-time variable x(t). The value of this variable changes every fixed time interval, and this fixed time is defined as the unit delay amount t1, that is, x(t + i×t1) = x(n + i). The key lies in constructing the corresponding delay amount, weight multiplication, and addition operations. The first-stage gain-type delay array in the technical solution of the present invention can form M kinds of delay combinations that increase successively, with an interval of t1, which can form the row elements in optical computing. The first-stage gain-type delay array can form M kinds of delay combinations that increase successively, with an interval of t2, which can traverse the column elements in optical computing. The above connection method and the silicon-based phase shifters configured on each connection can achieve the function of weight multiplication, and the silicon-based beam combiner can achieve the effect of addition.

[0017] A photonic convolutional neural network system is characterized in that it integrates the above silicon- erbium-doped lithium niobate photonic computing chip.

[0018] The technical effects of the present invention are as follows:

[0019] 1. The silicon - erbium - doped lithium niobate photonic computing chip of the present invention introduces the on - chip optical amplification characteristics of erbium - doped lithium niobate into the silicon - photonics platform, enabling gain - type electro - optic modulators and gain - type delay - line arrays to have on - chip optical amplification characteristics, effectively improving the optical loss budget of the optical link, breaking through the limitations of splitting loss and modulator loss on the integration scale, and doubling the optical computing scale and computing accuracy.

[0020] 2. The present invention is integrated based on the wafer - to - wafer bonding method, with flexible bonding positions. Bonding only needs to be carried out in the modulation area, and it avoids the problem that the current erbium - doped lithium niobate wafers limit the integration scale due to their small size.

[0021] 3. The present invention utilizes the advantages of silicon materials and the erbium - doped lithium niobate platform to separately fabricate the advantageous devices suitable for each. By controlling the dynamic movement of photons and mutual adjustment through the connection between devices, complex optical path designs are carried out, integrating signal delay, weight loading, and convolution calculation in optical computing onto a single chip, enabling a single chip to simultaneously execute complex computing tasks.

[0022] 4. The silicon - erbium - doped lithium niobate photonic computing chip described in the present invention is monolithically integrated, without the need for complex inter - chip coupling processes and optical interconnection steps, avoiding the loss of light caused by chip - to - chip coupling, greatly improving the device integration degree and integration scale, realizing the integration of diverse device types and array - type device scales, and providing a hardware foundation for photonic computing to process high - precision and high - complexity tasks. Description of the Drawings

[0023] Figure 1 Schematic diagram of the silicon - erbium - doped lithium niobate photonic computing chip of the present invention

[0024] Figure 2 is a cross - sectional schematic diagram of the silicon - erbium - doped lithium niobate photonic computing chip of the present invention. Among them, (a) is the wafer cross - sectional view of the non - bonding area, and (b) is the wafer cross - sectional view of the bonding area.

[0025] Figure 3 Inter - layer coupler of the present invention

[0026] In the figure: 1 - non - bonding area; 2 - bonding area; 3 - silicon substrate layer; 4 - silicon oxide isolation layer; 5 - silicon waveguide layer; 6 - silicon oxide buffer layer; 7 - erbium - doped lithium niobate layer; 8 - silicon oxide cladding layer; 9 - metal electrode layer;

[0027] 1 - 1 end - face coupler; 1 - 2 silicon - based phase - shift array; 1 - 3 waveguide cross - junction; 1 - 4 silicon - based optical splitter; 2 - 1 inter - layer coupler; 2 - 2 gain - type electro - optic modulator; 2 - 3 gain - type delay array; Detailed Embodiments

[0028] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. Specific embodiments and structures are given, but the protection scope of the present invention is not limited to the following embodiments.

[0029] This embodiment provides a silicon-doped erbium lithium niobate photonic computing chip. Through the wafer-to-wafer bonding technology, silicon and erbium-doped lithium niobate are tightly bonded together to form a heterogeneous integration structure. The overall structure is divided into a bonding region 2 and a non-bonding region 1. The wafer bonding region 2 contains devices such as a gain-type delay array 2-3, a gain-type electro-optic modulator 2-2, and an interlayer coupler 2-1, mainly located in the erbium-doped lithium niobate layer 7. The non-wafer bonding region contains devices such as a waveguide crossing 1-3, a silicon-based phase-shift array 1-2, and an end-face coupler 1-1, mainly located in the silicon waveguide layer 5. In the bonding region, the chip is composed of a silicon substrate, a silicon oxide isolation layer, a silicon waveguide layer, a silicon oxide buffer layer, an erbium-doped lithium niobate layer, a silicon oxide cladding layer, and a metal electrode layer. These layers are arranged in sequence in the vertical direction to form a complex waveguide structure. In the non-wafer bonding region, it only contains a silicon substrate, a silicon oxide isolation layer, and a silicon waveguide layer. In the wafer bonding region, the optical mode field is mainly distributed in the erbium-doped lithium niobate waveguide; in the non-wafer bonding region, the optical mode field is mainly distributed in the silicon waveguide.

[0030] In this chip, the end-face coupler 1-1, the gain-type electro-optic modulator 2-2, and the photonic computing network are connected in sequence.

[0031] The end-face coupler 1-1 is located at the edge of the chip and is connected to an external light source and a signal source, and is used to couple the off-chip signal light and pump light into the on-chip waveguide.

[0032] The gain-type electro-optic modulator 2-2 is connected to the end-face coupler 1-1, receives the coupled optical signal, loads the radio frequency signal onto the optical signal, and inputs it into the photonic computing network. This gain-type electro-optic modulator not only has a modulation function but also has a gain performance, which can compensate for the loss of the optical signal during transmission. It can not only modulate the optical signal (i.e., change certain characteristics of the optical signal, such as intensity, phase, or polarization), but also enhance the intensity of the optical signal to ensure that the signal maintains sufficient intensity during transmission.

[0033] The photonic computing network is used to process the on-chip optical signal and is composed of a first-stage gain-type delay array, a silicon-based phase-shift array 1-2, and a second-stage gain-type delay array, realizing data shifting, weight regulation, and addition operations.

[0034] Wherein:

[0035] First - stage gain - type delay array: It is used for data shifting. The optical signal is divided into M paths by a silicon - based optical splitter, and the delay of each path from top to bottom increases step - by - step, forming a delay gradient. That is, part of the optical power is distributed to a silicon - based phase shifter. The output port of the (M - 1) - th first - stage delay line serves as the M - th optical output port. Let the delay of each first - stage delay line be t1. According to the above connection method, the signals at the M output ports of the first - stage delay and splitting module are delayed by 0, t1, 2t1, …, (M - 1)×t1 respectively.

[0036] Silicon - based phase - shift array: It is used for weight regulation. Each optical input port is connected to the output port of the first - stage gain - type delay array, and a silicon - based beam splitter is connected behind each optical input port, which is divided into M paths horizontally. The M - path outputs of different gain - type delay lines are combined vertically, thus forming a fully - connected topological structure. The optical signals output from each gain - type delay line are successively connected to M path - phase shifters through a silicon - based optical splitter, forming an M×M silicon - based phase - shift array. By adjusting the phase of each optical signal, the weight adjustment is realized, and the weight regulation of the optical computing system is achieved. The waveguide cross - junction is used to realize low - crosstalk cross - transmission of optical signals. The waveguide cross - junction does not change the transmission direction of optical signals, and the input and output waveguides of the waveguide cross - junction are both in the same plane.

[0037] Second - stage gain - type delay array: It is used for further data shifting; the optical signals that have undergone weight regulation are combined and delayed. The M silicon - based phase shifters in the vertical direction are connected to the optical combiner and input into the second - stage optical gain - type delay line, and are combined successively from left to right. The gain - type delay line decreases step - by - step, realizing data shifting of M×M - path signals. The delay of each delay line is t2. When the signals corresponding to each input port reach the output port, the delays experienced are (M - 1)×t2, (M - 2)×t2, …, t2, 0 respectively. Finally, the optical signal is output to the outside of the chip through the end - face coupler, completing the optical - domain calculation of data.

[0038] Figure 2 is a cross - sectional schematic diagram of the silicon - erbium - doped lithium niobate photonic computing chip of the present invention. As shown in the figure, the bonding region 2, from bottom to top, is successively a silicon substrate layer 3, a silicon dioxide isolation layer 4, a silicon waveguide layer 5, a silicon dioxide buffer layer 6, an erbium - doped lithium niobate layer 7, a silicon dioxide cladding layer 8, and a metal electrode layer 9. The silicon dioxide layer is placed between the silicon substrate layer 3 and the silicon waveguide layer 5, and between the erbium - doped lithium niobate layer 7 and the metal electrode layer 9 as an isolation layer. The silicon dioxide layer serves as a buffer layer between the silicon waveguide layer 5 and the erbium - doped lithium niobate layer 7. In the non - wafer bonding region 1, the waveguide cross - section from bottom to top is successively a silicon substrate layer 3, a silicon dioxide isolation layer 4, and a silicon waveguide layer 5.

[0039] The gain electro-optic modulator 2-2 is integrated on the silicon waveguide layer 5 and consists of a hybrid waveguide composed of an erbium-doped lithium niobate layer 7, a silica buffer layer 8, and a silicon waveguide layer 9. The silicon-erbium-doped lithium niobate interlayer coupler 2-1 is integrated on the silicon waveguide layer 5 and the erbium-doped lithium niobate layer 7, and adopts a tapered gradient coupler structure with upper and lower layers, and tapered waveguide structures are respectively arranged in the silicon waveguide layer 5 and the lithium niobate thin film layer 7.

[0040] In an embodiment, the splitting number of the optical splitter is four, and the original optical signal is divided into M paths and transmitted to the photonic computing network respectively. At this time, the loss brought by the splitting to a single optical signal is 6 dB. As long as the gain of the gain electro-optic modulator 2-2 is above 6 dB, the loss brought by the silicon-based optical splitter to the original optical signal can be compensated.

[0041] The gain delay line array 2-3 can also compensate for the splitting loss, such as Figure 1 As shown, in a 4x4 array, each optical signal will pass through an optical delay line after splitting. When the optical signal is split equally each time, the loss brought by the splitting to a single optical signal is 3 dB. As long as the gain of a single gain delay line is above 3 dB, the loss brought by the splitting can be compensated. When the optical signal is split into 1:3 each time, the loss brought by the splitting to a single optical signal is 6 dB. As long as the gain of a single gain delay line is above 6 dB, the loss brought by the splitting can be compensated. When the optical signal is split into 1:7 each time, the loss brought by the splitting to a single optical signal is 9 dB. As long as the gain of a single gain delay line is above 9 dB, the loss brought by the splitting can be compensated.

[0042] The gain delay line array 2-3 can compensate for the optical loss of the silicon-based phase shifter array 1-2, such as Figure 1 As shown, in a 4x4 array, the optical signal will pass through the gain delay line array 2-3 after three paths of signals are combined. In each longitudinal branch, the optical signal is regulated by four silicon-based phase shifters. Therefore, when the loss of each silicon-based phase shifter is 0.5 dB, as long as the gain of a single gain delay line is above 2 dB, the loss brought by the phase shift can be compensated. When the loss of each silicon-based phase shifter is 1 dB, as long as the gain of a single gain delay line is above 4 dB, the loss brought by the phase shift can be compensated.

[0043] In this embodiment, if the scale of the photonic computing network is n×n, the number of gain delay lines in the two gain delay line arrays 2-3 is n-1 respectively, the number of silicon-based phase shifters in each group of silicon-based phase shifter arrays 1-2 is n, and there are n groups of silicon-based phase shifter arrays 1-2. The signal light and the pump light are combined before splitting, and the pump light always exists in the photonic circuit to provide the energy required for optical amplification of the signal light.

[0044] In practical applications, in this embodiment, the gains of the gain-type electro-optic modulator 2-2 and the gain-type delay line array 2-3 can be combined and designed according to the splitting number of the required photonic computing network and the actual device loss of the device. The gain can be changed by the waveguide structures of the gain-type electro-optic modulator 2-2 and the gain-type delay line array 2-3, or the gain can be changed by changing the doping concentration of erbium-doped lithium niobate, so as to increase the loss budget of the photonic link. The invention can multiply increase the integration scale of the optical computing system, improve the processing accuracy of the photonic computing chip, and the pump light and signal light lasers can be further integrated on the chip to achieve monolithic integration, reduce the inter-chip coupling loss. In this way, the system integration degree can be improved, the chip miniaturization and large-scale integration can be realized, and it has high application value.

Claims

1. A silicon-doped erbium lithium niobate photonic computing chip, characterized in that, The chip integrates a silicon substrate and erbium-doped lithium niobate by bonding to form a heterogeneous integration structure; this structure is divided into a bonding region and a non-bonding region, where: The non-bonding region includes: An end-face coupler for coupling the off-chip signal light and pump light into the waveguide inside the chip. A silicon-based phase-shifting array connected to the output of the first-stage gain-type delay array, used to implement weight regulation in the optical computing system, including multiple silicon-based phase shifters, each phase shifter being connected to the output of the corresponding delay line. A waveguide cross-junction for realizing low-crosstalk cross-transmission of optical signals, and the input and output waveguides are in the same plane. A silicon-based optical splitter for splitting the optical signal into multiple paths to form a delay array. The bonding region includes: An interlayer coupler for realizing optical signal interconnection between the non-bonding region and the bonding region. A gain-type electro-optic modulator for loading a radio frequency signal onto the optical signal and having a gain performance to compensate for optical signal loss. The first-stage gain-type delay array, connected to the gain-type electro-optic modulator, is composed of multiple delay lines split by a silicon-based optical splitter. The delay amount of each delay line increases step by step, used for data shifting in the optical computing system. The second-stage gain-type delay array, connected to the output of the silicon-based phase-shifting array, is used to further process the optical signal and realize data shifting, including multiple delay lines. The delay amount of each delay line decreases step by step relative to the first stage or is configured in a different way to achieve the required data processing. Among them, the chip inputs the signal light and pump light through the end-face coupler, enters the photonic computing network through the gain-type electro-optic modulator, is split into multiple paths by the silicon-based optical splitter, undergoes delay processing through the gain-type delay array, then has its weight regulated by the silicon-based phase shifter array, and part of the optical path realizes low-crosstalk transmission through the waveguide cross-junction. Finally, after being combined by the optical combiner and possibly undergoing another delay processing, it is output to the outside of the chip through the end-face coupler to complete the optical-domain calculation of the data.

2. The silicon- erbium-doped lithium niobate photonic computing chip according to claim 1, characterized in that Each silicon-based phase shifter in the silicon-based phase-shifting array is connected to the output of the corresponding delay line through a waveguide to form a fully connected topological structure.

3. The silicon- erbium-doped lithium niobate photonic computing chip according to claim 1, wherein The number of delay lines in the first-stage gain-type delay array and the second-stage gain-type delay array is the same, and the delay amount of each delay line is configured in a step-by-step increasing and decreasing manner respectively.

4. The silicon- erbium-doped lithium niobate photonic computing chip according to claim 1, wherein The waveguide cross-section of the chip from bottom to top in the wafer bonding region is successively a silicon substrate layer, a silicon oxide isolation layer, a silicon waveguide layer, a silicon oxide buffer layer, an erbium-doped lithium niobate layer, a silicon oxide cladding layer, and a metal electrode layer; in the non-wafer bonding region, the waveguide cross-section from bottom to top is successively a silicon substrate layer, a silicon oxide isolation layer, a silicon waveguide layer, and a silicon oxide buffer layer.

5. The silicon- erbium-doped lithium niobate photonic computing chip according to any one of claims 1 to 48, characterized in that, The gain-type electro-optic modulator and the gain-type delay array utilize the stimulated emission light amplification characteristic of erbium-doped lithium niobate to achieve high-linear amplification of the optical signal and compensate for the loss of photonic computing network devices and splitting loss.

6. The silicon- erbium - doped lithium niobate photonic computing chip according to claim 5, wherein The gain-type electro-optic modulator is integrated on the silicon waveguide layer, and its function is realized by a hybrid waveguide composed of an erbium-doped lithium niobate layer, a silicon oxide buffer layer, and a silicon waveguide layer.

7. The silicon- erbium-doped lithium niobate photonic computing chip according to claim 1, characterized in that, The interlayer coupler is integrated on the silicon waveguide layer and the erbium-doped lithium niobate layer, and adopts a tapered coupler structure with upper and lower layers, and a tapered waveguide structure is respectively arranged in the silicon waveguide layer and the lithium niobate thin film layer.

8. A photon convolution neural network system, characterized in that, Integrated with the silicon-erbium-doped lithium niobate photonic computing chip according to any one of claims 1-6.

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