Memory device, memory system, and operating method of memory device

Abstract

A memory device, a memory system, and an operating method of the memory device are provided. The memory device may include a first correction circuit configured to adjust phases of first to fourth clock signals and output first to fourth corrected clock signals; a second correction circuit configured to output first to fourth offset clock signals based on a size of each of first to fourth reference data included in the first data signal; and a driver configured to output a second data signal based on the first to fourth corrected clock signals.

Description

Technical Field

[0001] The present disclosure relates to a storage device, and more particularly, to a storage device including a clock signal correction circuit, a memory system, and an operating method of the storage device. Background Art

[0002] A clock signal can provide timing for circuits included in a storage device to operate. A four-phase clock signal can include four clock signals, each clock signal being configured to have a 90-degree phase difference, and the storage device can perform operations instructed by a memory controller based on these four clock signals.

[0003] When the storage device performs a read operation, the four-phase clock signal can be provided to each element in the storage device along a clock signal path configured in the storage device. During this transmission process, the phase of each clock signal may have an error, and as the number of transistors arranged in the path for transmitting the clock signal increases, the error may increase. Summary of the Invention

[0004] Generally, in some aspects, the present disclosure relates to a storage device configured to operate at an accurate timing by arranging a correction circuit at a position that minimizes an error in a four-phase clock signal of the storage device, thereby increasing the accuracy of a data signal output from the storage device.

[0005] According to some embodiments, the present disclosure relates to a storage device that may include: a memory cell array that stores first data to fourth data; a first correction circuit configured to receive a first clock signal to a fourth clock signal and a control signal, adjust phases of the first clock signal to the fourth clock signal based on the control signal, and output a first corrected clock signal to a fourth corrected clock signal; a second correction circuit configured to receive the first clock signal to the fourth clock signal through the first correction circuit, adjust phases of the first clock signal to the fourth clock signal based on magnitudes of each of first reference data to fourth reference data included in a first data signal, and output a first offset clock signal to a fourth offset clock signal; a control circuit configured to generate the control signal based on the first offset clock signal to the fourth offset clock signal received from the second correction circuit; and a driver configured to output a second data signal including the first data to the fourth data read from the memory cell array based on the first corrected clock signal to the fourth corrected clock signal received from the first correction circuit.

[0006] According to some embodiments, the present disclosure relates to an operation method of a storage device. The operation method may include: generating first to fourth clock signals based on a first reference clock signal and a second reference clock signal; generating first to fourth offset clock signals based on the magnitude of each of first to fourth reference data included in a first data signal; generating first to fourth corrected clock signals by adjusting the phases of the first to fourth clock signals based on the first to fourth offset clock signals; and outputting a second data signal including data stored in the storage device based on the first to fourth corrected clock signals.

[0007] According to some embodiments, the present disclosure relates to a memory system. The memory system may include: a memory controller configured to generate a first reference clock signal, a second reference clock signal, and a first control signal; and a storage device configured to provide a first data signal and a second data signal to the memory controller. Wherein, the storage device may include: a memory cell array storing first to fourth data; a clock buffer circuit configured to generate first to fourth clock signals based on the first reference clock signal and the second reference clock signal; a first correction circuit configured to receive the first to fourth clock signals and a second control signal, adjust the phases of the first to fourth clock signals based on the second control signal, and output first to fourth corrected clock signals; a second correction circuit configured to receive the first to fourth clock signals through the first correction circuit, adjust the phases of the first to fourth clock signals based on the first control signal, and output first to fourth offset clock signals; a control circuit configured to generate the second control signal based on the first to fourth offset clock signals received from the second correction circuit; and a driver configured to output the second data signal including the first to fourth data read from the memory cell array based on the first to fourth corrected clock signals received from the first correction circuit. And the memory controller is further configured to generate the first control signal to adjust the phases of the first to fourth clock signals based on the magnitude of each of the first to fourth reference data included in the first data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of an example of a memory system according to some embodiments.

[0010] Figure 2 is a block diagram of an example of an input / output circuit according to some embodiments.

[0011] Figure 3 is a timing diagram showing an example of a reference clock signal and an input clock signal according to some embodiments.

[0012] Figure 4 is a timing diagram showing an example of a clock signal of a storage device according to some embodiments.

[0013] Figure 5 is a block diagram of an example of an input / output circuit according to some embodiments.

[0014] Figure 6 is a timing diagram showing an example of data output from a storage device according to a clock signal according to some embodiments.

[0015] Figures 7A to 7E is a timing diagram describing an example of a storage device that corrects a clock signal according to some embodiments.

[0016] Figure 8 is a flowchart describing an example of an operation method of a storage device according to some embodiments.

[0017] Figure 9 is a block diagram of an example of a system of an electronic device including a storage device according to some embodiments. Detailed Description

[0018] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. When describing embodiments with reference to the drawings, the same reference numerals are assigned to the same or corresponding elements, and redundant descriptions thereof are omitted.

[0019] Figure 1 is a block diagram of an example of a memory system according to some embodiments. In Figure 1Among them, the memory system 10 can be referred to as a computing device, such as an integrated circuit, an electronic device or system, a smart phone, a desktop personal computer (PC), a computer, a server, a workstation, a mobile communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), and other suitable computers, virtual machines or their virtual computing devices. In some embodiments, the memory system 10 can be a part of an element included in a computing system, such as a graphics card. According to some embodiments, the memory system 10 can be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0020] The memory system 10 may include a memory controller 100 and a storage device 200. The memory controller 100 may provide a clock signal CLK, a command / address signal CA, an offset control signal CTRL_os, and a data signal DQ to the storage device 200. The memory controller 100 may be communicatively connected to the storage device 200 via a memory bus. The clock signal CLK, the command / address signal CA, the offset control signal CTRL_os, and the data signal DQ may be provided between the memory controller 100 and the storage device 200 via a single signal line. The signal lines between the memory controller 100 and the storage device 200 may be connected via a connector. The connector may be implemented as pins, balls, signal lines, or other hardware components. The data signal DQ may be sent from the memory controller 100 to the storage device 200, or from the storage device 200 to the memory controller 100.

[0021] In some embodiments, when the memory controller 100 reads data stored in the storage device 200, the storage device 200 may provide a data signal DQ including the data read according to the clock signal CLK to the memory controller 100.

[0022] The memory controller 100 may generate an offset control signal CTRL_os based on the size of the data included in the data signal DQ received from the storage device 200. The memory controller 100 may adjust the phase of the clock signal within the storage device 200 via the offset control signal CTRL_os. A description of the offset control signal CTRL_os will be provided below with reference to Figure 5 Provide a description of the offset control signal CTRL_os.

[0023] The memory device 200 may include a memory cell array 210 and an input / output (I / O) circuit 220. The memory cell array 210 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. The plurality of memory cells may be respectively formed at points where the word lines and the bit lines cross each other. Each memory cell may include a volatile memory cell (e.g., a dynamic random access memory (DRAM) cell or a static RAM (SRAM) cell). However, the present disclosure is not limited thereto.

[0024] The I / O circuit 220 may receive a clock signal CLK from the memory controller 100. When the memory device 200 performs a write operation, the I / O circuit 220 may be configured to receive a data signal DQ. When the memory device 200 performs a read operation, the I / O circuit 220 may send the data signal DQ to the memory controller 100. In addition, the I / O circuit 220 may generate a four-phase clock signal based on the clock signal CLK received from the memory controller 100. The memory device 200 may include a correction circuit for correcting an error in the four-phase clock signal. The memory device 200 may correct an error in the four-phase clock signal through the correction circuit, thereby improving the accuracy of data reading accordingly. A description thereof will be provided below with reference to Figure 5 Provide a description thereof.

[0025] Figure 2 Is a block diagram of an example of an input / output circuit according to some embodiments. Reference may be made to Figure 1 For Figure 2 A description will be made, and redundant descriptions may be omitted.

[0026] In Figure 2 The I / O circuit 220 may receive a clock signal CLK from the memory controller 100. The clock signal CLK may include a first reference clock signal CLK_ref and a second reference clock signal CLKB_ref. The first reference clock signal CLK_ref and the second reference clock signal CLKB_ref may have the same period, and the phase difference between the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref may be 180 degrees. As Figure 2 Shown, the arrows indicated by the dashed lines from the clock buffer 221 to the driver 225 may refer to the clock path, that is, the path for sending the clock signal received from the memory controller 100. As used herein, the clock path may also be referred to as the read path.

[0027] The I / O circuit 220 may include a clock buffer 221, a delay locked loop (DLL) 222, a clock compensation loop circuit 223, and a driver 225. The clock buffer 221 may generate a four-phase clock signal based on a first reference clock signal CLK_ref and a second reference clock signal CLKB_ref received from the memory controller 100. The four-phase clock signal may be a clock signal having a respective frequency lower than the frequencies of the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref. As used herein, the clock buffer 221 may also be referred to as a clock divider. The four-phase clock signal may include, for example, a first input clock signal I_CLK_in, a second input clock signal Q_CLK_in, a third input clock signal IB_CLK_in, and a fourth input clock signal QB_CLK_in. In some embodiments, the clock buffer 221 may output the first input clock signal I_CLK_in and the third input clock signal IB_CLK_in based on the first reference clock signal CLK_ref. The phase difference between the first input clock signal I_CLK_in and the third input clock signal IB_CLK_in may be 180 degrees. The frequency of each of the first input clock signal I_CLK_in and the third input clock signal IB_CLK_in may be lower than (or less than) the frequency of the first reference clock signal CLK_ref. In other words, the period of each of the first input clock signal I_CLK_in and the third input clock signal IB_CLK_in may be longer than the period of the first reference clock signal CLK_ref. The clock buffer 221 may output the second input clock signal Q_CLK_in and the fourth input clock signal QB_CLK_in based on the second reference clock signal CLKB_ref. The phase difference between the second input clock signal Q_CLK_in and the fourth input clock signal QB_CLK_in may be 180 degrees. The frequency of each of the second input clock signal Q_CLK_in and the fourth input clock signal QB_CLK_in may be lower than the frequency of the second reference clock signal CLKB_ref. In other words, the period of each of the second input clock signal Q_CLK_in and the fourth input clock signal QB_CLK_in may be longer than the period of the second reference clock signal CLKB_ref.

[0028] The DLL 222 can receive a first input clock signal I_CLK_in, a second input clock signal Q_CLK_in, a third input clock signal IB_CLK_in, and a fourth input clock signal QB_CLK_in from the clock buffer 221. The DLL 222 can delay the phase of each received clock signal by a certain period of time, and can provide a first clock signal I_CLK, a second clock signal Q_CLK, a third clock signal IB_CLK, and a fourth clock signal QB_CLK as delayed clock signals to the clock compensation loop circuit 223. In this case, the magnitudes of the periods of time for which the respective clock signals are delayed can all be the same. This will be described below with reference to Figure 4 be described.

[0029] The clock compensation loop circuit 223 can include a first correction circuit 223_1, a second correction circuit 223_2, and a control circuit 223_3. The clock compensation loop circuit 223 can receive an offset control signal CTRL_os from the memory controller 100. The second correction circuit 223_2 can generate an offset clock signal based on the offset control signal CTRL_os. As used herein, the offset control signal CTRL_os can also be referred to as a first control signal. The control circuit 223_3 can generate a correction control signal according to the offset clock signal received from the second correction circuit 223_2, and the correction control signal is used to adjust the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK received by the first correction circuit 223_1. The first correction circuit 223_1 can, in response to the correction control signal received from the control circuit 223_3, provide a first corrected clock signal I_CLK_cr, a second corrected clock signal Q_CLK_cr, a third corrected clock signal IB_CLK_cr, and a fourth corrected clock signal QB_CLK_cr with adjusted phases to the driver 225. A detailed description of the clock compensation loop circuit 223 will be provided below with reference to Figure 3 provide a detailed description of the clock compensation loop circuit 223.

[0030] The driver 225 can receive read data RDT from the storage cell array 210. The read data RDT can be data stored in the storage cell array 210. The driver 225 can output a data signal DQ based on the first corrected clock signal I_CLK_cr, the second corrected clock signal Q_CLK_cr, the third corrected clock signal IB_CLK_cr, and the fourth corrected clock signal QB_CLK_cr received from the clock compensation loop circuit 223. The data signal DQ can include the read data RDT.

[0031] Figure 3 is a timing diagram showing examples of a reference clock signal and input clock signals according to some embodiments. It can be referred toFigure 1 and Figure 2 pair Figure 3 is described, and redundant descriptions may be omitted.

[0032] In Figure 3 it, a first reference clock signal CLK_ref, a second reference clock signal CLKB_ref, a first input clock signal I_CLK_in, a second input clock signal Q_CLK_in, a third input clock signal IB_CLK_in, and a fourth input clock signal QB_CLK_in are shown.

[0033] The memory controller 100 may generate the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref, and provide the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref to the memory device 200.

[0034] In some embodiments, the period of each of the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref may be a first period ΔTP1. As used herein, the first period ΔTP1 may be referred to as a reference period, and the period corresponding to half of the reference period may be referred to as a second period ΔTP2.

[0035] In some embodiments, the period of each of the first input clock signal I_CLK_in, the second input clock signal Q_CLK_in, the third input clock signal IB_CLK_in, and the fourth input clock signal QB_CLK_in may correspond to twice the first period ΔTP1.

[0036] In some embodiments, the first input clock signal I_CLK_in, the second input clock signal Q_CLK_in, the third input clock signal IB_CLK_in, and the fourth input clock signal QB_CLK_in may all be configured to have a phase difference corresponding to the second period ΔTP2. That is, the phase difference between the second input clock signal Q_CLK_in and the first input clock signal I_CLK_in may be 90 degrees. The phase difference between the third input clock signal IB_CLK_in and the first input clock signal I_CLK_in may be 180 degrees. The phase difference between the fourth input clock signal QB_CLK_in and the first input clock signal I_CLK_in may be 270 degrees.

[0037] Figure 4 is a timing diagram showing an example of clock signals of a memory device according to some embodiments. Reference may be made to Figures 1 to 3 pair Figure 4 is described, and redundant descriptions may be omitted.

[0038] In Figure 4 it, a first clock signal I_CLK, a second clock signal Q_CLK, a third clock signal IB_CLK, and a fourth clock signal QB_CLK are shown.

[0039] The DLL 222 can receive a first input clock signal I_CLK_in, a second input clock signal Q_CLK_in, a third input clock signal IB_CLK_in, and a fourth input clock signal QB_CLK_in, and delay each input clock signal by the same phase. For example, the first clock signal I_CLK can be a signal obtained by delaying the first input clock signal I_CLK_in by a first time period ΔT1. The second clock signal Q_CLK can be a signal obtained by delaying the second input clock signal Q_CLK_in by the first time period ΔT1. The third clock signal IB_CLK can be a signal obtained by delaying the third input clock signal IB_CLK_in by the first time period ΔT1. The fourth clock signal QB_CLK can be a signal obtained by delaying the fourth input clock signal QB_CLK_in by the first time period ΔT1.

[0040] The DLL 222 can output the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK generated by delaying the first input clock signal I_CLK_in, the second input clock signal Q_CLK_in, the third input clock signal IB_CLK_in, and the fourth input clock signal QB_CLK_in by the first time period ΔT1, respectively.

[0041] Figure 5 is a block diagram of an example of an input / output circuit according to some embodiments. Reference may be made to Figure 1 and Figure 2 for Figure 5 description, and redundant descriptions may be omitted.

[0042] In Figure 5 it, the I / O circuit 220 can include a clock compensation loop circuit 223, a third repeater (RPT3) 224, and a driver 225. In Figure 5In order to facilitate the description, only the clock compensation loop circuit 223, RPT3 224, and driver 225 are shown as elements of the I / O circuit 220. The clock compensation loop circuit 223 may include a first correction circuit 223_1, a second correction circuit 223_2, a control circuit 223_3, a first repeater (RPT1) 223_4, and a second repeater (RPT2) 223_5. In an embodiment, each of RPT1 223_4, RPT2 223_5, and RPT3 224 may be a circuit configured to amplify a received signal and send the amplified signal to a single element.

[0043] The first correction circuit 223_1 may receive a first clock signal I_CLK, a second clock signal Q_CLK, a third clock signal IB_CLK, and a fourth clock signal QB_CLK. In the following description, except Figure 5 for, for convenience of description, it is assumed that the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK have been Figure 2 adjusted by the DLL 222 as shown.

[0044] The first correction circuit 223_1 may provide the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK to the second correction circuit 223_2 through RPT1 223_4. The first correction circuit 223_1 may provide a first corrected clock signal I_CLK_cr, a second corrected clock signal Q_CLK_cr, a third corrected clock signal IB_CLK_cr, and a fourth corrected clock signal QB_CLK_cr to RPT3 224 through RPT2 223_5. As used herein, the first correction circuit 223_1 may also be referred to as a quadrature error correction circuit (QEC). In an embodiment, each of RPT1 223_4 and RPT2 223_5 may include a plurality of inverters.

[0045] The first correction circuit 223_1 may perform correction of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK based on a correction control signal CTRL_cr generated by the control circuit 223_3. As used herein, the correction control signal CTRL_cr may also be referred to as a second control signal. The control circuit 223_3 may also be referred to as a quadrature error detection circuit (QED).

[0046] In some embodiments, the calibration control signal CTRL_cr may include offset information regarding the first clock signal I_CLK, offset information regarding the second clock signal Q_CLK, offset information regarding the third clock signal IB_CLK, and offset information regarding the fourth clock signal QB_CLK.

[0047] The second calibration circuit 223_2 may receive an offset control signal CTRL_os from the memory controller 100. The second calibration circuit 223_2 may, in accordance with the indication of the offset control signal CTRL_os, generate a first offset clock signal I_CLK_os, a second offset clock signal Q_CLK_os, a third offset clock signal IB_CLK_os, and a fourth offset clock signal QB_CLK_os by delaying or advancing the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK by an offset amount. The second calibration circuit 223_2 may provide the first offset clock signal I_CLK_os, the second offset clock signal Q_CLK_os, the third offset clock signal IB_CLK_os, and the fourth offset clock signal QB_CLK_os to the control circuit 223_3. In some embodiments, the second calibration circuit 223_2 may be referred to as a global duty cycle adjustment circuit (GDCA).

[0048] The control circuit 223_3 may determine the degree to which the clock signals received by the first calibration circuit 223_1 are delayed based on the first offset clock signal I_CLK_os, the second offset clock signal Q_CLK_os, the third offset clock signal IB_CLK_os, and the fourth offset clock signal QB_CLK_os. The control circuit 223_3 may adjust the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK. In this case, the direction in which the control circuit 223_3 adjusts the phase may be opposite to the direction in which the second calibration circuit 223_2 adjusts the phase. For example, it may be assumed that the second calibration circuit 223_2 generates the second offset clock signal Q_CLK_os by advancing the phase of the second clock signal Q_CLK by a second time period. In this case, the control circuit 223_3 may control the first calibration circuit 223_1 such that the phase of the second clock signal Q_CLK output to the RPT2 223_5 is delayed by the second time period by the calibration control signal CTRL_cr. Examples thereof will be described in detail with reference to Figure 7C and Figure 7D Examples thereof will be described in detail.

[0049] RPT3 224 can receive a first corrected clock signal I_CLK_cr, a second corrected clock signal Q_CLK_cr, a third corrected clock signal IB_CLK_cr, and a fourth corrected clock signal QB_CLK_cr from RPT2 223_5, and provide the first corrected clock signal I_CLK_cr, the second corrected clock signal Q_CLK_cr, the third corrected clock signal IB_CLK_cr, and the fourth corrected clock signal QB_CLK_cr to the driver 225. In some embodiments, the corrected clock signals provided to the driver 225 may be in the form of a first output clock signal I_CLK_out, a second output clock signal Q_CLK_out, a third output clock signal IB_CLK_out, and a fourth output clock signal QB_CLK_out. This may reflect that the first corrected clock signal I_CLK_cr, the second corrected clock signal Q_CLK_cr, the third corrected clock signal IB_CLK_cr, and the fourth corrected clock signal QB_CLK_cr are distorted when passing through the clock path. However, because the clock compensation loop circuit 223 performs correction on the clock signals considering this distortion, the driver 225 can output a data signal DQ including read data RDT stored in the memory cell array 210 by performing a read operation based on the clock signals all having minimal errors according to precise timing.

[0050] In some embodiments, it may be assumed that the data signal DQ includes a first data signal and a second data signal, and the first data signal includes first reference data to fourth reference data. The memory controller 100 can control the second correction circuit 223_2 through an offset control signal CTRL_os based on the degree of distortion of the first reference data to fourth reference data included in the first data signal, to adjust the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK for reading the second data signal. In this case, the degree of distortion of the first reference data to fourth reference data can be determined by comparing the magnitude of each reference data with a reference unit interval (UI). As used herein, the reference UI may correspond to half of the period of the first reference clock signal CLK_ref or the second reference clock signal CLKB_ref. For example, the reference UI may correspond to Figure 3 and Figure 4 the second period ΔTP2 shown.

[0051] In some embodiments, the memory controller 100 may not adjust the phase of the first clock signal I_CLK. In other words, the second correction circuit 223_2 may generate a first offset clock signal I_CLK_os having the same phase as the first clock signal I_CLK according to the offset control signal CTRL_os received from the memory controller 100. This is because the first clock signal I_CLK may be a reference point for other remaining clock signals.

[0052] In some embodiments, the memory controller 100 may control the second correction circuit 223_2 to generate a second offset clock signal Q_CLK_os, a third offset clock signal IB_CLK_os, and a fourth offset clock signal QB_CLK_os based on the comparison results of the magnitudes of each of the first reference data to the fourth reference data with the reference UI. Details will be provided. Figures 7A to 7E Provide its detailed description.

[0053] Figure 6 is a timing diagram showing an example of data output according to a clock signal of a storage device according to some embodiments. It can be referred to Figures 1 to 5 for Figure 6 description, and redundant descriptions can be omitted.

[0054] In Figure 6 , the storage device 200 outputs a data signal DQ including first data D1 to eighth data D8 based on the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK. The magnitude of each of the first data D1 to the eighth data D8 may correspond to a second time period ΔTP2. That is, the magnitude of each of the first data D1 to the eighth data D8 may correspond to the reference UI. In Figure 6 , a total of eight data including the first data D1 to the eighth data D8 are only illustrated as examples and are not intended to limit the present disclosure.

[0055] The driver 225 may output the first data D1 from the first time point t1 to the second time point t2. The first time point t1 may be the time point at which the rising edge of the first clock signal I_CLK appears, and the second time point t2 may be the time point at which the rising edge of the second clock signal Q_CLK appears.

[0056] The driver 225 may output the second data D2 from the second time point t2 to the third time point t3. The second time point t2 may be the time point at which the rising edge of the second clock signal Q_CLK appears, and the third time point t3 may be the time point at which the rising edge of the third clock signal IB_CLK appears.

[0057] Driver 225 outputs third data D3 from the third time point t3 to the fourth time point t4. The third time point t3 may be the time point at which the rising edge of the third clock signal IB_CLK occurs, and the fourth time point t4 may be the time point at which the rising edge of the fourth clock signal QB_CLK occurs.

[0058] Driver 225 may output fourth data D4 from the fourth time point t4 to the fifth time point t5. The fourth time point t4 may be the time point at which the rising edge of the fourth clock signal QB_CLK occurs, and the fifth time point t5 may be the time point at which the rising edge of the first clock signal I_CLK occurs.

[0059] Driver 225 may output fifth data D5 from the fifth time point t5 to the sixth time point t6. The fifth time point t5 may be the time point at which the rising edge of the first clock signal I_CLK occurs, and the sixth time point t6 may be the time point at which the rising edge of the second clock signal Q_CLK occurs.

[0060] Driver 225 may output sixth data D6 from the sixth time point t6 to the seventh time point t7. The sixth time point t6 may be the time point at which the rising edge of the second clock signal Q_CLK occurs, and the seventh time point t7 may be the time point at which the rising edge of the third clock signal IB_CLK occurs.

[0061] Driver 225 may output seventh data D7 from the seventh time point t7 to the eighth time point t8. The seventh time point t7 may be the time point at which the rising edge of the third clock signal IB_CLK occurs, and the eighth time point t8 may be the time point at which the rising edge of the fourth clock signal QB_CLK occurs.

[0062] Driver 225 may output eighth data D8 from the eighth time point t8 to the ninth time point t9. The eighth time point t8 may be the time point at which the rising edge of the fourth clock signal QB_CLK occurs, and the ninth time point t9 may be the time point at which the rising edge of the first clock signal I_CLK occurs.

[0063] As described above, the timing for reading the first data D1 to the eighth data D8 from the first time point t1 to the ninth time point t9 has been described. Figure 6 The process of reading data in the case where the phases of the clock signals are ideal is shown. When an error occurs in the phases of the clock signals, it may be necessary to correct the phases of the clock signals with errors until the clock signals are provided to driver 225 along the clock path. When an error occurs as described above, the magnitude of each of the first data D1 to the eighth data D8 may not be constant. This will be described below with reference to Figures 7A to 7E is described.

[0064] Figures 7A to 7EIt is a timing diagram showing an example of a storage device that corrects a clock signal according to some embodiments. Reference can be made to Figures 1 to 6 for Figures 7A to 7E description, and redundant descriptions can be omitted.

[0065] In Figure 7A , the first output clock signal I_CLK_out, the second output clock signal Q_CLK_out, the third output clock signal IB_CLK_out, and the fourth output clock signal QB_CLK_out received by the driver 225 are shown.

[0066] The driver 225 can receive the first correction clock signal I_CLK_cr, the second correction clock signal Q_CLK_cr, the third correction clock signal IB_CLK_cr, and the fourth correction clock signal QB_CLK_cr from the first correction circuit 223_1 and perform a read operation based on these signals. When there is no error in the process of sending the clock signal to the driver 225, the forms of the first correction clock signal I_CLK_cr, the second correction clock signal Q_CLK_cr, the third correction clock signal IB_CLK_cr, and the fourth correction clock signal QB_CLK_cr received by the driver 225 from the first correction circuit 223_1 can be the same as Figure 6 the ideal form of the clock signal shown in. However, when an error occurs in the process of providing the clock signal to the driver 225 along the clock path, the clock signals received by the driver 225 can include the first output clock signal I_CLK_out, the second output clock signal Q_CLK_out, the third output clock signal IB_CLK_out, and the fourth output clock signal QB_CLK_out, which are different from the first correction clock signal I_CLK_cr, the second correction clock signal Q_CLK_cr, the third correction clock signal IB_CLK_cr, and the fourth correction clock signal QB_CLK_cr. In Figure 7A , for the sake of description, it is assumed that the error occurs in relation to the second output clock signal Q_CLK_out. That is, it is assumed that the time point at which the logic level of the second output clock signal Q_CLK_out transitions to the high level does not occur at the second time point t2a, but occurs at a time point advanced by the second time period ΔT2 from the second time point t2a. This is only an example for explanation and is not intended to limit the present disclosure.

[0067] In some embodiments, the driver 225 may operate based on the first output clock signal I_CLK_out, the second output clock signal Q_CLK_out, the third output clock signal IB_CLK_out, and the fourth output clock signal QB_CLK_out. The driver 225 may output a first data signal DQ1 from the memory cell array 210 to the memory controller 100. The first data signal DQ1 includes first reference data RD1 to eighth reference data RD8. In this case, since the phase of the second output clock signal Q_CLK_out is advanced by a second time period ΔT2, the magnitude of the first reference data RD1 may be less than the reference UI, and the magnitude of the second reference data RD2 may be greater than the reference UI. Similarly, the magnitude of the fifth reference data RD5 may be less than the reference UI, and the magnitude of the sixth reference data RD6 may be greater than the reference UI. The memory controller 100 may receive the first data signal DQ1 from the memory device 200. Since the magnitudes of the first reference data RD1, the second reference data RD2, the fifth reference data RD5, and the sixth reference data RD6 among the multiple data included in the first data signal DQ1 do not match the reference UI, the memory controller 100 may determine that the second clock signal Q_CLK needs to be corrected.

[0068] In Figure 7B , the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK provided to the second correction circuit 223_2 are shown.

[0069] In Figure 7C , the first offset clock signal I_CLK_os, the second offset clock signal Q_CLK_os, the third offset clock signal IB_CLK_os, and the fourth offset clock signal QB_CLK_os output from the second correction circuit 223_2 are shown. By adjusting Figure 7B the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK shown, the second correction circuit 223_2 may generate the first offset clock signal I_CLK_os, the second offset clock signal Q_CLK_os, the third offset clock signal IB_CLK_os, and the fourth offset clock signal QB_CLK_os. The second correction circuit 223_2 may output the offset clock signal in response to the offset control signal CTRL_os received from the memory controller 100.

[0070] In some embodiments, since the memory controller 100 has determined that the second clock signal Q_CLK needs to be corrected based on the first data signal DQ1, the memory controller 100 may provide an offset control signal CTRL_os for adjusting the offset of the second clock signal Q_CLK to the second correction circuit 223_2. Contrary to the assumption in Figure 7A , when the memory controller 100 has determined that the third clock signal IB_CLK needs to be corrected based on the first data signal DQ1, the memory controller 100 may provide an offset control signal CTRL_os for adjusting the offset of the third clock signal IB_CLK to the second correction circuit 223_2. Similarly, when the memory controller 100 has determined that the fourth clock signal QB_CLK needs to be corrected based on the first data signal DQ1, the memory controller 100 may provide an offset control signal CTRL_os for adjusting the offset of the fourth clock signal QB_CLK to the second correction circuit 223_2.

[0071] In some embodiments, as Figure 7A illustrates, when the size of the first reference data is less than the reference UI, the memory controller 100 may control the second correction circuit 223_2 to generate a second offset clock signal Q_CLK_os by advancing the phase of the second clock signal Q_CLK by an offset amount. In this case, the size of the offset amount may correspond to the difference between the length of the reference UI and the length of the UI of the first reference data. For example, the size of the offset amount may correspond to the second time period ΔT2.

[0072] In some embodiments, when assuming a situation contrary to the situation illustrated in Figure 7A , that is, when the size of the first reference data is greater than the reference UI, the memory controller 100 may control the second correction circuit 223_2 to generate a second offset clock signal Q_CLK_os by delaying the phase of the second clock signal Q_CLK by an offset amount. In this case, the size of the offset amount may correspond to the difference between the length of the UI of the first reference data and the length of the reference UI. For example, the size of the offset amount may correspond to the second time period ΔT2.

[0073] In Figure 7D , the first correction clock signal I_CLK_cr, the second correction clock signal Q_CLK_cr, the third correction clock signal IB_CLK_cr, and the fourth correction clock signal QB_CLK_cr are illustrated.

[0074] The control circuit 223_3 can receive a second offset clock signal Q_CLK_os with a phase advanced by a second time period ΔT2 from the second correction circuit 223_2. In this case, the control circuit 223_3 can generate a correction control signal CTRL_cr that delays the phase of the second clock signal Q_CLK by the second time period ΔT2 to correct the second clock signal Q_CLK. The control circuit 223_3 can provide the correction control signal CTRL_cr to the first correction circuit 223_1.

[0075] In response to the correction control signal CTRL_cr from the control circuit 223_3, the first correction circuit 223_1 can output a first corrected clock signal I_CLK_cr, a second corrected clock signal Q_CLK_cr, a third corrected clock signal IB_CLK_cr, and a fourth corrected clock signal QB_CLK_cr. The first corrected clock signal I_CLK_cr, the second corrected clock signal Q_CLK_cr, the third corrected clock signal IB_CLK_cr, and the fourth corrected clock signal QB_CLK_cr can be provided to the driver 225 through RPT2 223_5 and RPT3 224.

[0076] In Figure 7E it shows a first output clock signal I_CLK_out, a second output clock signal Q_CLK_out, a third output clock signal IB_CLK_out, and a fourth output clock signal QB_CLK_out, where the correction value is reflected based on the first corrected clock signal I_CLK_cr, the second corrected clock signal Q_CLK_cr, the third corrected clock signal IB_CLK_cr, and the fourth corrected clock signal QB_CLK_cr.

[0077] In some embodiments, based on Figure 7E the shown first output clock signal I_CLK_out, second output clock signal Q_CLK_out, third output clock signal IB_CLK_out, and fourth output clock signal QB_CLK_out, the driver 225 can convert the clock signal into a first recovered clock signal I_CLK_rec, a second recovered clock signal Q_CLK_rec, a third recovered clock signal IB_CLK_rec, and a fourth recovered clock signal QB_CLK_rec. The pulse width of each of the first recovered clock signal I_CLK_rec, the second recovered clock signal Q_CLK_rec, the third recovered clock signal IB_CLK_rec, and the fourth recovered clock signal QB_CLK_rec can correspond to the second period ΔTP2.

[0078] In some embodiments, the driver 225 may output a second data signal DQ2 by reading data from the memory cell array 210 based on a first recovered clock signal I_CLK_rec, a second recovered clock signal Q_CLK_rec, a third recovered clock signal IB_CLK_rec, and a fourth recovered clock signal QB_CLK_rec. The second data signal DQ2 may include first data D1 to eighth data D8. In this case, the sizes of the first data D1 to the eighth data D8 included in the second data signal DQ2 may be constant.

[0079] Figure 8 is a flowchart illustrating an example of an operation method of a memory device according to some embodiments. Reference may be made to Figures 1 to 7E for Figure 8 description, and redundant descriptions may be omitted.

[0080] In Figure 8 operation S110, the memory device 200 may generate a first clock signal I_CLK, a second clock signal Q_CLK, a third clock signal IB_CLK, and a fourth clock signal QB_CLK based on a first reference clock signal CLK_ref and a second reference clock signal CLKB_ref received from the memory controller 100.

[0081] In some embodiments, the period of each of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK may correspond to twice the period of one of the first reference clock signal CLK_ref and the second reference clock signal CLKB_ref.

[0082] In some embodiments, the phase difference between the second clock signal Q_CLK and the first clock signal I_CLK may be 90 degrees. The phase difference between the third clock signal IB_CLK and the first clock signal I_CLK may be 180 degrees. The phase difference between the fourth clock signal QB_CLK and the first clock signal I_CLK may be 270 degrees.

[0083] In operation S120, the memory device 200 may generate a first offset clock signal I_CLK_os, a second offset clock signal Q_CLK_os, a third offset clock signal IB_CLK_os, and a fourth offset clock signal QB_CLK_os based on the magnitude of each of the first reference data RD1 to the fourth reference data RD4 included in the first data signal DQ1. Specifically, the memory controller 100 may receive the first data signal DQ1 from the memory device 200 and provide an offset control signal CTRL_os generated based on the magnitude of the first reference data RD1 to the fourth reference data RD4 included in the first data signal DQ1 to the memory device 200. In response to the offset control signal CTRL_os, the memory device 200 may adjust the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK through the second correction circuit 223_2.

[0084] In some embodiments, when the magnitude of the first reference data RD1 is less than the reference UI, the memory device 200 may generate the second offset clock signal Q_CLK_os by advancing the phase of the second clock signal Q_CLK by an offset amount. In this case, the magnitude of the offset amount may correspond to the difference between the reference UI and the magnitude of the first reference data RD1.

[0085] In some embodiments, when the magnitude of the first reference data RD1 is greater than the reference UI, the memory device 200 may generate the second offset clock signal Q_CLK_os by delaying the phase of the second clock signal Q_CLK by an offset amount. In this case, the magnitude of the offset amount may correspond to the difference between the magnitude of the first reference data RD1 and the magnitude of the reference UI.

[0086] In operation S130, the memory device 200 may adjust the phases of the first clock signal I_CLK, the second clock signal Q_CLK, the third clock signal IB_CLK, and the fourth clock signal QB_CLK based on the first offset clock signal I_CLK_os, the second offset clock signal Q_CLK_os, the third offset clock signal IB_CLK_os, and the fourth offset clock signal QB_CLK_os. The memory device 200 may generate a first corrected clock signal I_CLK_cr, a second corrected clock signal Q_CLK_cr, a third corrected clock signal IB_CLK_cr, and a fourth corrected clock signal QB_CLK_cr, which are clock signals with adjusted phases.

[0087] In operation S140, the memory device 200 may output a second data signal DQ2 including first data D1 to fourth data D4 based on a first correction clock signal I_CLK_cr, a second correction clock signal Q_CLK_cr, a third correction clock signal IB_CLK_cr, and a fourth correction clock signal QB_CLK_cr.

[0088] Figure 9 is a block diagram of an example of a system of an electronic device including a memory device according to some embodiments. In Figure 9 the system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memories 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (AP) 1800. The system 1000 may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system 1000 may be implemented as a server or a PC.

[0089] The camera 1100 may capture a still image or record a video under user control and may store the obtained image / video data or send the image / video data to the display 1200. The audio processor 1300 may process audio data or network content included in the flash memories 1600a and 1600b. The modem 1400 may modulate and transmit signals for wired / wireless data transmission and reception, and at the receiving end, the signals may be demodulated and restored to the original signals. The I / O devices 1700a and 1700b may include devices providing digital input and / or output functions, such as, a universal serial bus (USB) or a memory, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, and a touch screen.

[0090] The AP 1800 can control all operations of the system 1000. The AP 1800 can include a controller 1810, an accelerator 1820, and an interface 1830. The AP 1800 can control the display 1200 to display some of the content stored in the flash memories 1600a and 1600b on the display 1200. When user inputs are received through the I / O devices 1700a and 1700b, the AP 1800 can perform control operations corresponding to the user inputs. The AP 1800 can include an accelerator block as a dedicated circuit for artificial intelligence (AI) data operations, or can include an accelerator 1820 separate from the AP 1800. A DRAM 1500b can be additionally installed on the accelerator 1820. The accelerator is a functional block that specifically executes a particular function of the AP 1800, and the accelerator can include a graphics processing unit (GPU) (a functional block dedicated to graphics data processing), a neural processing unit (NPU) (a block dedicated to AI computing and inference), and a data processing unit (DPU) (a block dedicated to data transfer).

[0091] The system 1000 can include multiple DRAMs 1500a and 1500b. The AP 1800 can perform communication by setting a DRAM interface protocol to control the DRAMs 1500a and 1500b through commands and mode register (MRS) settings compliant with the Joint Electron Device Engineering Council (JEDEC) standards, or perform company-specific functions such as low voltage, high speed, and reliability, as well as cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 can communicate with the DRAM 1500a through a JEDEC-standard compliant interface (such as LPDDR4 and / or LPDDR5), and the accelerator 1820 can perform communication by setting a new DRAM interface protocol to control the accelerator DRAM 1500b with a bandwidth higher than that of the DRAM 1500a.

[0092] Although Figure 9Only DRAM 1500a and 1500b may be shown, but the present disclosure is not limited thereto. Any memory such as phase change RAM (PRAM), static RAM (SRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), or hybrid RAM may be used as long as the bandwidth, response speed, and voltage conditions of AP 1800 or accelerator 1820 are satisfied. Compared with the latency and bandwidth of I / O devices 1700a and 1700b or flash memories 1600a and 1600b, the latency and bandwidth of DRAM 1500a and 1500b are relatively small. DRAM 1500a and 1500b may be initialized when the system 1000 is powered on, and when the operating system and application data are loaded, DRAM 1500a and 1500b may be used as a temporary storage location for the operating system and application data or as an execution space for various software codes.

[0093] Four basic arithmetic operations including addition, subtraction, multiplication, and division, vector operations, address operations, or fast Fourier transform (FFT) operations may be executed in DRAM 1500a and 1500b. In addition, the execution function for inference may be executed in DRAM 1500a and 1500b. In this case, an artificial neural network may be used for inference in a deep learning algorithm. The deep learning algorithm may include a training operation of learning a model through various data and an inference operation of identifying data using the trained model. In some embodiments, an image captured by the user using the camera 1100 may be signal-processed and stored in DRAM 1500b, and the accelerator 1820 may identify data by performing AI data operations using the data stored in DRAM 1500b and a function for inference.

[0094] The system 1000 may include multiple flash memories 1600a and 1600b or multiple storage devices having a larger capacity than DRAM 1500a and 1500b. The accelerator 1820 may perform training operations and AI data operations by using the flash memories 1600a and 1600b. In some embodiments, each of the flash memories 1600a and 1600b may include a memory controller 1610 and a flash memory 1620, and the training operations and inference AI data operations performed by the AP 1800 and / or the accelerator 1820 may be executed more efficiently by using the computing devices provided in the memory controller 1610. The flash memories 1600a and 1600b may store photos captured by the camera 1100 or data transmitted through a data network. For example, augmented reality / virtual reality, high definition (HD), or ultra-high definition (UHD) content may be stored.

[0095] While this disclosure contains many specific implementation details, these details should not be construed as limiting the scope of the claims. The specific features described in the context of separate embodiments of this disclosure can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although features may be described above as acting in certain combinations, in some cases, one or more features from a combination can be deleted from that combination, and the combination can be directed to a sub-combination or a variant of the sub-combination.

Claims

1. A storage device, the storage device comprising: A memory cell array that stores a plurality of data; A first correction circuit configured to: receive a plurality of clock signals and a control signal, adjust the phases of the plurality of clock signals based on the control signal, and output a plurality of corrected clock signals; A second correction circuit configured to: receive the plurality of clock signals through the first correction circuit, adjust the phases of the plurality of clock signals based on the magnitude of each of a plurality of reference data included in a first data signal, and output a plurality of offset clock signals; A control circuit configured to: generate the control signal based on the plurality of offset clock signals received from the second correction circuit; And A driver configured to: output a second data signal including the plurality of data read from the memory cell array based on the plurality of corrected clock signals received from the first correction circuit.

2. The storage device according to claim 1, the storage device further comprising: A clock buffer circuit configured to: receive a first reference clock signal and a second reference clock signal, generate a first input clock signal and a third input clock signal based on the first reference clock signal, the period of each of the first input clock signal and the third input clock signal being longer than the period of the first reference clock signal, and generate a second input clock signal and a fourth input clock signal based on the second reference clock signal, the period of each of the second input clock signal and the fourth input clock signal being longer than the period of the second reference clock signal; And A delay locked loop circuit configured to: delay the phases of each of the first input clock signal, the second input clock signal, the third input clock signal, and the fourth input clock signal by an equal time period, and provide the delayed first input clock signal, the delayed second input clock signal, the delayed third input clock signal, and the delayed fourth input clock signal to the first correction circuit as the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal.

3. The storage device according to claim 1, Among them, Among the plurality of corrected clock signals, the phase difference between the second corrected clock signal and the first corrected clock signal corresponds to 90 degrees, Wherein, among the plurality of corrected clock signals, the phase difference between the third corrected clock signal and the first corrected clock signal corresponds to 180 degrees, and Wherein, among the plurality of corrected clock signals, the phase difference between the fourth corrected clock signal and the first corrected clock signal corresponds to 270 degrees.

4. The storage device according to claim 1, wherein The driver is further configured to: Read the first data among the plurality of data from the rising edge of the first corrected clock signal among the plurality of corrected clock signals to the rising edge of the second corrected clock signal among the plurality of corrected clock signals, Read the second data among the multiple data from the rising edge of the second correction clock signal to the rising edge of the third correction clock signal among the multiple correction clock signals. Read the third data among the multiple data from the rising edge of the third correction clock signal to the rising edge of the fourth correction clock signal among the multiple correction clock signals, and Read the fourth data among the multiple data from the rising edge of the fourth correction clock signal to the rising edge of the first correction clock signal.

5. The memory device according to claim 1, wherein, The second correction circuit is further configured to generate a first offset clock signal among the multiple offset clock signals, and the first offset clock signal has the same phase as the first clock signal among the multiple clock signals.

6. The storage device according to claim 1, Among them, The second correction circuit is further configured to: based on the size of the first reference data among the multiple reference data being less than a reference unit interval, generate a second offset clock signal among the multiple offset clock signals by advancing the phase of the second clock signal among the multiple clock signals by an offset amount, and provide the generated second offset clock signal to the control circuit, wherein the size of the offset amount corresponds to the difference between the reference unit interval and the size of the first reference data.

7. The storage device according to claim 1, Among them, The second correction circuit is further configured to: based on the size of the first reference data among the multiple reference data being greater than the reference unit interval, generate a second offset clock signal among the multiple offset clock signals by delaying the phase of the second clock signal among the multiple clock signals by an offset amount, and provide the generated second offset clock signal to the control circuit, wherein the size of the offset amount corresponds to the difference between the size of the first reference data and the reference unit interval.

8. The storage device according to claim 1, the storage device further includes: A first repeater configured to provide the multiple clock signals from the first correction circuit to the second correction circuit; and A second repeater configured to provide the multiple correction clock signals from the first correction circuit to the driver.

9. An operation method of a storage device, the operation method includes: Generate multiple clock signals based on a first reference clock signal and a second reference clock signal; Generate multiple offset clock signals based on the size of each of the multiple reference data included in the first data signal; Generate multiple correction clock signals by adjusting the phases of the multiple clock signals based on the multiple offset clock signals; and and Output a second data signal including data stored in the storage device based on the multiple correction clock signals.

10. The operating method according to claim 9, wherein, Generating the multiple clock signals includes: Based on the first reference clock signal, generate the first clock signal among the multiple clock signals and the third clock signal among the multiple clock signals, and the period of each of the first clock signal and the third clock signal is longer than the period of the first reference clock signal; and Based on the two reference clock signals, generate a second clock signal among the multiple clock signals and a fourth clock signal among the multiple clock signals, wherein the period of each of the second clock signal and the fourth clock signal is longer than the period of the second reference clock signal.

11. The operation method according to claim 9, wherein the operation method further comprises reading a plurality of data stored in the storage device, Among them, The reading comprises: Reading a first data among the plurality of data from a rising edge of a first calibration clock signal among the plurality of calibration clock signals to a rising edge of a second calibration clock signal among the plurality of calibration clock signals; Reading a second data among the plurality of data from the rising edge of the second calibration clock signal to a rising edge of a third calibration clock signal among the plurality of calibration clock signals; Reading a third data among the plurality of data from the rising edge of the third calibration clock signal to a rising edge of a fourth calibration clock signal among the plurality of calibration clock signals; and Reading a fourth data among the plurality of data from the rising edge of the fourth calibration clock signal to the rising edge of the first calibration clock signal.

12. The operating method according to claim 9, wherein, Generating the plurality of offset clock signals includes: generating a first offset clock signal having the same phase as a first clock signal among the plurality of clock signals.

13. The operating method according to claim 9, wherein, Generating the plurality of offset clock signals includes: Comparing the magnitude of a first reference data with a reference unit interval; Based on the magnitude of the first reference data being less than the magnitude of the reference unit interval, advancing the phase of a second clock signal among the plurality of clock signals by an offset amount corresponding to a difference between the reference unit interval and the magnitude of the first reference data; and Generating a second offset clock signal with the phase of the second clock signal among the plurality of offset clock signals advanced.

14. The operating method according to claim 9, wherein, Generating the plurality of offset clock signals includes: Comparing the magnitude of a first reference data with a reference unit interval; Based on the magnitude of the first reference data being greater than the magnitude of the reference unit interval, delaying the phase of a second clock signal among the plurality of clock signals by an offset amount corresponding to a difference between the magnitude of the first reference data and the reference unit interval; and Generating a second offset clock signal with the phase of the second clock signal among the plurality of offset clock signals delayed.

15. A memory system, the memory system comprising: A memory controller configured to generate a first reference clock signal, a second reference clock signal, and a first control signal; And A storage device configured to provide a first data signal and a second data signal to the memory controller, Wherein, the storage device includes: A memory cell array configured to store a plurality of data; A clock buffer circuit configured to generate a plurality of clock signals based on the first reference clock signal and the second reference clock signal; A first correction circuit configured to receive the plurality of clock signals and a second control signal, adjust phases of the plurality of clock signals based on the second control signal, and output a plurality of corrected clock signals; A second correction circuit configured to receive the plurality of clock signals through the first correction circuit, adjust phases of the plurality of clock signals based on a first control signal, and output a plurality of offset clock signals; A control circuit configured to generate the second control signal based on the plurality of offset clock signals received from the second correction circuit; and A driver configured to output the second data signal including the plurality of data read from the memory cell array based on the plurality of corrected clock signals received from the first correction circuit, and wherein the memory controller is further configured to generate the first control signal to adjust phases of the plurality of clock signals based on a magnitude of each of the plurality of reference data included in the first data signal.

16. The memory system according to claim 15, Among them, Among the plurality of corrected clock signals, a phase difference between a second corrected clock signal and a first corrected clock signal corresponds to 90 degrees, wherein, among the plurality of corrected clock signals, a phase difference between a third corrected clock signal and the first corrected clock signal corresponds to 180 degrees, and wherein, among the plurality of corrected clock signals, a phase difference between a fourth corrected clock signal and the first corrected clock signal corresponds to 270 degrees.

17. The memory system according to claim 15, wherein, The memory device is further configured to: Read first data among the plurality of data from a rising edge of the first corrected clock signal among the plurality of corrected clock signals to a rising edge of the second corrected clock signal among the plurality of corrected clock signals, Read second data among the plurality of data from the rising edge of the second corrected clock signal to a rising edge of the third corrected clock signal among the plurality of corrected clock signals, Read third data among the plurality of data from the rising edge of the third corrected clock signal to a rising edge of the fourth corrected clock signal among the plurality of corrected clock signals, and Read fourth data among the plurality of data from the rising edge of the fourth corrected clock signal to the rising edge of the first corrected clock signal.

18. The memory system according to claim 15, wherein, The second correction circuit is further configured to generate a first offset clock signal among the plurality of offset clock signals, the first offset clock signal having the same phase as a first clock signal among the plurality of clock signals.

19. The memory system according to claim 15, wherein, The second correction circuit is further configured to: generate a second offset clock signal among the plurality of offset clock signals by advancing a phase of a second clock signal among the plurality of clock signals by an offset amount based on a magnitude of a first reference data among the plurality of reference data being less than a reference unit interval, and provide the generated second offset clock signal to the control circuit, wherein a magnitude of the offset amount corresponds to a difference between the reference unit interval and the magnitude of the first reference data.

20. The memory system according to claim 15, wherein, The second correction circuit is further configured to: based on that the magnitude of the first reference data among the plurality of reference data is greater than the reference unit interval, generate a second offset clock signal among the plurality of offset clock signals by delaying the phase offset of the second clock signal among the plurality of clock signals, and provide the generated second offset clock signal to the control circuit, wherein the magnitude of the offset corresponds to the difference between the magnitude of the first reference data and the reference unit interval.

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