A load switch and control method integrating bidirectional current limiting protection and overcurrent protection.

Abstract

This invention discloses a load switch and control method integrating bidirectional current limiting protection and overcurrent protection. It includes a high-voltage selector, a charge pump, a driver, a power transistor unit, a current limiting sampling unit, and an overcurrent protection unit. The two input terminals of the high-voltage selector are connected to input signals VA and VB, respectively. The output terminal of the high-voltage selector is connected to the input terminal of the charge pump. The output terminal of the charge pump is connected to the input terminal of the driver and generates a signal VCP. The output terminal of the driver is connected to the input terminal of the power transistor unit and the first input terminal of the current limiting sampling unit. The output terminal of the power transistor is connected to the second input terminal of the current limiting sampling unit and generates a signal V2. The output terminal of the overcurrent protection unit is connected to the first control terminal of the driver, and the output terminal of the current limiting sampling unit is connected to the second control terminal of the driver. This invention facilitates current control while the external port is bidirectionally conducting, achieving bidirectional current limiting protection and overcurrent protection for the load switch.

Description

Technical Field

[0001] This invention relates to a load switch and control method, particularly a load switch and control method integrating bidirectional current limiting protection and overcurrent protection, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In complex external power systems, USB-compatible power delivery systems are particularly important. Load switch chips are used to connect and isolate power rails, typically exhibiting unidirectional conduction. In practical applications, the electrical equipment connected to the load switch is often complex and prone to overcurrent and short circuits. Therefore, the chip usually incorporates current limiting and overcurrent protection modules. When the load switch chip experiences an output short circuit or the load current exceeds a specified value upon power-up, current limiting protection is implemented to limit the chip's startup current. During normal operation, if the load current exceeds a specified value, overcurrent protection is implemented to prevent excessive current from damaging downstream circuitry. In certain applications, such as smart grids, existing load switches cannot achieve bidirectional conduction and current limiting, resulting in poor adaptability. Therefore, load switches with bidirectional current limiting and overcurrent protection are required.

[0003] Traditional load switches limit the output current to ensure that external circuits do not draw excessive current, maintaining the normal operation of the load switch system. In current-limiting mode, the load switch provides continuous current until the switching current drops below the current limit. When the load current exceeds the rated value, the load switch quickly disconnects the circuit to prevent sensitive components from burning out due to overcurrent. In the switching path, the input and output electrical ports are strictly limited; the load switch can only control the unidirectional flow of current and has unidirectional current-limiting and overcurrent protection functions, thus losing its competitiveness in the bidirectional current control market. In short, existing load switch technology is only applicable to unidirectional power supply systems, resulting in significant application limitations. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a load switch and control method that integrates bidirectional current limiting protection and overcurrent protection, so as to realize bidirectional current limiting protection and bidirectional overcurrent protection of the load switch.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A load switch integrating bidirectional current limiting protection and overcurrent protection includes a high-voltage selector, a charge pump, a driver, a power transistor unit, a current limiting sampling unit, and an overcurrent protection unit. The first input terminal of the high-voltage selector is connected to the input signal VA, and the second input terminal of the high-voltage selector is connected to the input signal VB. The output terminal of the high-voltage selector is connected to the input terminal of the charge pump, and the output terminal of the charge pump is connected to the input terminal of the driver and generates a signal VCP. The output terminal of the driver is connected to the input terminal of the power transistor unit and the first input terminal of the current limiting sampling unit. The output terminal of the power transistor is connected to the second input terminal of the current limiting sampling unit and generates a signal V2. The output terminal of the overcurrent protection unit is connected to the first control terminal of the driver, and the output terminal of the current limiting sampling unit is connected to the second control terminal of the driver.

[0007] Furthermore, the power transistor unit includes an NMOS transistor M0 and an NMOS transistor M1. The drain of the NMOS transistor M0 is connected to the input signal VA. The gate of the NMOS transistor M0 is connected to the gate of the NMOS transistor M1 and serves as the input terminal of the power transistor unit. The source of the NMOS transistor M0 is connected to the source of the NMOS transistor M1 and serves as the output terminal of the power transistor unit to generate the signal V2. The drain of the NMOS transistor M1 is connected to the signal VB.

[0008] Further, the current-limiting sampling unit includes NMOS transistors M2, M3, M4, M5, and M6, error amplifiers EA1, EA2, and EA3, and resistor R0. The drain of NMOS transistor M2 is connected to signal V4. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M5 and serves as the first input terminal of the current-limiting sampling unit. The source of NMOS transistor M2 is connected to the drain of NMOS transistor M3 and the first input terminal of error amplifier EA1 to generate signal V1. The second input terminal of error amplifier EA1 is connected to the first input terminal of error amplifier EA2 and serves as the second input terminal of the current-limiting sampling unit. The output terminal of error amplifier EA1... The gate of NMOS transistor M3 is connected to the gate of NMOS transistor M4. The source of NMOS transistor M3 is connected to the source of NMOS transistor M4, one end of resistor R0, and the first input terminal of error amplifier EA3. The gate of NMOS transistor M4 is connected to the output terminal of error amplifier EA2. The drain of NMOS transistor M4 is connected to the second input terminal of error amplifier EA2 and the source of PMOS transistor PM5 to generate signal V3. The drain of NMOS transistor M5 is connected to signal V6. The other end of resistor R0 is grounded. The second input terminal of error amplifier EA3 is connected to the reference voltage VREF. The output terminal of error amplifier EA3 is connected to the gate of NMOS transistor M6. The drain of NMOS transistor M6 serves as the output terminal of the current-limiting sampling unit. The source of NMOS transistor M6 is grounded.

[0009] Furthermore, the reference voltage VREF is generated by a bandgap reference source.

[0010] Furthermore, the overcurrent protection unit includes a common-gate comparator CGC1, a common-gate comparator CGC2, an OR gate, resistors R1, R2, R3, and R4. The first input terminal of the common-gate comparator CGC1 is connected to signal V4, and the second input terminal of the common-gate comparator CGC1 is connected to signal V5. The first input terminal of the common-gate comparator CGC2 is connected to signal V6, and the second input terminal of the common-gate comparator CGC2 is connected to signal V7. The output terminal of the common-gate comparator CGC1 is connected to the first input terminal of the OR gate, and the output terminal of the common-gate comparator CGC2 is connected to the second input terminal of the OR gate. The output terminal of the OR gate serves as the output terminal of the overcurrent protection unit. One end of resistor R1 is connected to one end of resistor R2 and is connected to the input signal VA. The other end of resistor R1 generates signal V4, and the other end of resistor R2 generates signal V5. One end of resistor R3 is connected to one end of resistor R4 and is connected to the input signal VB. The other end of resistor R3 generates signal V6, and the other end of resistor R4 generates signal V7.

[0011] Furthermore, the common-gate comparators CGC1 and CGC2 respectively include resistors R5 and R6, PMOS transistors M7 and M8, current source I3 and current source I4. One end of resistor R5 is connected to one end of resistor R6 and is connected to signal VA. The other end of resistor R5 is connected to the source of PMOS transistor M7 and serves as the first input terminal of the common-gate comparator. The other end of resistor R6 is connected to the source of PMOS transistor M8 and serves as the second input terminal of the common-gate comparator. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8, the drain of PMOS transistor M7 is connected to one end of current source I3, and the drain of PMOS transistor M8 is connected to one end of current source I4 and serves as the output terminal of the common-gate comparator. The other ends of current source I3 and current source I4 are grounded.

[0012] A control method for a load switch integrating bidirectional current limiting protection and overcurrent protection includes the following steps:

[0013] The high-voltage selector compares the voltage magnitudes of input signals VA and VB and outputs the maximum value between VA and VB.

[0014] The charge pump boosts the output voltage of the high-voltage selector and outputs a signal VCP to drive the power transistor unit;

[0015] The driver controls the conduction state of the power transistor unit by controlling the gate voltage of NMOS transistors M0 and M1. When the load current of the load switch is within the current limit range, the driver controls NMOS transistors M0 and M1 to conduct. When the load current is greater than the current limit, the driver limits the gate voltage of NMOS transistors M0 and M1 to provide a constant current to the load until the load current drops to the current limit.

[0016] When the load current of the load switch is less than the current limit, the load switch is equivalent to a wire connected to the external circuit. When the load current is greater than the current limit, the load switch is equivalent to a current source providing a constant current to the external circuit. The power transistor unit adopts a back-to-back circuit connection of NMOS transistors M0 and M1, and the power transistor unit can operate in both directions.

[0017] A bandgap reference source generates a reference voltage VREF to set the threshold for current limiting detection;

[0018] Error amplifier EA3 controls the conduction state of NMOS transistor M6 by comparing the voltage generated by the sampling current of NMOS transistor M2 or NMOS transistor M5 flowing through resistor R0 with the reference voltage VREF, and controls the conduction state of NMOS transistors M0 and M1 through a driver; NMOS transistor M2, resistor R1, NMOS transistor M3 and error amplifier EA1 constitute the current sampling module for signal VB, and NMOS sampling transistor M5, resistor R3, NMOS transistor M4 and error amplifier EA2 constitute the current sampling module for signal VA;

[0019] When signal VB is connected to the load current and signal VA is connected to the power supply voltage, error amplifier EA1 and NMOS transistor M3 form a negative feedback loop, clamping signals V1 and V2. According to the MOSFET saturation current formula:

[0020]

[0021]

[0022] Where I0 is the current through NMOS transistor M0, and I2 is the sampling current flowing through NMOS transistor M2. It is the average mobility of electrons in the channel. is the gate oxide capacitance per unit area, W is the width of the transistor channel, and L is the length of the transistor channel. It is the width-to-length ratio of the NMOS transistor M0. It is the width-to-length ratio of NMOS transistor M2. It is the gate-source voltage of the transistor. It is the threshold voltage. It is the channel length modulation coefficient. It is the drain-source voltage of NMOS transistor M0. It is the drain-source voltage of NMOS transistor M2; when the resistance of resistor R1 is very small, the voltage drop across resistor R1 is ignored; the sampling current I2 is determined by the ratio of the width-to-length ratio of NMOS transistor M0 and NMOS transistor M2; the voltage generated by the sampling current I2 flowing into resistor R0 is compared with the reference voltage VREF through error amplifier EA3, and the driver is controlled by controlling the conduction state of NMOS optocoupler M6.

[0023] The load switch current limit value is equal to the current I0 and

[0024]

[0025] The current limiting value of the load switch is determined by modifying the width-to-length ratio of NMOS transistor M0, the width-to-length ratio of NMOS transistor M2, the reference voltage VREF, and the value of resistor R0.

[0026] When signal VA is connected to the load current and signal VB is connected to the power supply voltage, error amplifier EA2 and NMOS transistor M4 form a negative feedback loop to clamp signals V3 and V2. When the resistance of resistor R3 is very small, the voltage drop across resistor R3 is ignored. The sampling current of NMOS transistor M5 is determined by the ratio of the width-to-length ratio of the second N-type power MOS transistor M1 and the sampling transistor M5. The voltage generated by the sampling current of NMOS transistor M5 flowing into resistor R0 is compared with the reference voltage VREF by error amplifier EA3, and the driver is controlled by controlling the conduction state of NMOS transistor M6.

[0027] The load switch current limit value is equal to the current I1 and

[0028]

[0029] The current limiting value of the load switch is determined by modifying the width-to-length ratio of NMOS transistor M1, the width-to-length ratio of NMOS transistor M5, the reference voltage VREF, and the value of resistor R0.

[0030] The maximum overcurrent value IOCP of the overcurrent protection unit is expressed as:

[0031]

[0032] Because the current value of current source I3 is much smaller than the sampling current I2, the current flowing through resistor R1 is equivalent to the sampling current I2. Therefore, the current relationship of the common-gate comparator CGC1 is expressed as follows:

[0033]

[0034] Where I4 is the current value of current source I4;

[0035] The final maximum overcurrent value IOCP of the overcurrent protection unit is expressed as:

[0036]

[0037] The maximum overcurrent value IOCP is determined by modifying the values ​​of current source I4 and resistor R6.

[0038] In the common gate comparator CGC1, if the load current of signal VB exceeds the maximum overcurrent value IOCP, the current replicated by the power transistor unit flows through resistor R5, causing the voltage drop across resistor R5 to be greater than the voltage drop across resistor R6. The voltage value of signal V4 is less than the voltage value of signal V5, and the output port of the common gate comparator CGC1 generates an overcurrent protection high-level signal VOCP.

[0039] Similarly, in the common-gate comparator CGC2, if the load current of the signal VA exceeds the maximum overcurrent value IOCP, the output port of the common-gate comparator CGC2 generates an overcurrent protection high-level signal VOCP.

[0040] The overcurrent protection signals output by common-gate comparators CGC1 and CGC2 are superimposed in the overcurrent protection unit via an OR gate, and the overcurrent protection is achieved by controlling the switching of the power transistor unit using a driver.

[0041] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a load switch and control method that integrates bidirectional current limiting protection and overcurrent protection, which is beneficial for current control at the external port while it is conducting in both directions; the load switch uses NMOS power transistors placed back to back, the current limiting sampling unit is implemented by error amplifier negative feedback clamping, and the overcurrent protection unit is implemented by comparison through a common gate comparator. The forward and reverse load currents are processed by two sampling circuits respectively, which is suitable for scenarios that require bidirectional current flow. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a load switch integrating bidirectional current limiting protection and overcurrent protection according to the present invention.

[0043] Figure 2 This is a schematic diagram of the common-gate comparator of the present invention. Detailed Implementation

[0044] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0045] like Figure 1 As shown, a load switch integrating bidirectional current limiting protection and overcurrent protection according to the present invention includes a high-voltage selector, a charge pump, a driver, a power transistor unit, a current limiting sampling unit, and an overcurrent protection unit. The first input terminal of the high-voltage selector is connected to the input signal VA, the second input terminal of the high-voltage selector is connected to the input signal VB, the output terminal of the high-voltage selector is connected to the input terminal of the charge pump, the output terminal of the charge pump is connected to the input terminal of the driver and generates a signal VCP, the output terminal of the driver is connected to the input terminal of the power transistor unit and the first input terminal of the current limiting sampling unit, the output terminal of the power transistor is connected to the second input terminal of the current limiting sampling unit and generates a signal V2, the output terminal of the overcurrent protection unit is connected to the first control terminal of the driver, and the output terminal of the current limiting sampling unit is connected to the second control terminal of the driver.

[0046] The power transistor unit includes NMOS transistors M0 and M1. The drain of NMOS transistor M0 is connected to the input signal VA. The gate of NMOS transistor M0 is connected to the gate of NMOS transistor M1 and serves as the input terminal of the power transistor unit. The source of NMOS transistor M0 is connected to the source of NMOS transistor M1 and serves as the output terminal of the power transistor unit to generate signal V2. The drain of NMOS transistor M1 is connected to the signal VB.

[0047] The current-limiting sampling unit includes NMOS transistors M2, M3, M4, M5, and M6, error amplifiers EA1, EA2, and EA3, and resistor R0. The drain of NMOS transistor M2 is connected to signal V4. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M5 and serves as the first input terminal of the current-limiting sampling unit. The source of NMOS transistor M2 is connected to the drain of NMOS transistor M3 and the first input terminal of error amplifier EA1 to generate signal V1. The second input terminal of error amplifier EA1 is connected to the first input terminal of error amplifier EA2 and serves as the second input terminal of the current-limiting sampling unit. The output terminal of error amplifier EA1 is connected to NMOS transistor M6. The gate of S-channel transistor M3 is connected to the source of NMOS transistor M3, the source of NMOS transistor M4, one end of resistor R0, and the first input terminal of error amplifier EA3. The gate of NMOS transistor M4 is connected to the output terminal of error amplifier EA2. The drain of NMOS transistor M4 is connected to the second input terminal of error amplifier EA2 and the source of PMOS transistor PM5 to generate signal V3. The drain of NMOS transistor M5 is connected to signal V6. The other end of resistor R0 is grounded. The second input terminal of error amplifier EA3 is connected to the reference voltage VREF. The output terminal of error amplifier EA3 is connected to the gate of NMOS transistor M6. The drain of NMOS transistor M6 serves as the output terminal of the current-limiting sampling unit. The source of NMOS transistor M6 is grounded.

[0048] The reference voltage VREF is generated by a bandgap reference source.

[0049] The overcurrent protection unit includes a common-gate comparator CGC1, a common-gate comparator CGC2, an OR gate, resistors R1, R2, R3, and R4. The first input terminal of the common-gate comparator CGC1 is connected to signal V4, and the second input terminal of the common-gate comparator CGC1 is connected to signal V5. The first input terminal of the common-gate comparator CGC2 is connected to signal V6, and the second input terminal of the common-gate comparator CGC2 is connected to signal V7. The output terminal of the common-gate comparator CGC1 is connected to the first input terminal of the OR gate, and the output terminal of the common-gate comparator CGC2 is connected to the second input terminal of the OR gate. The output terminal of the OR gate serves as the output terminal of the overcurrent protection unit. One end of resistor R1 is connected to one end of resistor R2 and is connected to the input signal VA. The other end of resistor R1 generates signal V4, and the other end of resistor R2 generates signal V5. One end of resistor R3 is connected to one end of resistor R4 and is connected to the input signal VB. The other end of resistor R3 generates signal V6, and the other end of resistor R4 generates signal V7.

[0050] Common-gate comparators CGC1 and CGC2 each include resistors R5 and R6, PMOS transistors M7 and M8, current source I3, and current source I4. One end of resistor R5 is connected to one end of resistor R6 and is connected to signal VA. The other end of resistor R5 is connected to the source of PMOS transistor M7 and serves as the first input terminal of the common-gate comparator. The other end of resistor R6 is connected to the source of PMOS transistor M8 and serves as the second input terminal of the common-gate comparator. The gates of PMOS transistors M7 and M8, the drain of PMOS transistor M7, and one end of current source I3 are connected. The drain of PMOS transistor M8 is connected to one end of current source I4 and serves as the output terminal of the common-gate comparator. The other ends of current sources I3 and I4 are grounded.

[0051] A control method for a load switch integrating bidirectional current limiting protection and overcurrent protection includes the following steps:

[0052] The high-voltage selector compares the voltage values ​​of input signals VA and VB and outputs the maximum value between them. If signal VA is greater than signal VB, the high-voltage selector outputs signal VA; if signal VB is greater than signal VA, the high-voltage selector outputs signal VB.

[0053] The charge pump boosts the output voltage of the high-voltage selector and outputs a signal VCP to drive the power transistor unit.

[0054] The driver controls the conduction state of the power transistor unit by controlling the gate voltage of NMOS transistors M0 and M1. When the load current of the load switch is within the current limit range, the driver controls NMOS transistors M0 and M1 to conduct. When the load current is greater than the current limit, the driver limits the gate voltage of NMOS transistors M0 and M1 to provide a constant current to the load until the load current drops to the current limit.

[0055] When the load current of the load switch is less than the current limit, the load switch is equivalent to a wire connected to the external circuit. When the load current is greater than the current limit, the load switch is equivalent to a current source providing a constant current to the external circuit. The power transistor unit adopts a back-to-back circuit connection of NMOS transistors M0 and M1, and the power transistor unit can operate in both directions.

[0056] A bandgap reference source generates a reference voltage VREF to set the threshold for current limiting detection.

[0057] Error amplifier EA3 controls the conduction state of NMOS transistor M6 by comparing the voltage generated by the sampling current of NMOS transistor M2 or NMOS transistor M5 flowing through resistor R0 with the reference voltage VREF, and controls the conduction state of NMOS transistors M0 and M1 through a driver; NMOS transistor M2, resistor R1, NMOS transistor M3 and error amplifier EA1 constitute the current sampling module for signal VB, and NMOS sampling transistor M5, resistor R3, NMOS transistor M4 and error amplifier EA2 constitute the current sampling module for signal VA.

[0058] When signal VB is connected to the load current and signal VA is connected to the power supply voltage, error amplifier EA1 and NMOS transistor M3 form a negative feedback loop, clamping signals V1 and V2. According to the MOSFET saturation current formula:

[0059]

[0060]

[0061] Where I0 is the current through NMOS transistor M0, and I2 is the sampling current flowing through NMOS transistor M2. It is the average mobility of electrons in the channel. is the gate oxide capacitance per unit area, W is the width of the transistor channel, and L is the length of the transistor channel. It is the width-to-length ratio of the NMOS transistor M0. It is the width-to-length ratio of NMOS transistor M2. It is the gate-source voltage of the transistor. It is the threshold voltage. It is the channel length modulation coefficient. It is the drain-source voltage of NMOS transistor M0. This is the drain-source voltage of NMOS transistor M2; when the resistance of resistor R1 is very small (on the order of a few ohms), the voltage drop across resistor R1 is ignored; the sampling current I2 is determined by the ratio of the width-to-length ratio of NMOS transistor M0 and NMOS transistor M2. In practice, the ratio of the width-to-length ratio of NMOS transistor M0 and NMOS transistor M2 is limited by the on-resistance RON of the load switch and the area of ​​the power transistor; the voltage generated by the sampling current I2 flowing into resistor R0 is compared with the reference voltage VREF through error amplifier EA3, and the driver is controlled by controlling the on-state of NMOS optocoupler M6.

[0062] The load switch current limit value is equal to the current I0 and

[0063]

[0064] The current limiting value of the load switch is determined by modifying the width-to-length ratio of NMOS transistor M0, the width-to-length ratio of NMOS transistor M2, the reference voltage VREF, and the value of resistor R0.

[0065] When signal VA is connected to the load current and signal VB is connected to the power supply voltage, error amplifier EA2 and NMOS transistor M4 form a negative feedback loop to clamp signals V3 and V2. When the resistance of resistor R3 is very small, the voltage drop across resistor R3 is ignored. The sampling current of NMOS transistor M5 is determined by the ratio of the width-to-length ratio of the second N-type power MOS transistor M1 and the sampling transistor M5. The voltage generated by the sampling current of NMOS transistor M5 flowing into resistor R0 is compared with the reference voltage VREF by error amplifier EA3, and the driver is controlled by controlling the conduction state of NMOS transistor M6.

[0066] The load switch current limit value is equal to the current I1 and

[0067]

[0068] The current limiting value of the load switch is determined by modifying the width-to-length ratio of NMOS transistor M1, the width-to-length ratio of NMOS transistor M5, the reference voltage VREF, and the value of resistor R0.

[0069] The maximum overcurrent value IOCP of the overcurrent protection unit is expressed as:

[0070]

[0071] Because the current value of current source I3 is much smaller than the sampling current I2, the current flowing through resistor R1 is equivalent to the sampling current I2. Therefore, the current relationship of the common-gate comparator CGC1 is expressed as follows:

[0072]

[0073] Where I4 is the current value of current source I4.

[0074] The final maximum overcurrent value IOCP of the overcurrent protection unit is expressed as:

[0075]

[0076] The maximum overcurrent value IOCP is determined by modifying the values ​​of current source I4 and resistor R6.

[0077] In the common-gate comparator CGC1, if the load current of signal VB exceeds the maximum overcurrent value IOCP, the current replicated by the power transistor unit flows through resistor R5, causing the voltage drop across resistor R5 to be greater than the voltage drop across resistor R6. The voltage value of signal V4 is less than the voltage value of signal V5, and the output port of the common-gate comparator CGC1 generates an overcurrent protection high-level signal VOCP.

[0078] Similarly, in the common-gate comparator CGC2, if the load current of the signal VA exceeds the maximum overcurrent value IOCP, the output port of the common-gate comparator CGC2 will generate an overcurrent protection high-level signal VOCP.

[0079] The overcurrent protection signals output by common-gate comparators CGC1 and CGC2 are superimposed in the overcurrent protection unit via an OR gate, and the overcurrent protection is achieved by controlling the switching of the power transistor unit using a driver.

[0080] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a load switch and control method that integrates bidirectional current limiting protection and overcurrent protection, which is beneficial for current control at the external port while it is conducting in both directions; the load switch uses NMOS power transistors placed back to back, the current limiting sampling unit is implemented by error amplifier negative feedback clamping, and the overcurrent protection unit is implemented by comparison through a common gate comparator. The forward and reverse load currents are processed by two sampling circuits respectively, which is suitable for scenarios that require bidirectional current flow.

[0081] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A load switch integrating bidirectional current limiting protection and overcurrent protection, characterized in that: It includes a high-voltage selector, a charge pump, a driver, a power transistor unit, a current-limiting sampling unit, and an overcurrent protection unit. The first input terminal of the high-voltage selector is connected to the input signal VA, the second input terminal of the high-voltage selector is connected to the input signal VB, the output terminal of the high-voltage selector is connected to the input terminal of the charge pump, the output terminal of the charge pump is connected to the input terminal of the driver and generates the signal VCP, the output terminal of the driver is connected to the input terminal of the power transistor unit and the first input terminal of the current-limiting sampling unit, the output terminal of the power transistor is connected to the second input terminal of the current-limiting sampling unit and generates the signal V2, the output terminal of the overcurrent protection unit is connected to the first control terminal of the driver, and the output terminal of the current-limiting sampling unit is connected to the second control terminal of the driver. The current-limiting sampling unit includes NMOS transistors M2, M3, M4, M5, and M6, error amplifiers EA1, EA2, and EA3, and resistor R0. The drain of NMOS transistor M2 is connected to signal V4. The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M5 and serves as the first input terminal of the current-limiting sampling unit. The source of NMOS transistor M2 is connected to the drain of NMOS transistor M3 and the first input terminal of error amplifier EA1 to generate signal V1. The second input terminal of error amplifier EA1 is connected to the first input terminal of error amplifier EA2 and serves as the second input terminal of the current-limiting sampling unit. The output terminal of error amplifier EA1 is connected to NMOS transistor M6. The gate of NMOS transistor M3 is connected to the source of NMOS transistor M3, the source of NMOS transistor M4, one end of resistor R0, and the first input terminal of error amplifier EA3. The gate of NMOS transistor M4 is connected to the output terminal of error amplifier EA2. The drain of NMOS transistor M4 is connected to the second input terminal of error amplifier EA2 and the source of PMOS transistor PM5 to generate signal V3. The drain of NMOS transistor M5 is connected to signal V6. The other end of resistor R0 is grounded. The second input terminal of error amplifier EA3 is connected to the reference voltage VREF. The output terminal of error amplifier EA3 is connected to the gate of NMOS transistor M6. The drain of NMOS transistor M6 serves as the output terminal of the current-limiting sampling unit. The source of NMOS transistor M6 is grounded.

2. The load switch integrating bidirectional current limiting protection and overcurrent protection according to claim 1, characterized in that: The power transistor unit includes NMOS transistors M0 and M1. The drain of NMOS transistor M0 is connected to the input signal VA. The gate of NMOS transistor M0 is connected to the gate of NMOS transistor M1 and serves as the input terminal of the power transistor unit. The source of NMOS transistor M0 is connected to the source of NMOS transistor M1 and serves as the output terminal of the power transistor unit to generate signal V2. The drain of NMOS transistor M1 is connected to the signal VB.

3. A load switch integrating bidirectional current limiting protection and overcurrent protection according to claim 1, characterized in that: The reference voltage VREF is generated by a bandgap reference source.

4. A load switch integrating bidirectional current limiting protection and overcurrent protection according to claim 1, characterized in that: The overcurrent protection unit includes a common-gate comparator CGC1, a common-gate comparator CGC2, an OR gate, resistors R1, R2, R3, and R4. The first input terminal of the common-gate comparator CGC1 is connected to signal V4, and the second input terminal of the common-gate comparator CGC1 is connected to signal V5. The first input terminal of the common-gate comparator CGC2 is connected to signal V6, and the second input terminal of the common-gate comparator CGC2 is connected to signal V7. The output terminal of the common-gate comparator CGC1 is connected to the first input terminal of the OR gate, and the output terminal of the common-gate comparator CGC2 is connected to the second input terminal of the OR gate. The output terminal of the OR gate serves as the output terminal of the overcurrent protection unit. One end of resistor R1 is connected to one end of resistor R2 and is connected to the input signal VA. The other end of resistor R1 generates signal V4, and the other end of resistor R2 generates signal V5. One end of resistor R3 is connected to one end of resistor R4 and is connected to the input signal VB. The other end of resistor R3 generates signal V6, and the other end of resistor R4 generates signal V7.

5. A load switch integrating bidirectional current limiting protection and overcurrent protection according to claim 4, characterized in that: The common-gate comparators CGC1 and CGC2 each include resistors R5 and R6, PMOS transistors M7 and M8, current source I3, and current source I4. One end of resistor R5 is connected to one end of resistor R6 and is connected to signal VA. The other end of resistor R5 is connected to the source of PMOS transistor M7 and serves as the first input terminal of the common-gate comparator. The other end of resistor R6 is connected to the source of PMOS transistor M8 and serves as the second input terminal of the common-gate comparator. The gates of PMOS transistor M7 and M8, the drain of PMOS transistor M7, and one end of current source I3 are connected. The drain of PMOS transistor M8 is connected to one end of current source I4 and serves as the output terminal of the common-gate comparator. The other ends of current sources I3 and I4 are grounded.

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