Serial transceiver repetitive extension coding system with wide rate adaptability

Abstract

The present invention discloses a serial transceiver repetition expansion coding system with a wide rate adaptability range, comprising: a transmitting transmission module, which converts the transmission bit width of upper-layer data and the input bit width of a bottom-layer transmitting repetition expansion encoder module; a transmitting repetition expansion encoder module, which performs repetition expansion coding on data received from the transmitting transmission module to generate a low-rate data signal input to a high-speed serial transceiver; a receiving repetition expansion decoder module, which extracts the original signal from the low-rate data signal output by the high-speed serial transceiver; and a receiving transmission module, which is used to convert the output bit width of the bottom-layer receiving repetition expansion decoder module and the receiving bit width of the upper-layer data. The serial transceiver repetition expansion coding system with a wide rate adaptability range of the present invention performs repetition expansion coding on upper-layer user transmitted data at the transmitting end and performs repetition expansion decoding on the received data at the receiving end, thereby achieving a line rate that is a positive integer fraction of the high-speed serial transceiver configuration line rate.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed serial transceivers, and in particular relates to a serial transceiver repetitive expansion coding system with a wide rate adaptation range. Background Art

[0002] High-speed serial transceivers (SerDes) are key components for high-speed, low-latency data transmission and are widely used in communications, data centers, storage devices, and other fields. At the transmitter end, a high-speed serial transceiver uses a serialization process to combine multiple parallel input data lines into a bit-by-bit serial signal for high-speed transmission over long distances. At the receiver end, a deserializer restores the data to its original parallel form for output, significantly reducing the number of transmission lines, thereby reducing system complexity and power consumption.

[0003] With the continuous advancement of communication technology, the transmission rates of high-speed serial transceivers have also continued to increase, supporting high-speed data streams ranging from several Gbps to hundreds of Gbps to meet modern data transmission requirements. FPGAs often use general-purpose high-speed serial transceivers to provide a wide range of line rate support. For example, Xilinx's high-end FPGA chips, such as the Versal series, already offer GTM transceivers with line rates ranging from 9.5 Gbps to 112 Gbps. However, to reduce design complexity, control cost and power consumption, and enhance product market positioning, high-end general-purpose high-speed serial transceivers used in FPGAs often do not support lower line rate configurations, while low-end high-speed serial transceivers are unable to achieve high-speed transmission and reception. Therefore, communication protocols that require switching between high and low rates, such as InfiniBand, which may switch between 2.5 Gbps and 106.25 Gbps, are difficult to implement using general-purpose FPGA high-speed serial transceivers, and typically require specialized custom high-speed serial transceivers.

[0004] It can be seen that providing a method that enables a general-purpose high-end high-speed serial transceiver to transmit and receive data at a rate lower than the minimum supported line rate to meet the needs of implementing specific communication protocols on platforms that are difficult to customize, such as FPGAs, has become a technical problem that needs to be urgently solved in this field. Summary of the Invention

[0005] The present invention provides a serial transceiver repetitive expansion coding system with a wide rate adaptability range to solve the above-mentioned technical problems, specifically adopting the following technical solutions:

[0006] A serial transceiver repetitive extension coding system with a wide rate adaptation range comprises: a transmitting transmission module, a transmitting repetitive extension encoder module, a receiving repetitive extension decoder module and a receiving transmission module;

[0007] The transmission transmission module is used to convert the transmission bit width of the upper layer data and the input bit width of the bottom layer transmission repetitive expansion encoder module;

[0008] The transmitting repeat extension encoder module is used to perform repeat extension encoding on the data received from the transmitting transmission module to generate a low-rate data signal input to a high-speed serial transceiver;

[0009] The receiving repetition extension decoder module is used to extract the original signal from the low-rate data signal output by the high-speed serial transceiver;

[0010] The receiving transmission module is used to convert the output bit width of the bottom layer receiving repetitive extension decoder module and the upper layer data receiving bit width.

[0011] Furthermore, the upper layer data clock and the lower layer data clock of the transmission module may be synchronous or asynchronous;

[0012] The validity of the data sent by the upper layer received by the transmission module is indicated by the corresponding valid indication signal, and the sent data is continuously valid;

[0013] The upper layer data transmission bandwidth of the transmission transmission module is equal to the lower layer transmission bandwidth of the repeated expansion encoder module, that is, the upper layer data effective frequency×upper layer data bit width=repeated expansion encoder module clock frequency×repeated expansion encoder module input data bit width.

[0014] Furthermore, the transmission transmission module includes:

[0015] The transmit FIFO is used to buffer data sent from the upper layer, complete data cross-clock domain conversion, and output a full signal to back pressure the upper layer;

[0016] The sending FIFO reading module is used to control the reading of the sending FIFO, complete the data bit width conversion, and ensure that the sent data is not lost and remains valid.

[0017] Furthermore, the output data bit width of the sending repetition extension encoder module is a positive integer multiple of the input data bit width;

[0018] The sending repeat expansion encoder module repeatedly expands the input data at adjacent positions in units of bits, and sends the generated data to the high-speed serial transceiver while maintaining the original order.

[0019] Furthermore, the input data bit width of the receiving repeat extension decoder module is a positive integer multiple of the output data bit width;

[0020] The receiving repetition extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver to restore the original signal.

[0021] Furthermore, the receiving repetition extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver to restore the original signal by adopting a fixed-interval sampling or statistical reasoning method.

[0022] Furthermore, the receiving repetition extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver to restore the original signal using statistical reasoning. The statistical reasoning includes calculating the median, mode or mean of the input data and using the result as the decoding result.

[0023] Furthermore, the bottom layer data clock and the upper layer data clock of the receiving transmission module may be synchronous or asynchronous;

[0024] The receiving transmission module receives the underlying data at every beat, and the validity of the uploaded data is indicated by the corresponding valid indication signal;

[0025] The bottom layer receiving repetitive expansion encoder module bandwidth of the receiving transmission module is equal to the upper layer receiving data bandwidth, that is, the repetitive expansion decoder module clock frequency×repetitive expansion decoder module output data bit width=upper layer data effective frequency×upper layer data bit width.

[0026] Furthermore, the receiving transmission module comprises:

[0027] The receiving FIFO is used to cache the underlying data, complete the data cross-clock domain conversion, output the empty indication signal for the upper layer to judge the data reading time, and output the corresponding valid indication signal to inform the upper layer when reading data;

[0028] The receiving FIFO writing module is used to control the writing of the receiving FIFO and complete the data bit width conversion.

[0029] Furthermore, the transmission repetition extension encoder module replicates each bit of the input data k times while maintaining the original transmission order, and its output bit width is k times the input bit width.

[0030] The present invention provides a serial transceiver repetition-spread coding system with a wide rate adaptability range. The transmitting end performs repetition-spread coding on upper-layer user data, and the receiving end performs repetition-spread decoding on the received data, achieving line rates that are positive integer fractions of the configured line rate of the high-speed serial transceiver. By combining appropriate encoding and decoding repetition times and high-speed serial transceiver configuration, this system can further support line rates below the minimum supported line rate of general-purpose high-speed serial transceivers, thereby meeting the needs of implementing specific communication protocols on platforms such as FPGAs, where high-speed serial transceivers are not easily customizable. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0032] Figure 1 A schematic diagram of a serial transceiver repetitive extension coding system with a wide rate adaptability range according to the present application;

[0033] Figure 2 A schematic diagram of the transmission of this application;

[0034] Figure 3 This is a schematic diagram of the coding of the send repetition extension encoder of this application;

[0035] Figure 4 This is a decoding diagram of the receiving repeat extension decoder of this application;

[0036] Figure 5 This is a schematic diagram of the structure of the receiving transmission of this application. DETAILED DESCRIPTION

[0037] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] Obviously, the embodiments described in this case are only part of the embodiments of this application, not all of the embodiments. It should be noted that for those skilled in the art, the embodiments and features in this application can be combined with each other without departing from the concept of this application and without conflicting with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of disclosure and protection of this application.

[0039] It should be noted that when a component is referred to as being "connected" to another component, it may be directly connected to the other component or there may be an intermediate component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention.

[0040] Figure 1 This is a structural diagram of a serial transceiver repetitive expansion coding system with a wide rate adaptation range of the present application. The system can be implemented in an FPGA chip using a general-purpose high-speed serial transceiver, but is not limited to this type of chip. Specifically, the system includes: a sending transmission module, a sending repetitive expansion encoder module, a receiving repetitive expansion decoder module and a receiving transmission module. Among them, the sending transmission module completes the writing and bit width conversion of valid data sent by the upper layer. Specifically, the sending transmission module is used to convert the sending bit width of the upper layer data and the input bit width of the bottom layer sending repetitive expansion encoder module. The sending repetitive expansion encoder module performs repetitive expansion encoding on the input data and sends the encoded data to the high-speed serial transceiver. The receiving repetitive expansion decoder module decodes the data output by the high-speed serial transceiver to extract the original signal. The receiving transmission module performs bit width conversion on the decoded data and provides a data valid indication signal for the upper layer to read.

[0041] In practical applications, the transmit bit width and number of code repetition extensions for the aforementioned module can be determined as follows: First, determine the actual line rate required, denoted as r. Then, configure the high-speed serial transceiver line rate R to a multiple of the actual line rate, denoted as k, i.e., R = k × r. Then, determine the appropriate high-speed serial transceiver interface bit width and upper-layer interface bit width based on the configured rate, denoted as D. The input bit width of the encoding module is then d = D / k. If the actual bit width of the upper-layer interface is not D, the upper-layer logic must perform the corresponding bit width conversion, or the corresponding bit width conversion logic must be integrated into the transmit / receive transmission module. The specific bit width conversion process is not detailed here. Considering that the interface bit width provided by high-speed serial transceivers at low rates is generally a power of 2 and the corresponding 8b10b encoded bit width, the prime factor of n is generally only 2 or 5. The same applies to the receiver.

[0042] The upper-layer data clock and the lower-layer data clock of the transmission module can be synchronized or asynchronous. The validity of the upper-layer data sent by the transmission module is indicated by the corresponding valid indication signal, and the sent data remains valid. The upper-layer data transmission bandwidth of the transmission module is equal to the bandwidth of the lower-layer transmission repeat-expanding encoder module. That is, the upper-layer data effective frequency × the upper-layer data bit width = the repeat-expanding encoder module clock frequency × the repeat-expanding encoder module input data bit width.

[0043] The receiving transmission module's bottom-layer data clock and upper-layer data clock can be synchronized or asynchronous. Each beat of the bottom-layer data received by the receiving transmission module is valid, and the validity of the uploaded data is indicated by a corresponding validity indication signal. The receiving transmission module's bottom-layer receive repeat-expand encoder module bandwidth is equal to the upper-layer receive data bandwidth, i.e., the repeat-expand decoder module clock frequency × the repeat-expand decoder module output data bit width = the upper-layer data valid frequency × the upper-layer data bit width.

[0044] like Figure 2 As shown, as a preferred embodiment, the sending transmission module includes a sending FIFO and a sending FIFO reading module. The sending FIFO is used to cache the data sent from the upper layer, complete the data cross-clock domain conversion, and output the full signal to back pressure the upper layer. The sending FIFO reading module is used to control the reading of the sending FIFO, complete the data bit width conversion, and ensure that the sent data is not lost and remains valid. The sending FIFO reading module includes a sending read counter and a sending data selection module. On the write side, using the clock provided by the upper layer, the sending FIFO uses the valid indication signal of the upper layer data as a write enable to write data, and outputs the full indication signal to the upper layer to back pressure to prevent the FIFO from being full. The upper layer design needs to ensure that it continues to write to the FIFO when there is no full signal to prevent it from reading empty. On the reading side, using the clock provided by the high-speed serial transceiver, the sending FIFO sends an empty indication signal to the sending read counter as a sign to start counting, receives the read enable of the sending read counter, and reads data to the sending data selector. When the read counter is not empty, it begins a cyclic count with a maximum value of k and outputs the count value to the transmit data selection module for selection. After the count reaches the maximum value, the FIFO is read and the count value is cleared. The transmit data selection module selects and outputs the input data from low to high bits according to the count value in ascending order to complete the bit width conversion.

[0045] The output data bit width of the sending repeat expansion encoder module is a positive integer multiple of the input data bit width. The sending repeat expansion encoder module repeatedly expands the input data at adjacent positions in units of bits and sends the generated data to the high-speed serial transceiver in the original order. Figure 3As shown in Figure 1, the transmit repeat extension encoder replicates each bit of the input data k times while maintaining the original transmission order. Its output bit width is k times the input bit width. For example, taking k=4, the input number 2'b01 becomes 8'b00001111 after encoding. Transmit repeat extension encoding can be performed using combinational logic within a single clock cycle, or by introducing sequential logic over multiple clock cycles to improve timing.

[0046] The input data width of the receive repeat extension decoder module is a positive integer multiple of the output data width. The receive repeat extension decoder module uses fixed-interval sampling or statistical inference to decode the low-rate data signal output by the high-speed serial transceiver and restore it to the original signal.

[0047] The receiving repeat extension decoder decodes the input data to restore the pre-encoded data. In the examples of this application, two methods are provided for the repeat extension decoder module to illustrate the possibilities of decoding repeated extension data. Therefore, this application does not limit these decoding methods. It is clear that those skilled in the art can adopt other technical means to implement the method according to actual circumstances. Therefore, any variations and implementations made using any known technical means for decoding repeated extension data, without departing from the inventive concept of this solution, are all within the scope of this application.

[0048] Method 1: Fixed interval sampling

[0049] like Figure 4 As shown in (a), the input is sampled once every k bits of the repeated extended code, with a k-1 bit interval between each sampling. The sampled results are directly used as the decoding results and output in the order received. For example, if the input data is 16'b0000111100001111, sampling at a fixed interval of k = 4 will produce 4'b0101. It is easy to see that for input with a repeated extended code count of k, regardless of the initial sampling point, the k-bit fixed interval sampling can decode every bit of the original data without omission or duplication.

[0050] Method 2: Statistical Reasoning

[0051] like Figure 4As shown in (b) of [the figure], the repeated extended encoding of the input is used to count the data content of every k bits, calculate their median, mode or average value, and use the result (the average value needs to be rounded to 0 or 1) as the decoding result, and output it in the receiving order. It is easy to find that since each bit of the input data has only two values, 0 or 1, the results of the median, mode and average value are the same. It should be noted that if k is an even number and the number of 0s and 1s within k bits is equal, the i-th bit (0 < i <= k) in the k bits is fixedly used as the decoding result, and at this time the statistical inference degenerates into fixed-interval sampling. For example, if the input data is 16’b0000111100001111, the statistical inference of the median with i = 2 and k = 4 results in 4’b'0101. It is easy to find that for the input with the repeated extended encoding times of k, no matter where the statistical interval starts to be divided, the statistical inference of k can decode each bit of the original data without omission and without repetition.

[0052] As Figure 5 shown, as a preferred embodiment, the receiving transmission module includes a receiving FIFO writing module and a receiving FIFO. The receiving FIFO writing module includes a receiving writing counter and a receiving data selection module. On the writing side, under the clock provided by the high-speed serial transceiver, after the high-speed serial transceiver is reset, the receiving writing counter starts a cyclic clear counting with the maximum value of k, outputs the count value to the receiving data selection module for it to select, writes to the FIFO after counting to the maximum value and clears the count value. The receiving data selection module selects and寄存 the input data according to the count value to complete the bit-width conversion. The receiving FIFO receives the count value of the read counter as the write enable. On the reading side, the clock is provided by the upper layer. The receiving FIFO receives the read enable signal from the upper layer, outputs the read data valid indication signal while outputting the data, and outputs the empty indication signal to the upper layer for judgment of reading to prevent it from being read empty or written full.

[0053] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all details in detail, nor limit the invention to the specific implementation manners described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments to better explain the principle and practical application of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0054] Those skilled in the art will appreciate that, in addition to implementing the system, device, and various modules provided by the present invention in pure computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. by logically programming the method steps. Therefore, the system and various modules provided by the present invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0055] In addition, all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program. The program is stored in a storage medium and includes a number of instructions for causing a single-chip microcomputer, chip, or processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0056] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the scope of protection of the present invention.

Claims

1. A serial transceiver repetitive extension coding system with a wide rate adaptability range, characterized in that: include: a sending transmission module, a sending repeat extension encoder module, a receiving repeat extension decoder module and a receiving transmission module; The transmission transmission module is used to convert the transmission bit width of the upper layer data and the input bit width of the bottom layer transmission repetitive expansion encoder module; The transmitting repeat extension encoder module is used to perform repeat extension encoding on the data received from the transmitting transmission module to generate a low-rate data signal input to a high-speed serial transceiver; The receiving repetition extension decoder module is used to extract the original signal from the low-rate data signal output by the high-speed serial transceiver; The receiving transmission module is used to convert the output bit width of the bottom layer receiving repeat extension decoder module and the upper layer data receiving bit width; The upper layer data clock and the lower layer data clock of the transmission module can be synchronous or asynchronous; The validity of the data sent by the upper layer received by the transmission module is indicated by the corresponding valid indication signal, and the sent data is continuously valid; The upper layer data transmission bandwidth of the transmission module is equal to the bandwidth of the bottom layer repeat expansion encoder module, that is, the upper layer data effective frequency × upper layer data bit width = repeat expansion encoder module clock frequency × repeat expansion encoder module input data bit width; The transmission repeat extension encoder module copies each bit of the input data k times while maintaining the original transmission order, and its output bit width is k times the input bit width.

2. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 1, characterized in that: The transmission module includes: The transmit FIFO is used to buffer data sent from the upper layer, complete data cross-clock domain conversion, and output a full signal to back pressure the upper layer; The sending FIFO reading module is used to control the reading of the sending FIFO, complete the data bit width conversion, and ensure that the sent data is not lost and remains valid.

3. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 1, characterized in that: The output data bit width of the sending repeat extension encoder module is a positive integer multiple of the input data bit width; The sending repeat expansion encoder module repeatedly expands the input data at adjacent positions in units of bits, and sends the generated data to the high-speed serial transceiver while maintaining the original order.

4. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 1, characterized in that: The input data bit width of the receiving repeat extension decoder module is a positive integer multiple of the output data bit width; The receiving repetition extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver to restore the original signal.

5. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 4, characterized in that: The receiving repetition extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver and restores the original signal by adopting a fixed-interval sampling or statistical reasoning method.

6. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 5, characterized in that: The receiving repeat extension decoder module decodes the low-rate data signal output by the high-speed serial transceiver to restore the original signal by using statistical reasoning. The statistical reasoning includes calculating the median, mode or mean of the input data and using the result as the decoding result.

7. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 1, characterized in that: The bottom layer data clock and the upper layer data clock of the receiving transmission module may be synchronous or asynchronous; The receiving transmission module receives the underlying data at every beat, and the validity of the uploaded data is indicated by the corresponding valid indication signal; The bottom layer receiving repetitive expansion encoder module bandwidth of the receiving transmission module is equal to the upper layer receiving data bandwidth, that is, the repetitive expansion decoder module clock frequency×repetitive expansion decoder module output data bit width=upper layer data effective frequency×upper layer data bit width.

8. The serial transceiver repetitive extension coding system with a wide rate adaptability range according to claim 1, characterized in that: The receiving transmission module comprises: The receiving FIFO is used to cache the underlying data, complete the data cross-clock domain conversion, output the empty indication signal for the upper layer to judge the data reading time, and output the corresponding read data valid indication signal to inform the upper layer when reading data; The receiving FIFO writing module is used to control the writing of the receiving FIFO and complete the data bit width conversion.

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