Back laser TOPCon battery structure and production process

Abstract

The invention discloses a back laser TOPCon battery structure and a production process, the back laser TOPCon battery structure comprises a substrate, one end face of the substrate is sequentially provided with a first silicon oxide layer and a first polycrystalline silicon layer, the surface of the first polycrystalline silicon layer comprises a plurality of first contact areas and second contact areas except the first contact areas, and the first contact areas and the second contact areas are arranged on the substrate. A second silicon dioxide layer matched with the first contact area is arranged on the first polycrystalline silicon layer, a second polycrystalline silicon layer matched with the second silicon dioxide layer and a third protection layer are sequentially arranged on one end face, back on to the first polycrystalline silicon layer, of the second silicon dioxide layer, and a second electrode is arranged on the third protection layer. One end of the second electrode penetrates through the third protection layer to be in contact with the second polycrystalline silicon layer, and the first polycrystalline silicon layer is provided with a second protection layer matched with the second contact area. Compared with the prior art, the back laser TOPCon battery structure and the production process have the advantage that the performance and the reliability of the battery are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaic cells, and specifically relates to a back laser TOPCon cell structure and a production process thereof. Background Art

[0002] Regarding the optimization of the battery preparation process, many improvement measures have been implemented. For example, during the preparation of the electrode material, various organic components have been added to improve the compatibility, the ratio of functional groups in the precursor has been adjusted to optimize the polymerization performance, and the conditions of dispersion and polymerization have been optimized to reduce the surface impurity content. In addition, the specific capacity and loading amount of the electrode material have also been adjusted to improve the manufacturing efficiency.

[0003] However, even with these improvement measures, there is still a certain degree of microscopic film bursting phenomenon in the low-efficiency gear. During the detection process, it is found that the proportion of EL black spots in the low-efficiency gear reaches more than 80%. This phenomenon not only affects the efficiency of the battery, but also may lead to instability in quality. Therefore, further research and improvement are still needed on how to further improve the stability of the battery in the low-efficiency gear.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a back laser TOPCon cell structure and a production process thereof, which can solve the technical problems raised in the above background art.

[0006] To achieve the above purpose, the technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A back laser TOPCon cell structure includes a substrate. On one end face of the substrate, a first silicon oxide layer and a first polysilicon layer are sequentially arranged. The surface of the first polysilicon layer includes a plurality of first contact areas and a second contact area other than the first contact areas. A second silicon oxide layer matching the first contact areas is arranged on the first polysilicon layer. On the end face of the second silicon oxide layer facing away from the first polysilicon layer, a second polysilicon layer and a third protective layer matching the second silicon oxide layer are sequentially arranged. A second electrode is arranged on the third protective layer. One end of the second electrode passes through the third protective layer and contacts the second polysilicon layer. A second protective layer matching the second contact area is arranged on the first polysilicon layer.

[0008] In one or more embodiments of the present invention, a boron emitter, a passivation layer, and a first protective layer are sequentially disposed on an end face of the substrate facing away from the first silicon oxide layer. A first electrode is disposed on the first protective layer, and one end of the first electrode passes through the first protective layer and the passivation layer and contacts the boron emitter.

[0009] In one or more embodiments of the present invention, the thickness of the second polysilicon layer is greater than the thickness of the first polysilicon layer.

[0010] In one or more embodiments of the present invention, the thickness of the first polysilicon layer is not greater than 20 nm, and the thickness of the second polysilicon layer is not greater than 300 nm.

[0011] In one or more embodiments of the present invention, the thickness of the third protective layer is greater than the thickness of the second protective layer.

[0012] In one or more embodiments of the present invention, the substrate is an N-type silicon substrate.

[0013] In one or more embodiments of the present invention, the third protective layer, the second protective layer, and the first protective layer are all SiNx layers.

[0014] In one or more embodiments of the present invention, the passivation layer is an AlOx layer.

[0015] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows:

[0016] A production process of a back laser TOPCon cell structure includes the following steps:

[0017] S1. Preceding steps:

[0018] A first silicon wafer with a textured surface and a PN junction formed on the front surface is obtained through a texturing, boron diffusion, and alkali polishing process.

[0019] S2. Polysilicon deposition and annealing:

[0020] Using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition technology, under plasma activation conditions, gaseous silicon molecules and dopant atoms are decomposed and recombined into solid polysilicon on the surface of the first silicon wafer, and the dopant atoms are uniformly distributed in the polysilicon thin film to form a polysilicon layer on the surface of the first silicon wafer.

[0021] The first silicon wafer with a polysilicon layer formed thereon is annealed to obtain a second silicon wafer.

[0022] S3. Laser patterning:

[0023] The polysilicon mask layer of the second silicon wafer is loosened and modified by laser, and the polysilicon is thinned by utilizing the difference in the etching rate of the polysilicon mask layer before and after modification in the wet etching process, forming a patterned polysilicon on the back surface to obtain the third silicon wafer;

[0024] S4, RCA process:

[0025] A protective film is fabricated on the back surface of the third silicon wafer after phosphorus doping, and the phosphorus doping layers deposited on the front and side surfaces are removed using a chemical solution;

[0026] The third silicon wafer is placed in a KOH solution or a NaOH solution containing additives for reaction, and then the silicon wafer is placed in a mixed solution of KOH or NaOH and H2O2 for cleaning. After the cleaning, the third silicon wafer is taken out and washed with water to obtain the fourth silicon wafer;

[0027] S4, ALD process:

[0028] A gaseous substance containing an aluminum source is introduced into the reaction chamber. The gaseous Al3 is first adsorbed on the surface of the silicon wafer, and then reacts with the water vapor introduced subsequently to generate aluminum hydroxide, which adheres to the surface of the fourth silicon wafer, while methane gas is produced. The reaction equation is:

[0029] Al(CH3)3 + 3H2O → Al(OH)3 + 3CH4↑

[0030] Al(OH)3 undergoes a dehydration reaction to be converted into aluminum oxide. The reaction equation is:

[0031] 2Al(OH)3 → Al2O3 + 3H2O↑

[0032] By repeating the above reaction steps, a layer-by-layer aluminum oxide film is formed on the surface of the fourth silicon wafer to obtain the fifth silicon wafer;

[0033] S5, silicon nitride coating:

[0034] Through the reaction of SiI and NH, a dense SiNx film is deposited on the surface of the silicon wafer to obtain the sixth silicon wafer;

[0035] S6, screen printing and sintering:

[0036] Positive and negative electrodes are fabricated on the surface of the sixth silicon wafer to conduct the current generated by the battery under illumination and realize the electrical performance of the battery.

[0037] In one or more embodiments of the present invention, in step S5, the thickness of the SiNx film is 60 - 100 nm.

[0038] Compared with the prior art, a back-laser TOPCon cell structure and production process of the present invention significantly improve the performance and reliability of the cell. First, a first silicon oxide layer and a first polysilicon layer are sequentially arranged on the back surface of the N-type silicon substrate. This design not only effectively avoids the corrosion of the substrate but also eliminates the generation of corrosion steps. This not only takes into account the carrier transport efficiency, optical performance, passivation effect, and mechanical load-bearing capacity but also eliminates the need for a back-side AlOx passivation layer, thus avoiding the problem of cell failure caused by the bursting of the passivation layer.

[0039] Second, the setting of the first polysilicon layer fundamentally improves the EL pitting problem caused by paste leakage during screen printing. EL pitting is a common defect in the cell manufacturing process, which affects the photoelectric conversion efficiency and appearance quality of the cell. By forming a passivation effect in the second contact area of the first polysilicon layer, no additional passivation treatment is required on the back surface of the substrate. This not only simplifies the manufacturing process but also further reduces the risk of back-side film bursting.

[0040] In addition, the thickness of the second polysilicon layer is significantly greater than that of the first polysilicon layer. This design enhances the anti-bending strength of the cell and solves the problem of strength attenuation of the TOPCon cell under mechanical stress. The combination of the second polysilicon layer and the second silicon oxide layer further optimizes the passivation effect and carrier transport efficiency of the cell, thereby improving the overall performance of the cell.

[0041] In terms of electrode design, the second electrode passes through the third protective layer and is in direct contact with the second polysilicon layer, ensuring good electrical connection and efficient carrier collection. At the same time, the first electrode passes through the first protective layer and the passivation layer and contacts the boron emitter, further optimizing the current transmission path of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 FIG. [ID] is a schematic structural diagram of a back-laser TOPCon cell structure in an embodiment of the present invention;

[0044] Figure 2 FIG. [ID] is a schematic structural diagram of a second silicon wafer in an embodiment of the present invention;

[0045] Figure 3 FIG. [ID] is a schematic structural diagram of a third silicon wafer in an embodiment of the present invention;

[0046] Figure 4 Schematic diagram of the structure of the fourth silicon wafer in an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the structure of the fifth silicon wafer in an embodiment of the present invention;

[0048] Figure 6 Comparison chart of electrical performance tests between the conventional TOPCon cell structure and the TOPCon cell structure of the present invention;

[0049] Figure 7 Comparison of the bending strength tests between the conventional TOPCon cell structure and the TOPCon cell structure of the present invention Figure 1 ;

[0050] Figure 8 Comparison of the bending strength tests between the conventional TOPCon cell structure and the TOPCon cell structure of the present invention Figure 1 ;

[0051] Figure 9 Schematic diagram of EL pits of the TOPCon cell of the present invention;

[0052] Figure 10 Partial schematic diagram of the silicon substrate prepared for the TOPCon cell of the present invention;

[0053] Figure 11 For Figure 10 Partial structure schematic diagram in

[0055] Main reference numeral description:

[0056] 1. Substrate; 2. Boron emitter; 3. Passivation layer; 4. First protective layer; 5. First electrode; 6. First silicon oxide layer; 7. First polysilicon layer; 8. Second protective layer; 9. Second silicon oxide layer; 10. Second polysilicon layer; 11. Third protective layer; 12. Second electrode; 13. Mask layer. Detailed implementation manners

[0057] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0058] Such as Figure 1As shown in the figure, a back laser TOPCon battery structure in an embodiment of the present invention includes a substrate 1, the substrate 1 is an N-type silicon substrate, and a first silicon oxide layer 6 and a first polysilicon layer 7 are sequentially arranged on one end surface of the substrate 1. The first silicon oxide layer 6 is arranged on the back surface of the substrate 1. The surface of the first polysilicon layer 7 includes several first contact areas and a second contact area other than the first contact areas. That is, the surface of the first polysilicon layer 7 has a plurality of first contact areas, and the surface of the first polysilicon layer 7 except for the first contact areas is the second contact area.

[0059] As Figure 1 shown, a second silicon oxide layer 9 matching the first contact area is arranged on the first polysilicon layer 7, that is, a second silicon oxide layer 9 matching the first contact area is arranged on the front surface of the first polysilicon layer 7. On the end surface of the second silicon oxide layer 9 facing away from the first polysilicon layer 7, a second polysilicon layer 10 and a third protective layer 11 matching the second silicon oxide layer 9 are sequentially arranged. That is, the second polysilicon layer 10 completely covers the second silicon oxide layer 9, and at the same time, the third protective layer 11 can completely cover the second polysilicon layer 10. A second electrode 12 is arranged on the third protective layer 11, and one end of the second electrode 12 passes through the third protective layer 11 and contacts the second polysilicon layer 10. A second protective layer 8 matching the second contact area is also arranged on the first polysilicon layer 7, and the second protective layer 8 completely covers the second contact area.

[0060] In this embodiment, the thickness of the third protective layer 11 is greater than the thickness of the second protective layer 8.

[0061] As Figure 1 shown, the thickness of the second polysilicon layer 10 is greater than the thickness of the first polysilicon layer 7. The thickness of the first polysilicon layer 7 is generally not greater than 20 nm. Preferably, the thickness of the first polysilicon layer 7 is 3 - 7 nm. The thickness of the second polysilicon layer 10 is generally not greater than 300 nm. Preferably, the thickness of the second polysilicon layer 10 is 130 - 160 nm. Among them, the thickness of the first silicon oxide layer 6 is 1 - 2 nm, and the thickness of the second silicon oxide layer 9 is 1 - 3 nm.

[0062] In this embodiment, one end of the second electrode 12 passes through the third protective layer 11 and is located inside the second polysilicon layer 10. The thickness of the first silicon oxide layer 6 is 1.5 nm, the thickness of the first polysilicon layer 7 is 5 nm, the thickness of the second silicon oxide layer 9 is 2 nm, and the thickness of the second polysilicon layer 10 is 145 nm.

[0063] As Figure 1As shown, on one end face of the substrate 1 facing away from the first silicon oxide layer 6, a boron emitter 2, a passivation layer 3, and a first protective layer 4 are sequentially arranged. A first electrode 5 is arranged on the first protective layer 4. One end of the first electrode 5 passes through the first protective layer 4 and the passivation layer 3 and then contacts the boron emitter 2. In this embodiment, one end of the first electrode 5 is located inside the boron emitter 2 after passing through the first protective layer 4 and the passivation layer 3.

[0064] In this embodiment, the third protective layer 11, the second protective layer 8, and the first protective layer 4 are all SiNx layers, and the passivation layer 3 is an AlOx layer.

[0065] The back laser TOPCon cell structure can avoid the corrosion of the substrate 1 by setting the first polysilicon layer 7, and thus there will be no generation of corrosion steps. It can not only take into account issues such as carrier transport, optics, passivation, and mechanical load, but also eliminate the back AlOx passivation, thereby avoiding the film bursting problem. At the same time, it can also solve the problem of the attenuation of the bending strength of the TOPCon cell.

[0066] In addition, by setting the first polysilicon layer 7, the EL pitting problem caused by screen printing paste leakage can be fundamentally improved, and the first polysilicon layer 7 can form a passivation effect in the second contact area where the second silicon oxide layer 9 is not provided. The back of the substrate 1 does not need to be passivated anymore, fundamentally avoiding the back film bursting problem.

[0067] A production process of a back laser TOPCon cell structure in an embodiment of the present invention includes the following steps:

[0068] S1. Preceding steps:

[0069] A first silicon wafer with a textured surface and a PN junction formed on the front surface is obtained through the processes of texturing, boron diffusion, and alkaline polishing.

[0070] Specifically, the main purpose of texturing is to form a textured surface structure on the silicon wafer to reduce light reflection and increase light absorption, thereby improving the photoelectric conversion efficiency of solar cells. The texturing process flow is as follows: After the silicon wafer enters the texturing tank, it comes into full contact with the etching solution and starts the etching reaction. By precisely controlling parameters such as the concentration, temperature, reaction time, and stirring speed of the etching solution, an ideal textured surface structure is formed on the silicon wafer surface. After texturing is completed, the etching solution and reaction products will remain on the silicon wafer surface, and multiple cleaning operations are required. Generally, it is first rinsed multiple times in deionized water to remove most of the impurities and residual etching solution on the surface, and then further removed of fine particles and organic substances through ultrasonic cleaning and other methods. During the cleaning process, the purity of the water quality and the cleaning time have an important impact on the surface quality of the silicon wafer. The cleaned silicon wafer needs to be dried to remove the surface moisture. Common drying methods include hot air drying, nitrogen blowing, etc. The drying process must ensure that there are no water marks and residual moisture on the silicon wafer surface, otherwise it may affect subsequent process steps. The dried silicon wafer is taken out of the equipment by a robotic arm or a conveying device and placed in a designated position, waiting to enter the next process.

[0071] Texturing process parameters: The reaction temperature is 70 ± 2 °C, the time is 410 ± 10 s, and the composition of the etching solution includes approximately 30 L of NaOH, approximately 650 L of H2O, and approximately 6 L of ADD. ADD is the additive.

[0072] The purpose of boron diffusion is to construct a PN junction, that is, to form a P-type region by boron diffusion on the N-type silicon substrate, forming a PN junction with the N-type main silicon to achieve photoelectric conversion. Its principle is that under certain conditions of concentration, temperature, pressure, and time, boron sources such as BBr3 or BCl3 are vaporized in a tube furnace and then deposited on the silicon wafer surface through a series of chemical reactions.

[0073] Taking BBr3 as an example, gaseous HCl and H2O generated during the reaction will be evenly distributed in the furnace tube under the carrier of N2. H2O will react with BBr3 and O2 to generate B2O3, and then generate gaseous HBO2. HBO2 decomposes at high temperature to generate B2O3, realizing the uniform distribution of B2O3 on the surface of the solar cell wafer, creating conditions for boron atoms to enter the silicon lattice.

[0074] The specific process flow of boron diffusion is as follows: Place the silicon wafer on a quartz boat and then put it into a diffusion furnace. First, perform a pre-oxidation treatment, then a pre-deposition treatment, followed by a secondary deposition treatment, and finally push the junction to obtain a boron diffusion layer. Finally, turn off the boron source and heating, and take out the silicon wafer after cooling.

[0075] Important process parameters: deposition temperature 820 ± 30 °C, deposition time 550 ± 50 s, BCl3 flow rate 180 ± 30 sccm, push temperature 1030 ± 20 °C, push time 5000 ± 500 s, O2 flow rate 20000 ± 1000 sccm.

[0076] The main purpose of alkaline polishing is to remove the PN junctions on the back and sides of the silicon wafer, improve the back surface reflectivity. After alkaline polishing treatment, the flatness of the back surface can be greatly improved, which has an obvious improvement on the optical long wavelength band and passivation, and finally improves the battery conversion efficiency.

[0077] The principle of alkaline polishing is to use inorganic alkali solutions such as KOH or NaOH to chemically react with the oxide layer and silicon on the surface of the silicon wafer. The hydroxide ions in the alkaline solution react with the silicon oxide on the surface of the silicon wafer to form soluble sodium silicate or potassium silicate, thereby removing the micro protrusions and defects on the surface of the silicon wafer and making the surface of the silicon wafer smooth and flat. Its process flow is as follows: in a chain equipment, HF is used to remove the borosilicate glass (BSG) on the back and edges of the silicon wafer after diffusion, while the BSG on the front of the silicon wafer is retained to prepare for alkaline polishing. Alkaline polishing treatment: in a tank equipment, the PSG on the front of the silicon wafer protects the front of the silicon wafer from being corroded by inorganic alkali, while the back and edges of the silicon wafer are polished in an inorganic alkali solution. By controlling parameters such as solution concentration, temperature, time and stirring speed, precise etching and polishing of the back and edges of the silicon wafer can be achieved. After alkaline polishing is completed, the silicon wafer is taken out of the alkali solution and rinsed with clean water such as reverse osmosis water and deionized water to remove the residual alkaline solution and impurities on the surface of the silicon wafer. Methods such as air drying or heating drying are used to ensure that the surface of the silicon wafer is dry without water stains and avoid secondary pollution to the surface of the silicon wafer caused by moisture, etc.

[0078] Important process parameters: reaction temperature 70 ± 3 °C, time 175 ± 10 s, the alkaline solution generally includes about 6.3 L of NaOH, about 685 L of H2O, and about 2.5 L of ADD.

[0079] S2. Polysilicon deposition and annealing:

[0080] Using plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition technology, under the condition of plasma activation, gaseous silicon molecules and dopant atoms are decomposed and recombined into solid polysilicon on the surface of the first silicon wafer, and the dopant atoms are evenly distributed in the polysilicon thin film, forming a polysilicon layer on the surface of the first silicon wafer. After annealing the first silicon wafer with the polysilicon layer formed, a second silicon wafer is obtained. The second silicon wafer is as Figure 2 shown, which includes a substrate 1, and a first silicon oxide layer 6, a first polysilicon layer 7, a second silicon oxide layer 9, a second polysilicon layer 10 and a mask layer 13 are sequentially arranged on one end face of the substrate 1.

[0081] Specifically, the main purpose of polysilicon deposition is to form a high-quality, high-doping-concentration polysilicon thin film, which serves as the back contact layer or local doping region of the battery, used to reduce the back surface recombination loss, improve the open-circuit voltage and short-circuit current of the battery, and ultimately enhance the conversion efficiency of the battery. It usually adopts plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) technology. Under plasma activation conditions, gaseous silicon molecules and dopant atoms are decomposed and recombined into solid polysilicon on the substrate surface, and the dopant atoms are uniformly distributed in the polysilicon thin film to form an N-type doped polysilicon layer.

[0082] The process flow of polysilicon deposition is as follows: Place the silicon wafer into the reaction chamber of the PECVD or LPCVD equipment, and introduce silicon source gas, doping gas, etc. according to the set process parameters to deposit a polysilicon layer on the surface of the silicon wafer. The annealing step is to anneal the deposited polysilicon layer, generally carried out in a tube-type thermal oxidation furnace, to improve the crystal structure of the polysilicon and enhance its performance.

[0083] Important process parameters: deposition temperature 430 ± 30 °C, SiH4 flow rate 2700 ± 100 sccm, N2O flow rate 10000 ± 200 sccm, H2 flow rate 8000 ± 150 sccm, PH3 flow rate 350 ± 20 sccm, power 15000 ± 1000; annealing temperature 900 ± 10 °C, annealing time 1800 ± 100 s.

[0084] S3. Laser patterning:

[0085] Use a laser to perform loosening modification on the polysilicon mask layer of the second silicon wafer, and utilize the difference in the etching rate of the polysilicon mask layer before and after modification in the wet etching process to achieve polysilicon thinning, forming a backside polysilicon pattern, and obtaining the third silicon wafer as shown in Figure 3 Figure.

[0086] Specifically, laser patterning is to use a 532 nm green picosecond laser to perform loosening modification on the polysilicon mask layer, and utilize the difference in the etching rate of the film layer before and after modification in the wet etching process to achieve polysilicon thinning, forming a backside polysilicon pattern. Its process flow is as follows: Adopt a picosecond laser or a femtosecond laser, image the battery cell through an imaging system, calculate the position of the metal grid lines, and plan the laser scanning processing route. Use a beam shaping system to shape the laser beam into a rectangular flat-top beam, and then scan and process the part between the metal grid lines on the back of the battery cell according to the planned route using a laser scanning system.

[0087] Important process parameters: single-point energy density 275 uj / cm2, spot length 330 ± 20 um, spot width 130 ± 20 um, overlap rate 15% ± 3%.

[0088] S4, RCA Process:

[0089] Its main purposes are as follows: First, a protective film is made on the back of the third silicon wafer after phosphorus doping, and the phosphorus-doped layers on the front and sides are removed using a chemical solution. Second, the polysilicon layer is selectively chemically etched (KOH + ADD) by laser on the back of the patterned third silicon wafer and the etching stops after reaching the laser zone oxide layer 9. Third, then the silicon wafer is placed in a mixed solution of KOH or NaOH and H2O2 for cleaning, and the washed fourth silicon wafer is taken out for water washing to obtain the fourth silicon wafer as shown in Figure 4 Figure; 4. Then it enters the HF + H2O tank to remove the non-laser zone oxide layer 13 and the laser zone oxide layer 9, ultimately achieving the purpose of selective etching patterning design without corrosion steps on the back, corresponding to the fifth silicon wafer in Figure 5 Figure.

[0090] Specifically, the first purpose of the RCA process is to remove the polysilicon thin film on the front and sides to prevent it from affecting the electrical performance of the battery, causing appearance problems or EL non-conformities, etc., ensuring the passivation effect of the battery chip, reducing problems such as leakage, and improving the conversion efficiency and product yield of the battery. Its process principle is: By making a water film on the back of the silicon wafer and other methods, the structures such as the phosphosilicate glass layer (PSG) on the back are protected from being damaged by the etching solution, ensuring that only the plated parts on the front and sides are removed. The chemical solution reacts with the plated polysilicon, phosphorus-doped layer, etc. to dissolve and remove them.

[0091] Specifically, the main purpose of the RCA process is as follows: First, utilize the difference in the looseness of the laser-selected area oxide layer and the densification of the non-laser-selected area oxide layer, which in turn leads to the difference in chemical etching rate, to perform selective etching and thus achieve the purpose of patterning. Its core reaction process is: 1. The polysilicon layer is selectively chemically etched (KOH + ADD) by laser on the back of the patterned third silicon wafer and the etching stops after reaching the laser zone oxide layer 9. Second, then the silicon wafer is placed in a mixed solution of KOH or NaOH and H2O2 for cleaning, and the washed fourth silicon wafer is taken out for water washing to obtain the fourth silicon wafer as shown in Figure 4 Figure. Third, it enters the HF + H2O tank to remove the non-laser zone oxide layer 13 and the laser zone oxide layer 9, ultimately achieving the purpose of selective etching patterning design without corrosion steps on the back, corresponding to the structural diagram of the fifth silicon wafer

[0092] Important process parameters: Reaction temperature 70 ± 2 °C, time 410 ± 10 s, the main components of the NaOH solution include approximately 30 L of NaOH, approximately 650 L of H2O, and approximately 6 L of ADD.

[0093] S4, ALD Process:

[0094] In TOPCon cells, alumina can effectively reduce the recombination rate on the silicon wafer surface, reduce the recombination of electrons and holes, thereby increasing the open-circuit voltage and short-circuit current of the cell, and ultimately improving the conversion efficiency of the cell. It usually uses atomic layer deposition (ALD) technology, and the specific steps are as follows:

[0095] Gaseous substances containing aluminum sources are introduced into the reaction chamber, such as trimethylaluminum (Al(CH3)3) and water vapor (H2O). Gaseous Al(CH3)3 is first adsorbed on the silicon wafer surface and then reacts with the subsequently introduced water vapor to form aluminum hydroxide, which adheres to the surface of the fourth silicon wafer, and methane gas is generated at the same time. The reaction equation is:

[0096] Al(CH3)3 + 3H2O → Al(OH)3 + 3CH4↑

[0097] Al(OH)3 will undergo a dehydration reaction to transform into alumina. The reaction equation is:

[0098] 2Al(OH)3 → Al2O3 + 3H2O↑

[0099] By continuously repeating the above reaction steps, an alumina thin film is grown layer by layer on the silicon wafer surface. By precisely controlling the number of reaction cycles and conditions, precise control of the thickness of the alumina thin film can be achieved. A layer-by-layer alumina thin film will be formed on the surface of the fourth silicon wafer to obtain the fifth silicon wafer as shown in Figure 5 the figure

[0100] Core process parameters: reaction temperature: 250 ± 30°C, TMA gas injection time 11 ± 3s, TMA purge time 8 ± 3s, H2O gas injection time 11 ± 3s, H2O purge time 8 ± 3s, alumina thickness 6 ± 3nm.

[0101] S5. Silicon nitride coating:

[0102] Through the reaction of SiI and NH, a dense SiNx film is deposited on the silicon wafer surface to obtain the sixth silicon wafer;

[0103] Specifically, the main purpose of silicon nitride coating is to prepare an antireflection layer with excellent passivation effect on the cell surface to reduce the reflectivity of the incident light on the cell surface, increase the open-circuit voltage and short-circuit current of the cell, and achieve the purpose of improving the cell conversion efficiency. Through the reaction of SiI and NH, a dense SiNx film with a thickness of about 60 - 100nm is deposited on the silicon wafer surface. In the preferred case, the thickness of the SiNx film is 80nm. This process is carried out in a PECVD device. The automatic wafer inverter loads the silicon wafers to be coated into the graphite boat, starts the program, and the device runs automatically. The required SiH and NH for the reaction are supplied by the special gas station, and the waste gas generated by the reaction is discharged into the silane combustion tower for treatment and then discharged through the exhaust stack after reaching the standard.

[0104] Important process parameters: Coating process time is 620 seconds, process pressure is 1750 mTorr, flow rate (sccm): SiH4:NH = 2250:11000.

[0105] S6. Screen printing and sintering:

[0106] Positive and negative electrodes are made on the surface of the sixth silicon wafer to conduct the current generated by the cell under light and realize the electrical performance of the cell.

[0107] Specifically, positive and negative electrodes are made on the surface of the TOPCon cell to conduct the current generated by the cell under light and realize the electrical performance of the cell. Materials: Commonly used pastes include silver paste, aluminum paste, etc. Silver paste has good conductivity and is used to make the front electrode. Aluminum paste can be used for the back electrode. Sometimes copper-containing paste is also used to reduce costs.

[0108] Process flow: According to the cell electrode design pattern, a screen plate with specific openings and shapes is made. The accuracy and opening size of the screen plate affect the line width and shape of the electrode. The metal paste is stirred evenly and adjusted to an appropriate viscosity and thixotropy so that it can pass through the screen plate smoothly. The silicon wafer is placed on the printing table, the screen plate is covered above the silicon wafer, and a certain pressure is applied to the screen plate with a squeegee to transfer the paste through the openings of the screen plate to the surface of the silicon wafer, forming the patterns of the positive and negative electrodes. Usually, multiple printings are required, such as front electrode printing, back electrode printing, etc. After each printing, drying treatment may be required to ensure the performance of the paste and the quality of subsequent printing.

[0109] The production process of the back laser TOPCon cell structure of the present invention has the following advantages: There is a 5nm polysilicon passivation layer retained in the laser opening area, which can avoid the corrosion of the silicon substrate and thus no corrosion steps will be generated. At the same time, it can take into account issues such as carrier transport, optics, passivation, and mechanical load, and the back AIOx passivation can be omitted, thereby avoiding the film bursting problem.

[0110] Such as Figure 6 As shown, the efficiency of the TOPCon cell of the present invention is increased by 0.01% compared with the conventional TOPCon cell, which is manifested as a 48 mA loss in Isc, a 0.13 mV gain in Uoc, and a 0.12% gain in FF. From the electrical performance results, the cell structure of the present invention has better balance among carrier transport, optics, and passivation.

[0111] Such as Figures 7 - 8 As shown, from the four-point bending strength test results, the bending strength of the TOPCon cell of the present invention and the conventional TOPCon cell in the bending area are 198 Mpa and 166 Mpa respectively. The TOPCon cell of the present invention has better bending performance.

[0112] The problems of alumina film bursting in existing conventional TOPCon cells mainly fall into two cases. One is the film bursting problem in the laser area: the silicon substrate tower base (20 - 25um) is larger than the Poly reserved area tower base (6 - 8um). The larger the tower base, the flatter the interface, and the faster the alumina deposition under the same process. The film bursting in this area can be improved by conventional methods in the industry, that is, appropriately increasing the annealing temperature or time to allow hydrogen to escape sufficiently. The other is the film bursting problem in the transition area between the laser area and the Poly reserved area. For example, there is residual laser opening film dust, and there are burrs and voids in the wet chemical etching at the edge steps, resulting in a large roughness in this area, which will cause the thickness of the alumina film to be uneven during deposition. In subsequent heat treatment and other processes, due to the uneven stress distribution in different areas, film bursting is likely to occur at weak parts. And it cannot be completely improved by conventional methods in the industry. As Figures 10 - 11 shown, because of the retention of the first polysilicon layer 7 in the present invention, on the one hand, it can protect the substrate 1 from wet chemical etching, and on the other hand, this film layer can serve as the passivation contact characteristic of the substrate 1, without the need to introduce additional alumina passivation.

[0113] The specific advantages of the TOPCon cell structure design of the present invention can be manifested as follows: there is a retention of the first polysilicon layer 7 in the laser area, which can fundamentally improve the EL pitting problem caused by screen printing paste leakage. It has a passivation effect on the laser area, and there is no need for alumina passivation on the back surface, fundamentally avoiding the problem of back surface film bursting. The substrate 1 will not be corroded by alkali, and there is no stepped area, further avoiding the problem of back surface film bursting. The silicon substrate will not be corroded by alkali, and there is no stepped area, and the problem of attenuation of the bending strength can be solved.

[0114] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non - restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0115] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A back laser TOPCon battery structure, characterized in that, It includes a substrate; On one end face of the substrate, a first silicon oxide layer and a first polysilicon layer are sequentially provided. The surface of the first polysilicon layer includes a plurality of first contact regions and a second contact region other than the first contact regions; On the first polysilicon layer, a second silicon oxide layer matching the first contact regions is provided. On the end face of the second silicon oxide layer facing away from the first polysilicon layer, a second polysilicon layer and a third protective layer matching the second silicon oxide layer are sequentially provided. A second electrode is provided on the third protective layer, and one end of the second electrode passes through the third protective layer and contacts the second polysilicon layer; On the first polysilicon layer, a second protective layer matching the second contact region is provided.

2. The back laser TOPCon battery structure according to claim 1, characterized in that On the end face of the substrate facing away from the first silicon oxide layer, a boron emitter, a passivation layer, and a first protective layer are sequentially provided. A first electrode is provided on the first protective layer, and one end of the first electrode passes through the first protective layer and the passivation layer and contacts the boron emitter.

3. A back laser TOPCon cell structure according to claim 1 or 2, characterized in that The thickness of the second polysilicon layer is greater than the thickness of the first polysilicon layer.

4. A back laser TOPCon cell structure according to claim 3, characterized in that, The thickness of the first polysilicon layer is not greater than 20 nm, and the thickness of the second polysilicon layer is not greater than 300 nm.

5. A back laser TOPCon cell structure according to claim 1, characterized in that, The thickness of the third protective layer is greater than the thickness of the second protective layer.

6. A back laser TOPCon battery structure and production process according to claim 1, characterized in that, The substrate is an N-type silicon substrate.

7. A back laser TOPCon battery structure and production process according to claim 2, characterized in that, The third protective layer, the second protective layer, and the first protective layer are all SiNx layers.

8. A back laser TOPCon battery structure and production process according to claim 1, characterized in that, The passivation layer is an AlOx layer.

9. A production process for a back laser TOPCon battery structure, characterized in that, It includes the following steps: S1. Preceding steps: Through the processes of texturing, boron diffusion, and alkaline polishing, a first silicon wafer with a textured surface and a PN junction formed on the front is obtained; S2. Polysilicon deposition and annealing: Using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition technology, under plasma activation conditions, gaseous silicon molecules and dopant atoms are decomposed and recombined into solid polysilicon on the surface of the first silicon wafer, and the dopant atoms are uniformly distributed in the polysilicon thin film, forming a polysilicon layer on the surface of the first silicon wafer; After the first silicon wafer with the polysilicon layer formed is annealed, a second silicon wafer is obtained; S3. Laser patterning: Using a laser to perform a loosening modification on the polysilicon mask layer of the second silicon wafer, and using the difference in the etching rate of the polysilicon mask layer before and after modification in the wet etching process to achieve polysilicon thinning, forming a backside polysilicon pattern, and obtaining a third silicon wafer; S4. RCA process: Making a protective film on the back of the third silicon wafer after phosphorus doping, and using a chemical solution to remove the phosphorus-doped layers that are plated around the front and sides; Putting the third silicon wafer into a KOH solution or NaOH solution containing additives to react, then putting the silicon wafer into a mixed solution of KOH or NaOH and H2O2 for cleaning, taking out the cleaned third silicon wafer and performing water washing to obtain a fourth silicon wafer; S4. ALD process: Introducing a gaseous substance containing an aluminum source into the reaction chamber. Gaseous Al3 first adsorbs on the surface of the silicon wafer, and then reacts with the water vapor introduced subsequently to generate aluminum hydroxide, which adheres to the surface of the fourth silicon wafer, and methane gas is generated at the same time. The reaction equation is: Al(CH3)3 + 3H2O → Al(OH)3 + 3CH4↑ Al(OH)3 will undergo a dehydration reaction to be converted into aluminum oxide. The reaction equation is: 2Al(OH)3→Al2O3+3H2O↑ By repeating the above reaction steps, a layer-by-layer alumina film will be formed on the surface of the fourth silicon wafer to obtain the fifth silicon wafer; S5. Silicon nitride coating: Through the reaction of SiI and NH, a dense SiNx film is deposited on the surface of the silicon wafer to obtain the sixth silicon wafer; S6. Screen printing and sintering: Positive and negative electrodes are fabricated on the surface of the sixth silicon wafer to conduct the current generated by the battery under light, realizing the electrical performance of the battery.

10. The production process of a back laser TOPCon battery structure according to claim 9, characterized in that, In step S5, the thickness of the SiNx film is 60 - 100 nm.

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