Topcon solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a Topcon solar cell, a preparation method thereof and a photovoltaic module. The Topcon solar cell includes: a silicon substrate having a front surface facing the sun during normal operation and a back surface opposite the front surface; the tunneling oxide layer is located on the back face of the silicon substrate and makes contact with the silicon substrate, and the thickness of the tunneling oxide layer ranges from 2.15 nm to 2.3 nm. Therefore, when the Rs performance of the battery is improved, the efficiency of the battery is not greatly lost, the weak light response of the TOPCon battery is finally improved, the overall weak light response of the battery is improved by 1%-5%, and the actual generating capacity of the solar battery can be increased and the application scene of the solar battery can be widened in partial areas with insufficient sunlight or cloudy and rainy areas.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and in particular, to Topcon solar cells, their preparation methods, and photovoltaic modules. Background Art

[0002] Topcon (Tunnel Oxide Passivated Contact) cells have an excellent passivated contact structure, and the cell efficiency is higher than that of Perc cells (Passivated Emitter Rear Cell). One of the reasons why Topcon cells can have excellent efficiency is that their Rs (series resistance) is extremely low. However, a low Rs will ultimately lead to poor low-light response of the cell. On rainy days or in the morning and evening, its power generation is less than expected.

[0003] Therefore, the current solar cells, their preparation methods, and photovoltaic modules still need to be improved. Summary of the Invention

[0004] This application is made based on the inventor's discovery and recognition of the following facts and problems:

[0005] Based on the single-diode model of photovoltaic cells, Rs and Rsh are the main factors affecting the low-light response of the cell. The higher Rs and Rsh are, the better the low-light response. Rs and Rsh are the characteristic resistances of the cell, which are the series resistance and the shunt resistance respectively.

[0006] For Topcon cells, the thickness of the thin tunneling layer can be <1 nm, and the tunneling effect of electrons is relatively good, and the electron tunneling probability is 2.04%. However, a thinner tunneling layer will increase the difficulty of process control because the doping elements of doped polysilicon will inevitably diffuse into the silicon substrate through the tunneling layer, and the thinner tunneling layer is easily damaged during the internal diffusion process, thereby reducing the passivation effect of the tunneling layer on the silicon substrate; however, when the thickness of the tunneling layer increases to 2 nm, the electron tunneling probability decreases to 0.05% at this time, and the tunneling probability decreases by 98% compared with when the thickness is less than 1 nm. Therefore, in order to improve the tunneling probability of carriers and at the same time protect the tunneling layer from being damaged by internal diffusion impurities and its passivation effect, the thickness of the tunneling layer of existing Topcon cells that mainly use the tunneling function to transport carriers is usually controlled at about 1.5 nm as much as possible.

[0007] There are also studies showing that when the thickness of the tunneling layer exceeds 2 nm, after the thickness of the tunneling layer increases, this film layer becomes a doped dielectric layer, which still has a very small tunneling effect, but its transmission is more inclined to Ohm's law, that is, it acts as a conductor with a specific resistivity. Therefore, at present, the thickness of the tunneling layer in some Topcon cell technologies is set to be greater than 2 nm, and the tunneling layer dielectric layer effect is used to transport carriers. However, if the thickness of the tunneling layer is too thick, it will cause a sharp drop in the FF (fill factor) of the cell, and ultimately lead to a cliff-like drop in the efficiency of the cell.

[0008] In addition, the inventors found that there is a certain relationship between the Rs of the cell and the thickness of the tunneling oxide layer of the Topcon cell. The relationship curve of the contact resistivity of the simulated solar cell varying with the thickness of the tunneling oxide layer is as Figure 4 shown. When the thickness of the tunneling oxide layer is too thin (1 nm - 1.5 nm), the contact resistivity is very low, and its Rs will also be very low, which has a greater impact on the low-light effect of the cell. When the thickness of the tunneling oxide layer exceeds a certain thickness (2.25 nm), the contact resistivity begins to increase sharply, and its Rs will also increase sharply.

[0009] The increase in Rs is bound to lead to a decrease in FF (fill factor), and ultimately affect the photoelectric conversion efficiency of the photovoltaic cell. The relationship curve of the efficiency of the simulated solar cell (normalized with the efficiency when the thickness of the tunneling oxide layer is 1 nm as the reference) varying with the thickness of the tunneling oxide layer is as Figure 5 shown. When the thickness of the tunneling oxide layer is in the range of 2.3 nm - 2.5 nm, the FF of the cell drops sharply, resulting in a rapid drop in the efficiency of the cell.

[0010] Therefore, by controlling the thickness of the tunneling oxide layer, without affecting the carrier transport of the tunneling oxide layer and the passivation of the silicon substrate, the series resistance Rs of the cell can be effectively controlled, thereby improving the low-light effect of the cell and the overall power generation efficiency of the cell.

[0011] If it is possible to make up for the efficiency reduction caused by the increase in Rs as much as possible while the contact resistance increases, then the low-light response can be improved while ensuring that the cell efficiency will not be lost too much, thereby increasing the actual power generation of the photovoltaic module and broadening the application scenarios of the photovoltaic module.

[0012] This application aims to alleviate or solve at least one of the above-mentioned problems to at least a certain extent.

[0013] In one aspect of the present application, the present application provides a Topcon solar cell. In some embodiments of the present application, the Topcon solar cell includes: a silicon substrate having a front face facing the sun during normal operation and a back face opposite to the front face; a tunneling oxide layer located on the back face of the silicon substrate and in contact with the silicon substrate, the thickness of the tunneling oxide layer being 2.15 nm - 2.3 nm. Thus, while improving the Rs performance of the cell, the cell efficiency does not have much loss, ultimately playing a role in improving the low-light response of the Topcon cell, increasing the overall low-light response of the cell by 1% - 5%. In some areas where sunlight is insufficient or there are many rainy days, the actual power generation of the solar cell can be increased, and the application scenarios of the solar cell can be broadened.

[0014] In some embodiments of the present application, the Topcon solar cell further includes an N-type polysilicon layer located on the back face of the silicon substrate and on the side of the tunneling oxide layer away from the silicon substrate. Thus, the passivation effect of the solar cell can be improved, and the recombination of carriers at the interface can be reduced.

[0015] In some embodiments of the present application, the thickness of the N-type polysilicon layer is 110 nm - 120 nm.

[0016] In some embodiments of the present application, the sheet resistance of the Topcon solar cell is 40 Ω / sq - 50 Ω / sq.

[0017] In some embodiments of the present application, the series resistance of the Topcon solar cell is 0.0010 Ω - 0.0012 Ω. Thus, the series resistance of the solar cell is relatively large, which is beneficial to improving the low-light response of the solar cell.

[0018] In some embodiments of the present application, the open-circuit voltage of the Topcon solar cell ≥ 0.745 V. Thus, it is beneficial to reduce the loss of cell efficiency and make the cell have a relatively high overall power generation.

[0019] In some embodiments of the present application, the Topcon solar cell further includes: an antireflection layer on the front face, the antireflection layer on the front face being located on the front face of the silicon substrate; a passivation layer on the front face, the passivation layer on the front face being located between the antireflection layer on the front face and the silicon substrate; an antireflection layer on the back face, the antireflection layer on the back face being located on the side of the N-type polysilicon layer away from the silicon substrate; a passivation layer on the back face, the passivation layer on the back face being located between the antireflection layer on the back face and the N-type polysilicon layer. Thus, it is beneficial to reduce the reflection of light and improve the utilization rate of sunlight by the solar cell; it is beneficial to improve the passivation effect, thereby being beneficial to further improving the performance of the solar cell.

[0020] In another aspect of the present application, the present application provides a method for manufacturing the aforementioned Topcon solar cell. In some embodiments of the present application, the method for manufacturing the aforementioned Topcon solar cell includes: oxidizing the surface of the silicon substrate to form a tunneling oxide layer, and the step of forming the tunneling oxide layer satisfies the following conditions: the flow rate of oxygen is 27,000 sccm - 36,000 sccm, the temperature is 590°C - 615°C, the process time for introducing oxygen is 500 s - 1,800 s, and the tube annealing time is 300 s - 1,000 s. Thus, it is beneficial to form a tunneling oxide layer with a relatively thick thickness and high film quality.

[0021] In some embodiments of the present application, the method for manufacturing the aforementioned Topcon solar cell further includes: forming a polysilicon layer on the side of the tunneling oxide layer away from the silicon substrate; performing a phosphorus diffusion process to form an N-type polysilicon layer on the polysilicon layer. The phosphorus diffusion process includes a step of introducing a phosphorus source and a pushing step, and the phosphorus diffusion process satisfies the following conditions: during the process of introducing the phosphorus source, the flow rate of the phosphorus source is 900 sccm - 1,400 sccm, the temperature is 780°C - 830°C, and the process time is 960 s - 1,500 s; during the pushing process, the temperature is 860°C - 900°C, and the process time is 900 s - 1,300 s. If the thickness of the tunneling oxide layer increases and the phosphorus diffusion process is not adjusted, due to the decrease in FF (fill factor), the efficiency will decrease significantly. Eventually, the power generation of the battery will fall short of expectations; it is necessary to readjust the phosphorus diffusion process to match the tunneling oxide layer to bring out the passivation advantage of thickening the tunneling oxide layer to make up for the efficiency reduction caused by partial FF loss, and finally achieve the effect of increased power generation. By adjusting the phosphorus diffusion process in the present application, the passivation advantage of thickening the tunneling oxide layer can be brought out, making up for the efficiency loss caused by partial FF loss, thereby increasing the power generation.

[0022] In yet another aspect of the present application, the present application provides a photovoltaic module. In some embodiments of the present application, the photovoltaic module includes the aforementioned Topcon solar cell. Thus, the photovoltaic module has all the features and advantages of the aforementioned Topcon solar cell, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 shows a schematic structural diagram of a Topcon solar cell according to an embodiment of the present application;

[0025] Figure 2Shows a schematic structural diagram of a Topcon solar cell according to another embodiment of the present application;

[0026] Figure 3 Shows a schematic structural diagram of a Topcon solar cell according to yet another embodiment of the present application;

[0027] Figure 4 Shows a relationship curve of the contact resistivity of a simulated solar cell varying with the thickness of the tunneling oxide layer;

[0028] Figure 5 Shows a relationship curve of the efficiency of a simulated solar cell varying with the thickness of the tunneling oxide layer.

[0029] Description of reference numerals:

[0030] 10: Silicon substrate; 11: Front side; 12: Back side; 20: Tunneling oxide layer; 30: N-type polysilicon layer; 41: Front passivation layer; 42: Front antireflection layer; 51: Back passivation layer; 52: Back antireflection layer; 60: Front grid line; 70: Back grid line; 80: P-type doping layer. Detailed description of the specific implementation

[0031] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described by referring to the drawings below are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0032] In one aspect of the present application, the present application proposes a Topcon solar cell. In some embodiments of the present application, refer to Figure 1, The Topcon solar cell includes a silicon substrate 10 and a tunneling oxide layer 20. Among them, the silicon substrate 10 has a front surface 11 facing the sun during normal operation and a back surface 12 opposite to the front surface 11. The tunneling oxide layer 20 is located on the back surface 12 of the silicon substrate 10 and is in contact with the silicon substrate 10. The thickness h1 of the tunneling oxide layer 20 can be 2.15 nm - 2.3 nm. For example, the thickness h1 of the tunneling oxide layer 20 can be 2.15 nm, 2.18 nm, 2.2 nm, 2.23 nm, 2.25 nm, 2.27 nm or 2.3 nm. When the thickness of the tunneling oxide layer is within the above range, it can at least to some extent improve the series resistance Rs of the battery, thereby being beneficial to improving the low-light response of the battery, so that the battery can still have a high power generation under low-light conditions; and, while the Rs performance of the battery is improved, the battery efficiency will not have too much loss, ultimately playing a role in improving the low-light response of the Topcon battery, increasing the overall low-light response of the battery by 1% - 5%. In some areas with insufficient sunlight or many rainy days, it can increase the actual power generation of the solar cell and broaden the application scenarios of the solar cell. In places with sufficient sunlight, the solar cell also has a high power generation.

[0033] In some embodiments of the present application, the silicon substrate 10 can be an N-type silicon wafer.

[0034] In some embodiments of the present application, the tunneling oxide layer 20 can be a silicon oxide layer.

[0035] In some embodiments of the present application, refer to Figure 2 , The Topcon solar cell further includes an N-type polysilicon layer 30. The N-type polysilicon layer 30 is located on the back surface 12 of the silicon substrate 10 and is on the side of the tunneling oxide layer 20 away from the silicon substrate 10. Thus, the tunneling oxide layer and the polysilicon layer form a passivation contact structure, which can improve the passivation effect of the solar cell and reduce the recombination of carriers at the interface.

[0036] In some embodiments of the present application, the N-type polysilicon layer 30 is a phosphorus-doped polysilicon layer. In some embodiments, the doping concentration on the surface of the phosphorus-doped polysilicon layer can reach 3×10 20 / cm 3 .

[0037] In some embodiments of the present application, refer to Figure 2 , The thickness h2 of the N-type polysilicon layer 30 can be 110 nm - 120 nm. For example, the thickness h2 of the N-type polysilicon layer 30 can be 110 nm, 112 nm, 113 nm, 115 nm, 117 nm, 118 nm or 120 nm. The N-type polysilicon layer with the above thickness combined with the tunneling oxide layer can achieve a good passivation effect, thereby being beneficial to improving the overall performance of the solar cell.

[0038] In some embodiments of the present application, the sheet resistance of the Topcon solar cell can be 40 Ω / sq - 50 Ω / sq. For example, the sheet resistance of the solar cell can be 40 Ω / sq, 42 Ω / sq, 43 Ω / sq, 45 Ω / sq, 47 Ω / sq, 48 Ω / sq, or 50 Ω / sq. An increase in the thickness of the tunneling oxide layer will cause a relatively large increase in Rs. If the sheet resistance of the battery is relatively high (e.g., higher than 50 Ω / sq), the efficiency of the battery will decrease significantly. In the present application, the sheet resistance is relatively low, and the contact effect is better, which can improve the efficiency of the battery.

[0039] In some embodiments of the present application, the series resistance of the Topcon solar cell can be 0.0010 Ω - 0.0012 Ω. For example, the series resistance of the solar cell can be 0.0010 Ω, 0.001055 Ω, 0.001060 Ω, 0.001070 Ω, 0.001080 Ω, 0.001090 Ω, or 0.0012 Ω. When the series resistance of the solar cell is within the above range, it is beneficial to improve the low-light response effect of the solar cell, so that the solar cell can have a relatively high power generation in rainy or cloudy days with weak light.

[0040] In some embodiments of the present application, the open-circuit voltage of the Topcon solar cell can be ≥0.745 V. A relatively high open-circuit voltage of the solar cell is beneficial to reducing the loss of battery efficiency and enabling the battery to have a relatively high overall power generation.

[0041] In some embodiments of the present application, refer to Figure 3 , the Topcon solar cell includes a P-type doping layer 80, and the P-type doping layer is located on the side of the silicon substrate 10 away from the tunneling oxide layer 20. In some specific embodiments, the P-type doping layer is a boron-doped layer.

[0042] In some embodiments, the thickness of the P-type doping layer 80 can be 0.7 μm - 1.2 μm. For example, the thickness of the P-type doping layer 80 can be 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, or 1.2 μm.

[0043] In some embodiments of the present application, refer to Figure 3 , the Topcon solar cell may further include a front passivation layer 41 and a front antireflection layer 42. The front antireflection layer 42 is located on the front side of the silicon substrate 10, and the front passivation layer 41 is located between the front antireflection layer 42 and the silicon substrate 10. Specifically, the front antireflection layer 42 is located on the side of the P-type doping layer 80 away from the silicon substrate 10, and the front passivation layer 41 is located between the front antireflection layer 42 and the P-type doping layer 80.

[0044] In some specific embodiments, the front passivation layer 41 may include aluminum oxide (AlO x ), and the front antireflection layer 42 may include silicon nitride (SiN x ). In some other specific embodiments, the front antireflection layer 42 may be composed of a plurality of sub-layers arranged in a stack.

[0045] In some embodiments of the present application, referring to Figure 3 , the Topcon solar cell may further include a back passivation layer 51 and a back antireflection layer 52. The back antireflection layer 52 is located on the side of the N-type polysilicon layer 30 away from the silicon substrate 10, and the back passivation layer 51 is located between the back antireflection layer 52 and the N-type polysilicon layer 30. In some specific embodiments, the back passivation layer 51 may include aluminum oxide (AlO x ), and the back antireflection layer 52 may include silicon nitride (SiN x ). In some embodiments, the back antireflection layer 52 may be composed of a plurality of stacked silicon nitride sub-layers, and the refractive indices of the plurality of silicon nitride sub-layers are different.

[0046] Setting the front antireflection layer and / or the back antireflection layer is beneficial to reducing the reflection of light, improving the utilization rate of sunlight by the solar cell, and thus beneficial to increasing the power generation of the battery. Setting the front passivation layer and / or the back passivation layer is beneficial to improving the passivation effect of the solar cell, and thus beneficial to improving the performance of the solar cell.

[0047] In some embodiments of the present application, referring to Figure 3 , the Topcon solar cell further includes a front grid line 60 and a back grid line 70. The front grid line 60 is in contact with the P-type doped layer 80, and the back grid line 70 is in contact with the N-type polysilicon layer 30.

[0048] On the other hand of the present application, the present application proposes a method for manufacturing the aforementioned Topcon solar cell. In some embodiments of the present application, the method for manufacturing the aforementioned Topcon solar cell may include the following steps:

[0049] S10: Oxidize the surface of the silicon substrate to form a tunneling oxide layer.

[0050] The steps of forming the tunneling oxide layer satisfy the following conditions: the flow rate of oxygen is 27000 sccm - 36000 sccm, the temperature is 590 °C - 615 °C, the process time for introducing oxygen is 500 s - 1800 s, and the tube annealing time is 300 s - 1000 s. For example, the flow rate of oxygen can be 27000 sccm, 28000 sccm, 30000 sccm, 31000 sccm, 33000 sccm, 35000 sccm or 36000 sccm, the temperature for forming the tunneling oxide layer is 590 °C, 595 °C, 600 °C, 605 °C, 610 °C or 615 °C, the process time for introducing oxygen is 500 s, 700 s, 1000 s, 1200 s, 1500 s or 1800 s, and the tube annealing time is 300 s, 500 s, 600 s, 800 s or 1000 s. Under the above process conditions, a tunneling oxide layer with good consistency and high film quality can be formed. A larger flow rate of oxygen, a longer process time for introducing oxygen, and a longer tube annealing time can form a thicker tunneling oxide layer, and the thicker tunneling oxide layer will increase the contact resistivity, which is beneficial to increasing the series resistance Rs of the solar cell, thereby improving the low-light response of the solar cell and increasing the power generation of the solar cell under low-light conditions.

[0051] In some embodiments, during the process of forming the tunneling oxide layer, the temperature can be 610 °C - 615 °C.

[0052] In some embodiments, during the process of forming the tunneling oxide layer, the tube annealing time can be 730 s - 840 s.

[0053] In some embodiments, the tunneling oxide layer can be prepared by the LPCVD (Low Pressure Chemical Vapor Deposition) method.

[0054] In some embodiments of the present application, before forming the tunneling oxide layer, texturing, boron diffusion, removing the back BSG, and back polishing treatments can be performed first.

[0055] In some embodiments, the silicon substrate can be textured with an alkaline solution to form a double-sided textured structure on the silicon substrate. Among them, the alkaline solution can include H2O, NaOH, and texturing additives (such as isopropyl alcohol, sodium silicate, etc.).

[0056] In the boron diffusion step, a boron source (such as BCl3, etc.) is introduced into the equipment under high-temperature conditions, and then diffusion is carried out to dope part of the silicon substrate with boron to form a P-type doped layer. After that, an oxidation treatment is performed to form BSG (boron silicate glass) on the P-type doped layer.

[0057] During the boron diffusion and oxidation processes, a P-type doped layer and BSG are also formed on the back surface of the silicon substrate. The back BSG can be removed by a wet acid trough chain machine. In some specific embodiments, the temperature of the chain machine trough can be 40°C, the process time can be 40 s, and the solution is composed of H2O and HF in a volume ratio of 5:1; the PN junction formed by diffusion around the back and side surfaces can be removed by a trough type, the temperature of the alkali polishing trough can be 50°C to 75°C, the process time can be 300 s, and the alkali solution is composed of H2O, NaOH, and a polishing additive in a volume ratio of 300:18:5, where the concentration of NaOH is about 3%.

[0058] After removing the back BSG and the back polishing step, the back surface texture is removed. Then, a tunneling oxide layer is prepared on the back surface of the silicon substrate.

[0059] In some embodiments of the present application, the method for fabricating the Topcon solar cell described above further includes the following steps:

[0060] S20: A polysilicon layer is formed on the side of the tunneling oxide layer away from the silicon substrate.

[0061] In some embodiments of the present application, PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to form a polysilicon layer on the side of the tunneling oxide layer away from the silicon substrate.

[0062] In some embodiments of the present application, the deposition temperature of the polysilicon layer can be 590°C - 615°C, the process time can be 2000 s ± 300 s, and the silane flow rates in the three-stage gas inlet mode can be 190 sccm, 440 sccm, and 620 sccm respectively.

[0063] In some embodiments of the present application, the thickness of the polysilicon layer can be 145 nm ± 5 nm. For example, the thickness of the polysilicon layer can be 140 nm, 143 nm, 145 nm, 147 nm, 148 nm, 149 nm, or 150 nm.

[0064] S30: A phosphorus diffusion process is carried out to make the polysilicon layer form an N-type polysilicon layer (phosphorus-doped polysilicon layer).

[0065] In some embodiments of the present application, the phosphorus diffusion process includes the steps of introducing a phosphorus source and a pushing step. First, the phosphorus source is introduced, and then it is pushed.

[0066] In some embodiments of the present application, the phosphorus diffusion process satisfies the following conditions: During the process of introducing the phosphorus source, the flow rate of the phosphorus source is 900 sccm - 1400 sccm, the temperature is 780 °C - 830 °C, and the process time is 960 s - 1500 s. For example, the flow rate of the phosphorus source can be 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, 1300 sccm, or 1400 sccm; the temperature can be 780 °C, 790 °C, 800 °C, 810 °C, 820 °C, or 830 °C; and the process time for introducing the phosphorus source can be 960 s, 980 s, 1000 s, 1100 s, 1200 s, 1300 s, 1400 s, or 1500 s. During the pushing process, the temperature can be 860 °C - 900 °C, and the process time can be 900 s - 1300 s. For example, the pushing temperature can be 860 °C, 865 °C, 870 °C, 875 °C, 880 °C, 885 °C, 890 °C, 895 °C, or 900 °C; and the pushing process time can be 900 s, 950 s, 1000 s, 1050 s, 1100 s, 1150 s, 1200 s, 1250 s, or 1300 s. Thus, the polysilicon layer can be phosphorus-doped to form a phosphorus-doped layer, which is beneficial to improving the passivation effect of the polysilicon layer, and can, to at least a certain extent, prevent phosphorus from entering the silicon substrate. By adjusting the phosphorus diffusion process to match the tunneling oxide layer, the passivation advantage of thickening the tunneling oxide layer can be manifested, bringing a better passivation effect to make up for the efficiency loss caused by the decrease in the fill factor; and the open-circuit voltage can be improved to have an advantage to make up for the efficiency loss caused by the increase in the series resistance.

[0067] In some embodiments, during the process of introducing the phosphorus source, the flow rate of the phosphorus source can be 1200 sccm - 1400 sccm, the temperature can be 780 °C - 820 °C, and the process time can be 1050 s - 1400 s.

[0068] In some embodiments, during the pushing process of the phosphorus diffusion, the temperature can be 870 °C - 880 °C, and the process time can be 920 s - 1200 s.

[0069] After forming the N-type polysilicon layer, an oxidation treatment can be performed. In some embodiments, the oxidation temperature can be 870 °C, the flow rate of oxygen can be 1500 sccm - 3000 sccm, and the oxidation time can be 520 s - 540 s. Finally, an N-type polysilicon layer and PSG (phosphosilicate glass) layer stack structure (N-poly + PSG structure) is formed, where the thickness of the N-type polysilicon layer can be 110 nm - 120 nm, and the thickness of the PSG can be 45 nm - 55 nm. In this case, the sheet resistance measured by the off-line four-probe method is 40 Ω / sq - 50 Ω / sq.

[0070] In some embodiments, during the oxidation treatment process, the flow rate of oxygen can be 2100 sccm - 2300 sccm.

[0071] During the phosphorus diffusion and oxidation treatment processes, an N-type polysilicon layer and a PSG layer stack structure will also be formed on the front and side surfaces of the silicon substrate. The PSG formed by diffusion around the edges on the front and side surfaces can be removed by a wet bench, and the polysilicon overcoat deposited on the front and side surfaces, as well as the front BSG and the back PSG, can be removed by a wet alkaline bath and an acid bath. In some embodiments, the temperature of the wet bench tank can be 40 °C, the process time can be 30 s, and the acid solution is composed of H2O and HF in a volume ratio of 5:1. In some embodiments, the temperature of the alkaline etching bath can be 50 °C - 75 °C, the process time can be 300 s, and the alkaline solution can be composed of H2O, NaOH, and a polishing additive in a volume ratio of 300:18:5, where the concentration of NaOH is about 3%; the temperature of the acid bath can be 40 °C, the process time can be 120 s, and the acid solution is composed of H2O and HF in a volume ratio of 3:2.

[0072] In some embodiments of the present application, the method for manufacturing a Topcon solar cell further includes steps such as forming a front passivation layer and a front antireflection layer, forming a back passivation layer and a back antireflection layer, forming front grid lines, forming back grid lines, light injection, and testing and sorting.

[0073] In some embodiments of the present application, the alumina layer can be deposited by a back-to-back double-insertion method. The alumina layer is prepared by the ALD (Atomic Layer Deposition) method. The process temperature can be 300 °C, the process time can be 900 s, and the thickness of the formed alumina can be 3.3 nm - 5.3 nm.

[0074] In some embodiments, an alumina layer can be formed on the front and back surfaces of the silicon substrate, which can play a role in enhancing the passivation effect.

[0075] In some embodiments of the present application, after forming the alumina layer, a film can be coated on the surface of the front alumina layer away from the silicon substrate. In some specific embodiments, the temperature of the film coating process can be 540 °C, divided into 6 layers of films. The deposition sequence from the silicon substrate outwards is silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide. Among them, the difference between the silicon nitride and silicon oxynitride film layers is the refractive index. The thickness of each layer of film is between 10 nm - 25 nm, and the final overall thickness of the film layer is 70 nm - 80 nm, and the refractive index is 2.05 - 2.15. This film layer can play an antireflection role.

[0076] In some embodiments, after forming the aluminum oxide layer, a film can be coated on the surface of the aluminum oxide layer on the back side away from the silicon substrate. The coating process temperature can be 530 °C, and it can be divided into three layers of film. The deposition sequence from the silicon substrate outwards is silicon nitride 1, silicon nitride 2, and silicon nitride 3. Among them, the difference in the silicon nitride film layers is the refractive index. The thickness of each layer of film is between 10 nm and 30 nm, and the final overall film thickness is 78 nm - 80 nm, and the refractive index is 2.07 - 2.17.

[0077] In some embodiments of the present application, the front grid line and the back grid line can be formed by screen printing. In some embodiments, by screen printing, metal grid lines are formed on the front and back sides. After high-temperature sintering, an ohmic contact is formed between the metal and the silicon substrate to collect and conduct the current. Generally, through a four-pass printing method, the first pass prints the back main grid, and the number of main grid lines is 9 - 24; the second pass prints the back fine grid, the number of fine grid lines is 150 - 250, and the width of the fine grid line is 4 μm - 13 μm; the third pass prints the front main grid, the number of main grid lines is 9 - 24; the fourth pass prints the front fine grid, the number of fine grid lines is 150 - 250, and the width of the fine grid line is 4 μm - 13 μm; the peak sintering temperature is generally 680 °C - 750 °C.

[0078] Generally speaking, by adjusting the thickness of the silicon oxide and the phosphorus diffusion process in the present application, while improving the performance of the parallel resistance Rs of the battery, the battery efficiency will not have too much loss. Finally, it plays a role in improving the low-light response of the Topcon battery, and the overall low-light response is improved. In some areas with insufficient sunlight or many rainy days, the actual power generation of the solar cell can be increased, and the application scenario of the solar cell can be broadened.

[0079] The present application will be described below through specific embodiments. Those skilled in the art can understand that the following specific embodiments are only for the purpose of illustration and do not limit the scope of the present application in any way. In addition, in the following embodiments, unless otherwise specified, the materials and equipment used are commercially available. If the specific processing conditions and processing methods are not clearly described in the following embodiments, the conditions and methods known in the art can be used for processing.

[0080] Embodiment 1

[0081] In Embodiment 1, an N-type silicon wafer is selected as the silicon substrate.

[0082] 1. Texturing: The alkaline solution for texturing is composed of H2O, NaOH, and a texturing additive in a volume ratio of 300:6:3, where the concentration of NaOH is 1%, the solution temperature is 70 °C, and the process time is 450 s; the silicon substrate is textured to form a double-sided textured surface structure;

[0083] 2. Boron diffusion: The three-step distributed diffusion method is adopted for boron diffusion. The boron diffusion temperatures are 830 °C (100 s), 840 °C (220 s), and 850 °C (225 s). The boron source used for boron diffusion is BCl3, the flow rate of the boron source is 160 sccm, the pushing temperature is 880 °C (600 s); the oxidation temperature is 1045 °C, the oxygen flow rate is 32000 sccm, and the oxidation time is 3800 s, finally forming a PN junction;

[0084] 3. Removal of backside BSG and backside polishing: The backside BSG is removed by a wet acid trough chain machine, and the PN junction formed by diffusion around the backside and sides is removed by a trough type; the temperature of the chain machine trough body is 40 °C, the process time is 40 s, and the solution is composed of H2O and HF in a volume ratio of 5:1; the temperature of the alkali polishing trough is 50 - 75 °C, the process time is 300 s, and the alkali solution is composed of H2O, NaOH, and a polishing additive in a volume ratio of 300:18:5, where the concentration of NaOH is about 3%;

[0085] 4. LPCVD: The oxygen flow rate for preparing the tunneling oxide layer is 36000 sccm, the temperature is 610 °C, the oxygen passing process time is 900 s, and the tube baking time is 730 s, which can prepare an oxide layer with near-ohmic characteristics. The deposition temperature of the polysilicon layer is 590 - 615 °C, the process time is 2000 ± 300 s, and the silane flow rates for the three-stage gas inlet are 190 sccm, 440 sccm, and 620 sccm respectively; finally, the thickness of the formed SiO2 is 2.15 nm, and the thickness of the polysilicon layer is 145 nm;

[0086] 5. Phosphorus diffusion: The phosphorus source amount for the source passing step of phosphorus diffusion is 1200 sccm, the temperature is 780 °C, and the process time is 1050 s; the temperature for the pushing step is 920 °C, and the pushing process time is 900 - 1300 s, converting the polysilicon layer into a doped polysilicon layer, and the doping concentration on the surface of the doped polysilicon layer reaches 3×10 20 / cm 3 ; the oxidation temperature is 870 °C, the oxygen flow rate is 2100 sccm, and the oxidation time is 520 s; finally, an N-poly+PSG structure is formed, where the thickness of N-poly is 115 nm and the thickness of PSG is 50 nm;

[0087] 6. Removal of front PSG and RCA: The front and side PSG formed by diffusion are removed through a wet bench machine. The poly wrap plating deposited on the front and side is removed through a wet alkaline tank and an acid tank, as well as the front BSG and the back PSG. The temperature of the bench machine tank is 40°C, the process time is 30s, and the acid solution is composed of H2O and HF in a volume ratio of 5:1. The temperature of the alkaline polishing tank is 50 - 75°C, the process time is 300s, and the alkaline solution is composed of H2O, NaOH, and a polishing additive in a volume ratio of 300:18:5, where the concentration of NaOH is approximately 3%. The temperature of the acid tank is 40°C, the process time is 120s, and the acid solution is composed of H2O and HF in a volume ratio of 3:2.

[0088] 7. ALD: Deposit an alumina layer by the back-to-back double insertion method. The ALD process temperature is 300°C, the process time is 900s, and the thickness of the formed alumina is 4.3nm.

[0089] 8. Front film: The coating process temperature is 540°C, divided into 6 layers of film. The deposition sequence from the silicon substrate outwards is silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide. The difference between the silicon nitride and silicon oxynitride film layers lies in the refractive index. The thickness of each layer of film is between 10 - 25nm, and the final overall film thickness is 75 ± 5nm, with a refractive index of 2.10 ± 0.05.

[0090] 9. Back film: The coating process temperature is 530°C, divided into 3 layers of film. The deposition sequence from the silicon substrate outwards is silicon nitride 1, silicon nitride 2, silicon nitride 3. The difference between the silicon nitride film layers lies in the refractive index. The thickness of each layer of film is between 10 - 30nm, and the final overall film thickness is 84 ± 6nm, with a refractive index of 2.12 ± 0.05.

[0091] 10. Screen printing: Through the screen printing method, metal grid lines are formed on the front and back. After high-temperature sintering, the metal grid lines form an ohmic contact with the silicon substrate to collect and conduct current.

[0092] Example 2

[0093] The difference between Example 2 and Example 1 is shown in Table 1, and the thickness of the tunneling oxide layer is 2.2nm. The remaining steps and parameters are the same as those in Example 1.

[0094] Example 3

[0095] The difference between Example 3 and Example 1 is shown in Table 1, and the thickness of the tunneling oxide layer is 2.3nm. The remaining steps and parameters are the same as those in Example 1.

[0096] Comparative Example 1

[0097] The differences between Comparative Example 1 and Example 1 are shown in Table 1, and the thickness of the tunneling oxide layer is 2.1 nm. The remaining steps and parameters are the same as those in Example 1.

[0098] Comparative Example 2

[0099] The differences between Comparative Example 2 and Example 1 are shown in Table 1, and the thickness of the tunneling oxide layer is 2.4 nm. The remaining steps and parameters are the same as those in Example 1.

[0100] Comparative Example 3

[0101] The differences between Comparative Example 3 and Example 1 are shown in Table 1, and the thickness of the tunneling oxide layer is 2.5 nm. The remaining steps and parameters are the same as those in Example 1.

[0102] Comparative Example 4

[0103] The differences between Comparative Example 4 and Example 1 are shown in Table 1, and the thickness of the tunneling oxide layer is 2.6 nm. The remaining steps and parameters are the same as those in Example 1.

[0104] Comparative Example 5

[0105] The differences between Comparative Example 5 and Example 1 are shown in Table 1, and the thickness of the tunneling oxide layer is 2.8 nm. The remaining steps and parameters are the same as those in Example 1.

[0106] Table 1

[0107]

[0108] In Table 1, the samples with the tunneling oxide layer thicknesses of 2.1 nm, 2.15 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, and 2.8 nm correspond to Comparative Example 1, Example 1, Example 2, Example 3, Comparative Example 2, Comparative Example 3, Comparative Example 4, and Comparative Example 5, respectively.

[0109] The thicknesses of the tunneling oxide layer and polysilicon layer deposited by LPCVD, the thickness of phosphorus diffusion, the sheet resistance, and the remaining polysilicon layer thickness after wet treatment in each example and comparative example are shown in Table 2. Among them, the sheet resistance in Table 2 was measured by the off-line four-probe method after the formation of the PSG layer.

[0110] Table 2

[0111]

[0112] After printing the front and back grid lines, the electrical properties of the solar cells in each example and comparative example were tested, and the test results were recorded in Table 3.

[0113] Table 3

[0114]

[0115] In Table 3, Eta is the photoelectric conversion efficiency, Uoc is the open-circuit voltage, Isc is the short-circuit current, FF is the fill factor, Rs is the series resistance, Rsh is the parallel resistance, and IRev2 is the reverse current (which can also be called the leakage current).

[0116] As can be seen from Table 3, compared with Comparative Example 1, the photoelectric conversion efficiency of the solar cells in Examples 1-3 is slightly reduced, the open-circuit voltage increases, and Rs increases.

[0117] The experimental results show that a tunneling oxide layer with a suitable thickness is more likely to achieve a better open-circuit voltage advantage. Compared with a conventional TOPCon cell with a thinner thickness, the open-circuit voltage in Examples 1-3 can be increased by 2 mV or even 3 mV. Finally, FF is reduced by about 0.5%, and the photoelectric conversion efficiency is not significantly reduced. Taking Example 2 as an example, compared with Comparative Example 1, the open-circuit voltage of Example 2 is increased by 3.2 mV, and Rs is increased by 0.32 mΩ, which can effectively enhance the low-light response of the TOPCon cell.

[0118] In Comparative Examples 2-5, the thickness of the tunneling oxide layer is too large. Compared with Comparative Example 1, Rs in Comparative Examples 2-5 is further increased, but the fill factor is significantly reduced, and the photoelectric conversion efficiency of the solar cell is significantly decreased, which will significantly reduce the power generation of the solar cell on sunny days. The solar cells in Comparative Examples 2-5 are difficult to meet the usage requirements.

[0119] The power generation of the solar cells of each example and comparative example on sunny days and rainy days was tested, and the test results are recorded in Table 4.

[0120] Table 4

[0121]

[0122]

[0123] As can be seen from Table 4, compared with Comparative Example 1, the power generation of the solar cells in Examples 1-3 is slightly reduced on sunny days, but the power generation on rainy days is significantly increased. It can increase the power generation of the solar cell in an environment with more rainy days, and can also maintain a high power generation in an environment dominated by sunny days. In Comparative Example 2, the thickness of the tunneling oxide layer is large, and the power generation of the solar cell on sunny days is significantly reduced. Although the power generation on rainy days is increased to a certain extent compared with Comparative Example 1, the overall power generation is reduced.

[0124] In the description of the present application, the orientation or positional relationship indicated by terms such as "front" and "back" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and does not require the present application to be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0125] In the description of this specification, the descriptions referring to the terms "one embodiment", "another embodiment", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment are included in at least one embodiment of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples. Additionally, it should be noted that in this specification, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0126] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application.

Claims

1. A Topcon solar cell, characterized in that, Comprising: A silicon substrate having a front face facing the sun during normal operation and a back face opposite to the front face; A tunneling oxide layer located on the back face of the silicon substrate and in contact with the silicon substrate, the thickness of the tunneling oxide layer being 2.15 nm - 2.3 nm.

2. The Topcon solar cell according to claim 1, wherein It further includes an N-type polysilicon layer located on the back face of the silicon substrate and on the side of the tunneling oxide layer away from the silicon substrate.

3. The Topcon solar cell according to claim 2, wherein, The thickness of the N-type polysilicon layer is 110 nm - 120 nm.

4. The Topcon solar cell according to claim 2, wherein, The sheet resistance of the Topcon solar cell is 40 Ω / sq - 50 Ω / sq.

5. The Topcon solar cell according to claim 2, characterized in that, The series resistance of the Topcon solar cell is 0.0010 Ω - 0.0012 Ω.

6. The Topcon solar cell according to claim 2, wherein The open-circuit voltage of the Topcon solar cell is ≥ 0.745 V.

7. The Topcon solar cell according to any one of claims 2-6, characterized in that, It further includes: A front antireflection layer located on the front face of the silicon substrate; A front passivation layer located between the front antireflection layer and the silicon substrate; A back antireflection layer located on the side of the N-type polysilicon layer away from the silicon substrate; A back passivation layer located between the back antireflection layer and the N-type polysilicon layer.

8. A method for preparing a Topcon solar cell according to any one of claims 1-7, characterized in that, Including: oxidizing the surface of the silicon substrate to form a tunneling oxide layer, The steps of forming the tunneling oxide layer satisfy the following conditions: the flow rate of oxygen is 27000 sccm - 36000 sccm, the temperature is 590 °C - 615 °C, the process time for introducing oxygen is 500 s - 1800 s, and the tube annealing time is 300 s - 1000 s.

9. The method according to claim 8, wherein It further includes: Forming a polysilicon layer on the side of the tunneling oxide layer away from the silicon substrate; Performing a phosphorus diffusion process to form the polysilicon layer into an N-type polysilicon layer, the phosphorus diffusion process including a step of introducing a phosphorus source and a pushing step, and the phosphorus diffusion process satisfies the following conditions: During the process of introducing the phosphorus source, the flow rate of the phosphorus source is 900 sccm - 1400 sccm, the temperature is 780 °C - 830 °C, and the process time is 960 s - 1500 s; during the pushing process, the temperature is 860 °C - 900 °C, and the process time is 900 s - 1300 s.

10. A photovoltaic module, characterized in that, Including the Topcon solar cell according to any one of claims 1 - 7.

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