Detecting power line carrier presence in branch circuit and improving AF detection and detrimental trip in CAFI / DF circuit breaker

Abstract

Methods and systems are provided for detecting the presence of an arc fault signal on a circuit of a power distribution system. The method and system may include sampling a signal that measures electrical activity on a circuit, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal including a plurality of sample segments; for each sample segment, calculating segment attributes including a signal-to-noise ratio and a root mean square; generating a pattern representing the presence of any signal transition within a signal sample period of the sampled signal according to the calculated segment attribute of each sample segment of the sampled signal; and determining the presence of an arc fault signal based on the generated pattern and a predetermined pattern of PLC activity on the circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of U.S. Non - Provisional Patent Application Serial No. 18 / 233,035, filed on August 11, 2023, and U.S. Provisional Patent Application Serial No. 63 / 435,823, filed on December 29, 2022. The entire disclosure of the above - mentioned prior U.S. patent applications is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to fault detection in a power distribution system, and more particularly, to methods and systems for performing fault detection on a power distribution system where power line carrier communication can be implemented. Background Art

[0004] The use of power line carrier (PLC) modules has become popular in many applications in homes. These PLC modules are an effective way to provide fast internet speeds without the need for a wired network or extending WiFi coverage through multiple access points. They utilize the AC network in the home to provide high - speed internet communication between connected devices. Since these devices operate in the high - frequency range of 1.8 MHz to 27 MHz, they may cause harmful tripping or blind AF detection in certain AFCI devices, thereby reducing their efficiency. Summary of the Invention

[0005] According to one embodiment, there are provided methods and systems including: sampling a signal that measures electrical activity on a circuit of a power distribution system, the sampled signal corresponding to the signal strength of the electrical activity on the circuit, the sampled signal including a plurality of sample segments; for each sample segment, calculating segment attributes including signal - to - noise ratio (SNR) and root mean square (RMS); based on the calculated segment attributes of each sample segment of the sampled signal, generating a pattern representing the presence of any signal transitions within a signal sample period of the sampled signal; and determining the presence of an arc - fault signal based on the generated pattern and a predetermined pattern of PLC activity on the circuit.

[0006] In various embodiments, the methods and systems further include determining the presence of power line carrier (PLC) activity on the circuit. Calculating the segment attributes is at least responsive to the presence of power line carrier activity on the circuit.

[0007] In various embodiments, the generating operation may include: assigning one of a positive value, a negative value, or a zero value based on the calculated SNR and / or RMS of each sample segment compared to a corresponding segment - attribute threshold; creating a first binary word to reflect any positive - vector representation over the plurality of sample segments; creating a second binary word to reflect any negative - vector representation over the plurality of sample segments; and applying an XNOR (exclusive NOR) function to the first and second binary words to create a third binary word of the sampled signal.

[0008] In various embodiments, the pattern may include a binary word. The generated pattern may be a binary word having a side region reflecting potential side transitions and a center region reflecting potential center transitions. When the side transitions of the generated pattern have non-zero values and decrease to zero values in the center transitions of the generated pattern, the presence of an arc fault signal may be determined. The side transitions with non-zero values may represent transitions captured near the zero crossings around the arc ignition and extinction regions, while the intermediate transitions with zero values may represent PLC communication.

[0009] In various embodiments, the determination may include analyzing the values of the side transitions / regions and the center transitions / regions from a third binary word to detect the presence of an arc fault signal.

[0010] In various embodiments, the method and system may further include: determining one or more patterns of PLC activity on the circuit, the pattern of PLC activity including at least the pattern of a PLC beacon; and storing the one or more patterns as one or more of the predetermined patterns of PLC activity.

[0011] In various embodiments, the method and system may further include: in response to detecting the absence of PLC activity, performing fault detection by comparing the signal strength of high-frequency signals within the electrical activity including voltage or current with a set of dynamic thresholds.

[0012] In various embodiments, PLC activity may include a PLC beacon or PLC communication. The sampled signal may include an RSSI (Received Signal Strength Indicator) signal, which may be generated by a logarithmic amplifier device based on the electrical signals monitored by at least one high-frequency sensor on a branch circuit. Each sample segment of the sampled signal may have the same length including the semi-cyclic signal length.

[0013] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory and do not limit the invention disclosed or claimed. The claims should be accorded their full scope, including equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The description of various example embodiments is explained in conjunction with the accompanying drawings.

[0015] Figure 1 An example of a block diagram of an arc detection system for detecting an arc fault signal and / or power line carrier (PLC) communication on a distribution system in accordance with an embodiment of the present disclosure is shown.

[0016] Figure 2Shows a high - level flowchart of an example arc - fault detection process according to an embodiment of the present disclosure, by which an arc - fault signal is detected on a power distribution system or a part thereof.

[0017] Figure 3 Shows a flowchart of an example process of an arc - fault detection process according to an embodiment of the present disclosure, by which sample segments of a sampled signal are assigned representative values to generate a positive vector and a negative vector for arc - fault detection analysis.

[0018] Figure 4 Shows a flowchart of an example process of an arc - fault detection process according to an embodiment of the present disclosure, by which the presence of a PLC is detected and a PLC presence flag is set.

[0019] Figure 5 Shows a flowchart of an example process of an arc - fault detection process according to an embodiment of the present disclosure, by which an arc - fault signal is detected on a power distribution system or a part thereof.

[0020] Figure 6 Shows an example of vector assignment for a sampled segment of a signal within a signal period according to one embodiment.

[0021] Figure 7 Shows an example of vector assignment for a sampled segment of a signal within a signal period according to one embodiment.

[0022] Figure 8A Shows a functional block diagram of an example process according to one embodiment, by which the positive vector and the negative vector of segment samples on a signal period are processed to detect an arc - fault signal on a power distribution system.

[0023] Figure 8B Shows a functional block diagram of an example process according to one embodiment, by which the positive vector and the negative vector of segment samples on a signal period are processed to detect an arc - fault signal on a power distribution system.

[0024] Figure 9A Shows an example of vector assignment for a sampled segment of a signal within a signal period with respect to a PLC signal according to one embodiment.

[0025] Figure 9B Shows an example of vector assignment for a sampled segment of a signal within a signal period with respect to a PLC signal according to one embodiment.

[0026] Figure 9C Shows an example of vector assignment for a sampled segment of a signal within a signal period with respect to a PLC beacon according to one embodiment.

[0027] Figure 10Shows an example PLC beacon that converts 4-HC (half-cycle) in an AC network to a 4-byte pattern in Example Group A according to one embodiment.

[0028] Figure 11 Shows an example PLC beacon that converts 4-HC (half-cycle) in an AC network to a 4-byte pattern in Group B according to one embodiment.

[0029] Figure 12 Shows an example graph that shows side and center transitions related to a PLC according to one embodiment.

[0030] Figure 13 Shows an example diagram that shows side and center transitions related to a PLC and an arc fault signal according to one embodiment. Detailed Description

[0031] Methods and systems are provided for detecting power line carriers in a power distribution system and improving arc fault (AF) detection and load interoperability based on the high-frequency envelope of a monitoring signal. The methods and systems can be based on the envelope of a high-frequency signal (e.g., demodulating and amplifying in a logarithmic scale signal). Such a baseband signal can consist of much lower frequencies (e.g., <100KHz), which can be sampled at a lower rate.

[0032] The sampled signal strength (e.g., received signal strength indication or RSSI signal) of a monitored signal on a power distribution system (or a part thereof) can be segmented. Each segment sample can be analyzed based on a signal-to-noise ratio (SNR) value. The methods and systems can detect the presence of a PLC signal and a PLC synchronization pattern within a specific amount of time. Once such a detection is established, the methods and systems can distinguish between an arc fault signal and a communication flow signal.

[0033] The methods and systems of the present disclosure can provide various benefits / advantages. For example, since the methods and systems can operate at a much lower sampling rate, the hardware requirements are simpler and the computational requirements are much lower. Thus, the methods and systems can allow for fast and low-cost computation and can achieve arc fault detection without compromising load interoperability.

[0034] In various embodiments, the methods and systems can rely on, for example, a specific power line carrier (PLC) signal signature that can be detected in the time domain (e.g., such as a PLC beacon and its occurrence within a specific amount of time). After obtaining signal strength samples (e.g., RSSI samples) within a signal cycle (e.g., half-cycle), these segment samples are grouped, and for each segment, the root mean square or RMS (e.g., RSSI RMS), minimum value, maximum value, SNR value, etc. are determined and these parameters are classified into a vector from two or more vectors (e.g., positive vector, negative vector, empty / zero vector, etc.).

[0035] In various embodiments, once the presence of the PLC is determined, both the positive and negative vectors are processed again to determine transitions within a signal period (e.g., a half-cycle). For example, using the XNOR function on the two binary words and extracting the transition byte shows where these transitions occur. The side transitions and the center transition can be dynamically correlated with arc faults and power line carrier signals, respectively. An arc fault can consist of transitions near the zero crossings around the arc ignition and extinction regions captured at the side transitions. The PLC stream can consist of transitions in the center region and the side regions. If an arc occurs during the PLC stream, then the center transition will be reduced to zero (0); thus, the AF flag can be set.

[0036] In various embodiments, the method and system can perform the determination of the noise floor, the maximum peak, and the SNR on the raw RSSI samples within a time period (e.g., a half-cycle). The method and system can divide the RSSI samples into multiple (N) equal-length segments and determine: [a] the segment RMS[i], SNR[i], and the dynamic threshold (TH[i]); [b] classify each segment with a positive or negative byte (1, -1, or 0), [c] create two parameter vectors for the positive and negative bytes; [d] convert these vectors into binary words; [e] calculate the exclusive NOR (XNOR) of the two binary words (positive and negative); and [f] create a transition word based on the XNOR result. The method and system can determine the patterns created from the positive and negative parameters from 4 to N half-cycles, determine the presence of the power line carrier beacon and PLC communication, determine the presence of an arc fault; and classify the arc fault half-cycle or PLC or high-frequency interference to improve the arc fault algorithm decision. In the case where an arc fault is determined to be present, the method and system can interrupt the power supply to the monitored and protected circuit through a tripping mechanism.

[0037] These and other example detection methods and systems of the present disclosure, and the features associated therewith, are shown and described in the accompanying drawings and appendices, which are hereby incorporated by reference in their entirety.

[0038] Figure 1FIG. 0 shows an example of a block diagram of an arc fault detection system 100 according to an embodiment. In this example, the arc fault detection system 100 may be implemented on a circuit breaker to monitor signals on the power line of the protected circuit 10. These signals may be high frequency (HF) signals. The circuit breaker may include a controller 110, a front end 122 having an RSSI device (or circuit) 124 to receive signals from a sensor 120 (such as a current sensor or other sensor for measuring electrical signals on the power line) and generate corresponding signal strength samples, etc., a memory 130, a communication interface / device 140 that communicates with a remote device via a communication medium, a user interface 150, a power supply 160 that powers the components of the circuit breaker, and a trip mechanism 170 that interrupts the power on the power line upstream of the protected circuit 10. The user interface 150 may include an on / off switch 152 (such as a handle), a push-to-talk (PTT) button 154 for testing the circuit breaker, and one or more LEDs or other indicators 156 or other circuit breaker information for indicating the status of the circuit breaker (such as on, off, reset, trip, etc.). The sensor 120 may be a current sensor, such as a Rogowski coil or other sensor for measuring signals on the power line, and may be an HF current sensor. The measured signal may be a high frequency signal or a signal within a frequency range for power line carrier (PLC) communication. The RSSI device 124 may be a logarithmic amplifier device.

[0039] In the circuit breaker, the front end 122 / RSSI circuit 124, the controller 110, and the memory 130 may operate together to provide an arc fault detection system that may be configured to detect arc fault signals and / or power line carrier communication on the power line, as described herein. The front end 122 may be configured to receive and monitor signals in a desired frequency region from the sensor 120 and provide a measurement of the signal strength of the monitored signal (such as an RSSI signal). The front end 122 may be an analog front end that may include a radio frequency (RF) receiver (including a bandpass filter), a signal strength indicator (such as an RSSI circuit), an A / D converter, a signal conditioning circuit, etc.

[0040] The controller 110 can be configured to implement various functions and features, including those related to arc fault detection and / or PLC detection, as described herein. The arc fault detection features can include, for example, detecting PLCs on the power lines of a power distribution system, calculating RMS and SNR and associated thresholds (e.g., dynamic thresholds) as well as the maximum (Max) and minimum (Min) values of each sampling segment (e.g., sampling RSSI segment) or other parameters, assigning representative values (e.g., vectors, etc.) to each segment, generating a pattern or its representation (e.g., binary word) for a set of segments; detecting an arc fault signal or other conditions based on the pattern or its representation, etc. In various embodiments, various operations and functions related to arc fault detection can be implemented on other processing circuits, such as ASICs or FPGAs or other processors, or implemented between other processing circuits / processors and the controller.

[0041] The controller 110 is also configured to initiate a circuit breaker tripping operation, which can interrupt the power on the power line via a tripping mechanism under certain conditions, including when an arc fault signal or the presence of other conditions is detected. The controller 110 is also configured to control other operations of the circuit breaker, including communication via the communication interface / device 140 (e.g., receiving or sending commands or status information / reports), performing operations based on actions input by a user through the user interface 150, such as outputting the status of the circuit breaker via the LED 156 or other output devices, and performing other operations of the circuit breaker related to arc fault detection and power interruption.

[0042] The memory 130 can store computer-executable code or programs or software that, when executed by the controller (or its processor), controls the operation of the circuit breaker, including arc fault detection and / or PLC detection operations and other circuit breaker operations, such as circuit interruption. The memory 130 can also store other data used by the circuit breaker or its components to perform the operations described herein. Other data can include, but is not limited to, RMS values, SNR values, maximum values, minimum values, thresholds, predefined patterns or signatures including power line carrier (e.g., PLC beacons or communications), other circuit breaker data, and other data discussed herein.

[0043] Figure 2 A high-level flowchart of an example of an arc fault detection process 200 according to an embodiment of the present disclosure is shown, by which an arc fault signal can be detected on a power distribution system or a part thereof. In various embodiments, the process 200 can operate on RSSI samples (e.g., raw RSSI samples) obtained for each half-cycle synchronized with the AC line voltage, and can classify the half-cycle as to whether there is an arc fault signal or a PLC or high-frequency interference noise. Figure 2 The flowchart shows an example of the main processing blocks and parameter creation for an improved arc fault detection process.

[0044] For example, the process 200 and the other processes below will be described with reference to one or more processors (also referred to herein as a processor or processors), which are configured to implement or control the various operations described herein.

[0045] The process 200 begins at block 210, where the processor obtains signal samples that reflect the electrical activity monitored on a circuit (e.g., a branch circuit) of the power distribution system. For example, the signal samples can be obtained periodically. In various embodiments, the signal samples can be raw RSSI samples obtained from each half-cycle synchronized with the line voltage (e.g., AC line voltage) on the monitored circuit. These samples can be grouped into N sample segments within a desired period for analysis.

[0046] At block 220, the processor processes the negative and positive vectors of the obtained signal samples.

[0047] For example, after obtaining a sample segment (e.g., RSSI samples), the processor can calculate the RMS, SNR, noise floor, and maximum peak. These samples can be grouped into N segments. Segment attributes, such as RMS, SNR, minimum and maximum values, and dynamic thresholds, can be determined for each segment for use in determining (e.g., determining, creating, calculating, etc.) vectors, i.e., positive and negative vectors.

[0048] At block 230, the processor determines the presence of power line carrier according to the decoding mode.

[0049] At block 240, the processor processes the transition vector. For example, the processor can process the positive and negative vectors of the signal samples to generate words, patterns, or other representative data from which to analyze the presence of any transitions.

[0050] At block 250, the processor performs arc fault detection. For example, the processor can detect the presence of an arc fault signal based on the presence of any transitions in the sample segment.

[0051] At block 260, the processor determines whether an arc fault (AF) or an AF signal has been detected. If not, the process 200 returns to block 210 to obtain more signal samples for analysis. Otherwise, at block 270, the processor can interrupt the power supply to the protected circuit. For example, the processor can control a tripping mechanism to open the contacts to interrupt the power flow to the protected circuit.

[0052] Various examples of the operations or functions performed by the process 200 will be described in more detail below with reference to Figure 3 、 4 and 5 and other figures.

[0053] In various embodiments, when no PLC presence is detected, the processor may be configured to use conventional or other detection methods to implement arc fault detection. For example, attributes of the sampled signal such as current or voltage may be compared with a threshold to detect the occurrence of an arc fault.

[0054] Figure 3 An example process 300 of an arc fault detection process according to an embodiment of the present disclosure is shown, by which a sampled segment of a sampled signal is assigned a representative value, and a positive vector and a negative vector for arc fault detection analysis are generated from the representative value. For example, after obtaining a sample segment (e.g., an RSSI sample), the processor may calculate the RMS, SNR, noise floor, and maximum peak, as well as any other segment / signal attributes. These samples may be grouped into N segments, and segment attributes such as RMS, SNR, dynamic threshold, etc. may be calculated for each segment to create two vectors, namely a positive vector and a negative vector. In various embodiments, a representative value of 1 (positive), -1 (negative), or 0 (zero) may be assigned to each segment based on the RMS and SNR. The positive vector may be generated based on positive values, and the negative vector may be generated based on negative values.

[0055] Process 300 begins at block 302, where the processor initializes radio frequency (RF) characteristics.

[0056] At block 304, the processor waits for a ZX interrupt.

[0057] At block 306, the processor obtains signal samples. For example, the signal samples may be RSSI samples of the electrical activity being monitored on a circuit.

[0058] At block 308, the processor calculates various attributes of the signal samples or the sampled signal segments. These attributes may include, for example, signal-to-noise ratio (SNR), root mean square (RMS), minimum (MIN), maximum (MAX), and other attributes to facilitate the detection of desired signals, including but not limited to PLC signals, arc fault signals, etc.

[0059] At block 310, the processor determines whether the SNR is greater than a first SNR threshold (e.g., threshold 1 or TH1). The SNR threshold may be the minimum or cutoff SNR required to process the sampled signal to perform various detection algorithms (or processes / methods) described herein. If not, process 300 returns to block 306 to obtain new signal samples. Otherwise, at block 312, the processor creates N segment samples.

[0060] At block 314, the processor calculates the SNR and RMS for each segment.

[0061] At block 316, for each segment, the processor determines whether the SNR of the segment is less than a second SNR threshold (e.g., SNR_segment < TH2). If the SNR of the segment is not less than the second SNR threshold, the processor clears the positive and negative vectors at block 318. Otherwise, if the SNR is less than the second SNR threshold, process 300 proceeds to block 320.

[0062] At block 320, the processor updates the segment threshold for each segment. For example, the segment threshold of a segment can be calculated based on the minimum value of the segment and the SNR of the segment. Thus, the segment threshold of each segment can be dynamic.

[0063] At block 322, for each segment, the processor determines whether the RMS of the segment is greater than an RMS threshold (e.g., RMS_segment > TH). If the RMS of the segment is not greater than the RMS threshold, the processor sets the negative vector (for the i-th element) at block 324. Otherwise, if the RMS of the segment is greater than the RMS threshold, the processor sets the positive vector (for the i-th element) at block 326.

[0064] Thus, process 300 can be used to generate positive and negative vectors (or their representations) for N segments of the sampled signal.

[0065] Figure 4 An example process 400 of an arc fault detection process according to an embodiment of the present disclosure is shown, by which the presence of a PLC is detected and a PLC presence flag is set.

[0066] Process 400 begins at block 402, where the processor sets a mode index (e.g., i = i % N, where N represents the number of segments in a time period, and where i = 1... N and represents the i-th sample segment).

[0067] At block 404, the processor converts the negative vector into a binary word.

[0068] At block 406, the processor determines whether the binary word is less than a threshold (e.g., TH3). If the binary word is less than the threshold, at block 408, the processor sets mode[i] to 0. Otherwise, if the binary word is greater than or equal to the threshold, the processor sets mode[i] to 1 at block 410.

[0069] In any case, process 400 then proceeds to block 412, where the processor then determines whether mode A or B can be determined. If not, then at block 414, the processor sets the mode count to zero (e.g., mode Count = 0). Then, at block 416, the processor decrements or reduces the timeout value of the PLC (e.g., PLC TimeOut value). At block 418, the processor determines whether the timeout value is equal to zero (e.g., TimeOut = 0). If the timeout is not equal to zero, process 400 returns to block 404. Otherwise, if the timeout value is equal to zero, the processor clears the power line carrier (PLC) presence flag, and process 400 returns to block 404.

[0070] Returning to block 412, if mode A or B is determined, the processor increments the mode count at block 422 (e.g., mode Count = mode Count + 1). At block 424, the processor determines whether the mode count is greater than a threshold, e.g., TH4. If the mode count is not greater than the threshold, process 400 proceeds to block 416. Otherwise, if the mode count is greater than the threshold, the processor sets the PLC presence flag at block 426. At block 428, the processor sets the timeout value (e.g., TimeOut value). Thereafter, process 400 returns to block 402.

[0071] Figure 5 An example process 500 of an arc fault detection process according to an embodiment of the present disclosure is shown, by which an arc fault signal is detected on a power distribution system or a part thereof. Process 500 provides a classification of the absence of PLC, the presence of PLC, or HF noise interference or arc fault markings, and an arc fault detection algorithm (also referred to as a process or method) uses this classification to determine whether to interrupt the power supply to a protected circuit.

[0072] Process 500 begins at block 502, where the processor converts the positive and negative vectors into binary words. For example, the binary word may include a first binary word based on the positive vector (e.g., for each segment, if positive, the binary value = 1, otherwise 0), and a second binary word based on the negative vector (e.g., for each segment, if negative, the binary value = 1, otherwise 0).

[0073] At block 504, the processor calculates the XNOR value of the first and second binary words to generate a third binary word (or XNOR binary word).

[0074] At block 506, the processor divides the XNOR binary word into two word transitions, e.g., side and center.

[0075] At block 508, the processor calculates the running minimum over N half - cycles of the center transition.

[0076] At block 510, the processor checks for the presence of the PLC. For example, at block 512, the processor accesses information on the value of the PLC presence flag and checks whether the PLC flag is = 1 (present) or = 0 (absent). If the PLC flag does not reflect the presence of the PLC, the process 500 proceeds to block 514 and determines that there is no PLC interference.

[0077] Otherwise, if at block 510 the PLC flag does indeed reflect the presence of the PLC, then at block 516, the processor determines whether the value of the side transition (TRX) is greater than zero (e.g., side TRX > 0). If at block 516 the value of the side transition is not greater than zero, the processor determines PLC or HF noise interference at block 518. If at block 516 the value of the side transition is greater than zero, the processor determines whether the center transition is equal to zero (e.g., center TRX = 0) at block 520. If at block 520 the value of the center transition is not equal to zero, the processor determines PLC or HF noise interference at block 518. Otherwise, if at block 520 the value of the center transition is equal to zero, the processor determines the presence of an arc fault (or its signal) and sets the arc fault flag at block 522 (e.g., AF Flag = 1).

[0078] Figure 6 An example 600 of vector allocation for a sampled segment of a signal within a half-cycle period according to an embodiment is shown. In Figure 6 it, two vectors, such as a positive vector and a negative vector, can be created for each signal period (e.g., half-cycle), and then processed again to create a pattern for determining the presence of a power line carrier or arc fault signal. In this example, an arc fault signal and corresponding positive and negative bytes are shown. The sampled segments are processed individually to determine a dynamic threshold Seg TH[i], where i = 1…N and N is the number of sampled segments. Based on the conditions satisfied by the threshold, each sampled segment is labeled as positive (1), negative (-1), or zero (0).

[0079] More specifically, as shown in the example of Figure 6 , for each sampled segment [i], SNR, RMS, Min, and Max can be determined (e.g., determined, calculated, worked out, derived, assigned, etc.), where i = 1…N and N is the number of segments of the defined signal period. The segment threshold (Seg TH) can be a dynamic threshold, and this dynamic threshold can be determined for each segment [i]. For example, the segment threshold can be represented by the following equation:

[0080] Seg TH i = RSSIMIN i +(Seg SNR i ) / 2,

[0081] where:

[0082] Seg TH is the segment threshold,

[0083] RSSIMIN is the minimum value of the segment,

[0084] Seg SNR is the SNR of the segment, and

[0085] i is the number of segments starting from 1…N, and

[0086] N is the number of segments in the defined signal period.

[0087] In various embodiments, the defined signal period can be a half cycle.

[0088] A value (or its representation) can be determined (e.g., determined, calculated, computed, derived, assigned, etc.) for each segment [i]. In this example, the value of each segment can be determined as follows:

[0089] · If the SNR of segment [i] is less than the SNR threshold (e.g., a second SNR threshold TH2 in dB), and if the RMS of segment [i] is greater than the segment threshold (e.g., Seg TH[i]), then the vector value of segment byte [i] is set to positive or 1.

[0090] · If the SNR of segment [i] is less than the SNR threshold, and if the RMS of segment [i] is not greater than the segment threshold, then the vector value of segment byte [i] is set to negative or -1.

[0091] · If the SNR of segment [i] is not less than the SNR threshold, then the vector value of segment byte [i] is set to zero or 0.

[0092] For the above method, it is desired that the total signal SNR is higher than a certain threshold TH1 so that the method processes and classifies the segments. Otherwise, both the positive and negative vectors can be initialized with some default values. For segments with SNR less than TH2, the determination of -1 or 1 is calculated, otherwise it is set to 0 (e.g., meaning a transition).

[0093] The segment vector can be divided into two positive and negative vectors and then converted into binary words. Each byte marked as 1 on the positive vector is marked as 0 on the negative vector, and each byte marked as -1 on the negative vector is marked as 1 in the negative word and 0 in the positive word. The two binary words can have the same bytes marked as zero (depicting the transition where SNR>TH2), but preferably they do not both have the same bytes set to 1.

[0094] In Figure 6In this example, the following word (or pattern) is determined to be: 01111110, for the sample segment within the defined signal period. This word can be further evaluated to generate a first binary word for the positive vector and a second binary word for the negative vector. The first binary word is 0111 1110b = 126d, and the second binary word is 0000 0000b = 0d. If PLC activity is detected, the XNOR function can be applied to the first and second binary words, which generates a third binary word 10 0000 01 (e.g., 10 01 for side transition, 0000 for center transition), indicating the potential transition pattern of the sampled signal. Figure 6 This pattern in Figure 6 will indicate the potential presence of an arc fault signal because the side transition is a non - zero value (e.g., greater than zero) and decreases to a center transition with a zero value that reflects PLC communication. In various embodiments, consecutive signal periods can be evaluated to confirm the presence of an arc fault signal.

[0095] Figure 7 Shows an example 700 of vector allocation for the sampled segment of a signal within a signal period according to one embodiment. As in Figure 6 the example in Figure 6 , for each sampled segment [i], SNR, RMS, Min, and Max can be determined (e.g., determined, calculated, computed, derived, allocated, etc.), where i = 1…N and N is the number of segments of the defined signal period. A value (or its representation) can be determined (e.g., determined, calculated, computed, derived, allocated, etc.) for each segment [i] based on SNR, RMS, Max, and Min.

[0096] In this example, the following word (or pattern) is determined to be: 0,1,1,1,1, - 1,1,1, for the sample segment within the defined signal period. This word can be further evaluated to generate a first binary word for the positive vector and a second binary word for the negative vector. The first binary word is 0111 1011b = 123d, and the second binary word is 0000 0100b = 4d. If PLC activity is detected, the XNOR function can be applied to the first and second binary words, which generates a third binary word 10 000000 (e.g., 10 00 for side transition, 0000 for center transition), indicating the potential transition pattern of the sampled signal. Figure 7 This pattern in Figure 7 will indicate the potential presence of an arc fault signal because the side transition is a non - zero value (e.g., greater than zero) and decreases to a center transition with a zero value, which reflects PLC communication. In various embodiments, consecutive signal periods can be evaluated to confirm the presence of an arc fault signal.

[0097] Figure 8A and 8BAn example process according to various embodiments is shown, by which the positive and negative vectors of segment samples on a signal period are processed to detect an arc fault signal on a power distribution system. For example, once the power line carrier flag is determined, the calculation of two new transition parameters can be performed. When both the positive word and the negative word have corresponding 0 values, this means that a transition has occurred due to a large SNR value. To extract where these transitions occur, first the two binary words are XNORed together, which will indicate on which segment the transition has occurred by marking the segment byte as 1.

[0098] Since these bytes describe the location of the transition, it is very important to divide these bytes into two regions (side regions and a central region). Since the AF signal has transitions at zero crossings, both side regions can contain transitions. However, due to the AF signal, it is less likely that the central region has many transitions, but transitions may also exist during power line carrier communication.

[0099] As Figure 8A shown, a functional block diagram 800 is provided to illustrate an example process according to an embodiment, by which the positive and negative vectors of segment samples on a signal period are processed to detect an arc fault signal on a power distribution system.

[0100] In this example, for each segment of the sampled signal, representative values -1, 1, 1, -1, -1, 1, 1, 0 have been determined as shown on the left side of Figure 8A . These values can be determined using, for example, the processes or operations described with respect to the above Figure 4 , 6 and 7. The positive and negative vectors can be determined (or updated) from these values and can be reflected as a first binary word and a second binary word respectively. In Figure 8A , the first binary word is 01100110 (positive vector / binary word) and the second binary word is 10011000 (negative vector / binary word). The XNOR (or XNOR) function 802 can be applied to the first and second binary words to generate a third binary word from which signal transitions (if any) can be identified. In this example, the third binary word is 00 0000 01 and can be divided into sub-words / regions, such as side regions and a central region (e.g., 00 / 0000 / 01). For example, the word for side transitions is 00 01b and the word for central transitions is 00 00b.

[0101] If there is PLC interference, the third binary word will reflect, for example, a side transition value greater than zero and a central transition value equal to zero, thus reflecting the presence of an arc fault signal.

[0102] As Figure 8BAs shown, a functional block diagram 850 is provided to illustrate an example process according to one embodiment, by which the positive and negative vectors of segment samples within a signal period are processed to detect an arc fault signal on a power distribution system.

[0103] In this example, for each segment of the sampled signal, representative values 0, -1, 1, -1, 1, 1, 1, -1 have been determined as shown on the left. These values can be determined using, for example, the processes or operations described with respect to the above Figure 4 and 6 and 7. The positive and negative vectors can be determined (or updated) from these values and can be reflected as a first binary word and a second binary word, respectively. In Figure 8B , the first binary word is 00101110 (positive vector / binary word) and the second binary word is 01010001 (negative vector / binary word). The exclusive-NOR (or XNOR) function 852 can be applied to the first and second binary words to generate a third binary word from which signal transitions (if any) can be identified. In this example, the third binary word is 10 0000 00 and can be divided into sub-words / regions, such as side regions and a center region (e.g., 10 / 0000 / 00). For example, the word for side transitions is 10 00b and the word for center transitions is 00 00b.

[0104] If there is PLC interference, the third binary word will reflect, for example, a side transition value greater than zero and a center transition value equal to zero, thus reflecting the presence of an arc fault signal.

[0105] In various embodiments, depending on the number of segments configured for processing and the number of bytes the positive and negative binary words have, the segment regions can contain more or fewer bytes. Additionally, these regions do not need to have the same number of bytes.

[0106] A running minimum filter for center transitions can be performed between a certain number of half-cycles. During any PLC data traffic that can run on 1 or 2 half-cycles, center transitions can be filtered out; otherwise, as shown and described in the following example, there may be a significant difference between the PLC and AF values.

[0107] Figure 9A and 9B show examples of a power line carrier (PLC) signal and its corresponding positive and negative vectors converted into bytes. Both the positive and negative vectors are described in a parameter table converted to binary.

[0108] Power line carrier can include a synchronization signal transmitted, for example, every two AC line cycles (50 Hz or 60 Hz), typically synchronized by the voltage zero crossing. This synchronization signal, called a PLC beacon, can be decoded into patterns over time, and these patterns can be stored for future use in identifying PLC activity on the circuit. For example, using negative vectors, these patterns can be processed to determine the presence of any power line carrier signal in the future when there is any data or Internet activity, such as during normal movie streaming or big data transfer activities. Figure 9C An example is shown in which the PLC beacon and its corresponding positive and negative vectors are converted into bytes.

[0109] In Figure 9A an example 900 of vector allocation for a sampled segment of a signal within a signal cycle of a PLC signal according to an embodiment is shown. In this example, there is a PLC signal. As Figure 9A shown, graph 910 shows the sampled signal (e.g., RSSI samples) 912 and the AC or current signal 914 varying over time, and graph 920 shows the vector representations of the positive vector 922 and the negative vector 924 corresponding to the sampled signal. As described herein, the representative value of each segment of the sampled signal within period 902 can be determined based on the analysis of the sampled segment to reflect the signal pattern of the sampled signal over time. In this example, the sampled segments of the sampled signal over period 902 have been evaluated and can be represented as follows: 00001110, as shown at 926, from which the positive and negative vectors of the sampled signal can be determined. Period 902 can be a half cycle.

[0110] In Figure 9B an example 930 of vector allocation for a sampled segment of a signal within a signal cycle of a PLC signal according to an embodiment is shown. In this example, there is a PLC signal. As Figure 9A shown, graph 940 shows the sampled signal (e.g., RSSI samples) 942 and the AC or current signal 944 varying over time, and graph 950 shows the vector representations of the positive vector 952 and the negative vector 954 corresponding to the sampled signal. As described herein, the representative value of each segment of the sampled signal within period 932 can be determined based on the analysis of the sampled segment to reflect the signal pattern of the sampled signal over time. In this example, the sampled segments of the sampled signal over period 932 have been evaluated and can be represented as follows: -1, 1, 0, 1, 1, 0, 0, 0, as shown at 956, from which the positive and negative vectors of the sampled signal can be determined. Period 932 can be a half cycle.

[0111] In Figure 9C an example 960 of vector allocation for a sampled segment of a signal within a signal cycle of a PLC beacon according to an embodiment is shown. In this example, there is a PLC signal. As Figure 9CAs shown, graph 970 shows a sampled signal (e.g., RSSI sample) 972 and an AC or current signal 974 varying over time, and graph 980 shows a vector representation corresponding to a positive vector 982 and a negative vector 984 of the sampled signal. As described herein, a representative value of each segment of the sampled signal within a period 902 can be determined based on an analysis of the sampled segments to reflect the signal pattern of the sampled signal over time. In this example, the sampled segments of the sampled signal on the first period 962 have been evaluated and can be represented as follows: -1, 1, 1, -1, -1, 1, 1, 0, followed by 0, -1, 1, -1, 1, 1, 1, -1 on period 962 as shown at 986, from which the positive and negative vectors of the sampled signal (or a portion thereof) can be determined.

[0112] Examples are shown in Figure 10 and 11 wherein a PLC beacon signal is processed into two unique group patterns (e.g., group A and group B), which can be used to detect the presence of any power line carrier with a high enough confidence. The method can use at least 4 half-cycles.

[0113] By applying a new threshold (e.g., TH3) to each negative word, new binary values can be created, which create a unique group pattern within 4 half-cycles (HF). Depending on the position of the beacon signal (since this synchronization signal drifts over time relative to the line voltage), the patterns can be divided into two groups A or B. The same network with a power line carrier module can start with the pattern of group A and then transfer to group B and rotate between them. Thus, it is desirable to detect both patterns, which can allow a flexible and adaptive algorithm to adjust under any synchronization drift that the PLC module may have.

[0114] In various embodiments, using a counter to measure the number of patterns that occur can increase the accuracy of the power line carrier presence flag.

[0115] Figure 10 Shows an example 1000 of a PLC beacon converting from 4-HC (half-cycle) to a 4-byte pattern in an AC network in example group A according to one embodiment. As Figure 10As shown, graph 1010 shows an example of a monitored signal sample (e.g., RSSI sample) over time, and graph 1020 shows the corresponding vector representation of negative vector 1022, which reflects the signal pattern of the PLC beacon. The signal pattern of the PLC beacon can be represented as a binary word having bit values (e.g., 0 or 1) associated with a sample segment threshold (e.g., TH3). In this example, a PLC beacon with an initial pattern 1100 is shown, where if the value of the negative vector of a segment is greater than the segment threshold, byte 1 is assigned, and if the value of the negative vector of the segment is less than (or equal to) the segment threshold, byte 0 is assigned. For example, the pattern 1100 can be part of a PLC pattern here called Group A, which can drift from 1100 to 1001 to 0011 to 0110 and back to 1100 (or between these patterns), and can be used for PLC communication on a protected circuit.

[0116] In various embodiments, a processor can be configured to monitor a sample signal on a protected circuit, detect PLC communication, and decode a PLC pattern associated with the PLC communication, including the pattern of a PLC beacon employed (or to be employed) on the circuit. Such a PLC pattern can be stored in a memory for detecting the presence of PLC activity on the circuit.

[0117] Figure 11 An example 1100 of a PLC beacon that converts from 4-HC (half-cycle) in an AC network to a 4-byte pattern in Group B according to an embodiment is shown. As Figure 11 shown, graph 1110 shows an example of a monitored signal sample (e.g., RSSI sample) over time, and graph 1120 shows the corresponding vector representation of negative vector 1122, which reflects the signal pattern of the PLC beacon. The signal pattern of the PLC beacon can be represented as a binary word having byte values (e.g., 0 or 1) associated with a sample segment threshold (e.g., TH3). In this example, a PLC beacon with an initial pattern 1110 is shown, where if the value of the negative vector of a segment is greater than the segment threshold, byte 1 is assigned, and if the value of the negative vector of the segment is less than (or equal to) the segment threshold, byte 0 is assigned. For example, the pattern 1110 can be part of a PLC pattern here called Group B, which can drift from 1110 to 1101 to 1011 0111 and back to 1110 (or between these patterns), and can be used for PLC communication on a protected circuit.

[0118] In various embodiments, a processor can be configured to monitor a sample signal on a protected circuit, detect PLC communication, and decode a PLC pattern associated with the PLC communication, including the pattern of a PLC beacon employed (or to be employed) on the circuit. Such a PLC pattern can be stored in a memory for detecting the presence of PLC activity on the circuit.

[0119] Figure 12 Example 1200 shows a graph according to an embodiment, showing side and center transitions related to PLC. As Figure 12 shown, graph 1210 shows an example of a monitored signal sample (e.g., RSSI sample) varying over time, and graph 1220 (parameter list) shows the corresponding vector representation, which reflects the patterns of center transition 1222 and side transition 1224. As described herein, when PLC communication is present, the center and side transitions can be analyzed to determine the presence (or absence) of an arc fault signal.

[0120] In this example, a significant number of center and side transitions are generated from the power line carrier RSSI signal. None of these half-cycles can be classified as arc fault half-cycles; thus, the AF detection algorithm can ignore and not determine a trip condition.

[0121] Figure 13 Example 1300 shows a graph according to an embodiment, showing side and center transitions related to PLC and arc fault signals. As Figure 13 shown, graph 1310 shows an example of a monitored signal sample (e.g., RSSI sample) varying over time, and graph 1320 (parameter list) shows the corresponding vector representation, which reflects the patterns of center transition 1322 and side transition 1324. As described herein, when PLC communication is present, the center and side transitions can be analyzed to determine the presence (or absence) of an arc fault signal. In this example, there is an arc fault signal.

[0122] In this example, even though there is a PLC signal, the arc fault signal does not have any center transitions. Thus, the AF detection algorithm can classify these half-cycles as arc discharges and determine a trip condition.

[0123] Various example methods and systems (including their components) are described herein. It should be understood that the various examples of the method and system can employ various signal processing circuits, including but not limited to converters (e.g., A / D converters), signal conditioning circuits, filters, etc., to facilitate the various operations and functions described herein. Additionally, the arc fault detection method and system can be implemented on a circuit protection device such as a circuit breaker or disconnector, or separately implemented in a computer-implemented detection system that can be used to control one or more circuit protection devices in response to the detection of an arc fault or other fault condition.

[0124] It should also be understood that the exemplary embodiments disclosed and taught herein are susceptible to many and various modifications and alternative forms. Thus, the use of singular terms, such as but not limited to "a", etc., is not intended to limit the number of items. Additionally, the naming conventions for the various components, functions, features, thresholds, and other elements used herein are provided as examples and may be given different names or labels. The use of the term "or" is not limited to the exclusive "or" and may also mean "and / or".

[0125] It should be understood that the development of actual, real-world commercial applications in conjunction with aspects of the disclosed embodiments will require many implementation-specific decisions to achieve the developer's ultimate goals for the commercial embodiment. Such implementation-specific decisions can include, and may not be limited to, compliance with system-related, business-related, government-related, and other constraints, which can vary with a particular implementation, location, and time. While the developer's efforts may be complex and time-consuming in an absolute sense, such efforts are still routine tasks for those skilled in the art who benefit from this disclosure.

[0126] Using the description provided herein, the example embodiments can be implemented as a machine, process, or article of manufacture by using standard programming and / or engineering techniques to generate programming software, firmware, hardware, or any combination thereof.

[0127] Any resulting program having computer-readable program code can be included on one or more tangible or non-transitory computer-usable media, such as a resident memory device, a smart card, or other removable memory device, or a transmission device, thereby forming a computer program product or article of manufacture according to an embodiment. Similarly, the terms "article of manufacture" and "computer program product" as used herein are intended to encompass a computer program that permanently or temporarily resides on any computer-usable or storage media or any transmission medium that transmits such a program.

[0128] The processor, controller, or processing unit described herein can be a processing system, which can include one or more processors, such as a CPU, a controller, an ASIC, or other processing unit or circuitry, which controls or executes the operation of the devices or systems described herein. The memory / storage device can include, but is not limited to, a disk, a solid-state drive, an optical disk, a removable storage device such as a smart card, a SIM, a WIM, a semiconductor memory such as RAM, ROM, PROM, etc. The transmission medium or network includes, but is not limited to, transmission via wired communication, wireless communication (such as radio frequency (RF) communication, Bluetooth, Wi-Fi, Li-Fi, etc.), the Internet, an intranet, telephone / modem-based network communication, a hardwired / cable communication network, satellite communication, and other fixed or mobile network systems / communication links. Wired communication can include power line communication.

[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and / or operations of various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion that includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative embodiments, the functions marked in the blocks may not occur in the order marked in the figures. For example, two consecutive blocks shown may actually be executed substantially simultaneously, or these blocks may sometimes be executed in the reverse order, depending on the functions involved. It will also be noted that each block in the block diagram and / or flowchart illustration, and combinations of blocks in the block diagram and / or flowchart illustration, can be implemented by a system based on dedicated hardware that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0130] Although specific embodiments and applications of the present disclosure have been shown and described, it should be understood that the present disclosure is not limited to the exact construction and composition disclosed herein, and that various modifications, changes, and variations will be apparent from the foregoing description without departing from the invention as defined in the appended claims.

Claims

1. A method, comprising: Sampling a signal that measures electrical activity on a circuit of a power distribution system, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal including a plurality of sample segments; For each sample segment, calculating segment attributes including signal-to-noise ratio (SNR) and root mean square (RMS); Based on the segment attributes calculated for each sample segment of the sampled signal, generating a pattern representing the presence of any signal transitions within a signal sample period of the sampled signal; and Determining the presence of an arc fault signal based on the generated pattern and a predetermined pattern of PLC activity on the circuit.

2. The method according to claim 1, further comprising: Determining the presence of power line carrier (PLC) activity on the circuit; Wherein the segment attributes are calculated at least in response to the presence of power line carrier activity on the circuit.

3. The method according to claim 1, wherein, The generated pattern is a binary word having a side region reflecting a potential side transition and a center region reflecting a potential center transition. The presence of an arc fault signal is determined when the side transition of the generated pattern has a non-zero value and decreases to a zero value in the center transition of the generated pattern. The side transition with a non-zero value represents a transition captured near a zero crossing around the arc ignition and extinction regions, and the center transition with a zero value represents PLC communication.

4. The method according to claim 1, wherein The generating operation includes: Assigning one of a positive value, a negative value, or a zero value based on the calculated SNR and / or RMS of each sample segment compared to a corresponding segment attribute threshold; Creating a first binary word to reflect any positive vector representation on the plurality of sample segments; Creating a second binary word to reflect any negative vector representation on the plurality of sample segments; and Applying an XNOR (exclusive NOR) function to the first and second binary words to create a third binary word of the sampled signal.

5. The method according to claim 4, wherein The determining includes: Analyzing the values of the side transition / region and the center transition / region from the third binary word to detect the presence of an arc fault signal.

6. The method according to claim 4, wherein The segment attribute threshold may include a dynamic threshold.

7. The method according to claim 1, further comprising: Determining one or more patterns of PLC activity on the circuit, the pattern of PLC activity including at least a pattern of a PLC beacon; And Storing the one or more patterns as one or more of the predetermined patterns of PLC activity.

8. The method according to claim 1, further comprising: In response to detecting the absence of PLC activity, performing fault detection by comparing the signal strength of a high-frequency signal within the electrical activity including voltage or current with a set of dynamic thresholds.

9. The method according to claim 1, wherein The PLC activity may include a PLC beacon or PLC communication.

10. The method according to claim 1, wherein, The sampled signal includes a RSSI (Received Signal Strength Indicator) signal, which is generated by a logarithmic amplifier device based on an electrical signal monitored by at least one sensor on the circuit, and each sample segment of the sampled signal has the same length including a half-cycle signal.

11. A system, comprising: A memory; And A processor configured to: Sampling a signal that measures electrical activity on a circuit of a power distribution system, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal including a plurality of sample segments; For each sample segment, calculate segment attributes including signal-to-noise ratio (SNR) and root mean square (RMS); Based on the segment attributes calculated for each sample segment of the sampled signal, generate a pattern representing the presence of any signal transitions within the signal sample period of the sampled signal; and Determine the presence of an arc fault signal based on the generated pattern and a predetermined pattern of PLC activity on the circuit.

12. The system according to claim 11, wherein, The processor is further configured to: Determine the presence of power line carrier (PLC) activity on the circuit; Wherein, calculate the segment attributes at least in response to the presence of power line carrier activity on the circuit.

13. The system according to claim 11, wherein, The generated pattern is a binary word having a side region reflecting potential side transitions and a center region reflecting potential center transitions. The presence of an arc fault signal is determined when the side transition of the generated pattern has a non-zero value and decreases to a zero value in the center transition of the generated pattern. The side transition with a non-zero value represents a transition captured near the zero crossing point around the arc ignition and extinction regions, and the center transition with a zero value represents PLC communication.

14. The system according to claim 11, wherein, To generate the pattern, the processor is configured to: Based on the calculated SNR and / or RMS of each sample segment compared with corresponding segment attribute thresholds, assign one of a positive value, a negative value, or a zero value; Create a first binary word to reflect any positive vector representation over multiple sample segments; Create a second binary word to reflect any negative vector representation over multiple sample segments; and Apply an XNOR (exclusive NOR) function to the first and second binary words to create a third binary word of the sampled signal.

15. The system according to claim 14, wherein, To determine the presence of an arc fault signal, the processor is configured to: Analyze the values of the side transition / region and the center transition / region from the third binary word to detect the presence of an arc fault signal.

16. The system according to claim 14, wherein, The segment attribute threshold may include a dynamic threshold.

17. The system according to claim 11, wherein, The processor is further configured to: Determine one or more patterns of PLC activity on the circuit, the pattern of PLC activity including at least the pattern of PLC beacons; And Store one or more patterns as one or more of the predetermined patterns of PLC activity in a memory.

18. The system according to claim 11, wherein, The processor is further configured to: In response to detecting the absence of PLC activity, perform fault detection by comparing the signal strength of a high-frequency signal within the electrical activity including voltage or current with a set of dynamic thresholds.

19. The system according to claim 11, wherein, The PLC activity may include PLC beacons or PLC communication.

20. The system according to claim 11, wherein The sampled signal includes a RSSI (Received Signal Strength Indicator) signal, which is generated by a logarithmic amplifier device based on an electrical signal monitored by at least one sensor on the circuit. Each sample segment of the sampled signal has the same length including a half-cycle signal.

21. A tangible computer medium storing computer-executable code, which when executed by one or more processors, the computer-executable code is configured to implement a method including the following: Sample a signal measuring electrical activity on a circuit of a power distribution system, the sampled signal corresponding to the signal strength of the electrical activity on the circuit, the sampled signal including a plurality of sample segments; For each sample segment, calculate segment attributes including signal-to-noise ratio (SNR) and root mean square (RMS); Generate a pattern representing the presence of any signal transitions within a signal sample period of the sampled signal based on segment attributes calculated for each segment of the sampled signal; and Determine the presence of an arc fault signal based on the generated pattern and a predetermined pattern of PLC activity on the circuit.

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