Infrared focal plane reading circuit and method with adjustable pixel-level integration time

Abstract

The invention discloses a pixel-level integration time adjustable infrared focal plane reading circuit and method. The pixel-level integration time adjustable infrared focal plane reading circuit comprises an integration time counter module, a pixel reading unit circuit array module, a control logic circuit module, a column processing circuit and an output module. The pixel read-out unit array module is composed of a plurality of read-out unit circuit sub-modules which are arranged in parallel, each read-out unit circuit sub-module comprises an integrating circuit, a memory and a comparator, an output signal of the memory serves as an input signal of the comparator, and an output of the comparator is connected to the integrating circuit and controls the integrating circuit to stop integrating. The output of the integrating circuit is connected to the column processing circuit and the output module. Different numerical values are configured in a memory of the readout unit circuit, the pixel integration time can be adjusted, each pixel can be independently adjusted, information of a strong target and information of a weak target can be obtained in the same frame at the same time, and the high-dynamic-range imaging effect is achieved.

Description

Technical Field

[0001] The present invention relates to the fields of integrated circuits and optoelectronic technologies, and particularly to an infrared focal plane readout circuit and method with adjustable pixel-level integration time. Background Art

[0002] An infrared focal plane consists of a sensitive element array and a readout circuit. The readout circuit completes the extraction, integration, amplification, and output of the photocurrent of the sensitive element.

[0003] In a traditional readout circuit, the integration time of all pixels is adjusted uniformly and cannot be adjusted independently for each pixel. This limitation greatly restricts the application of the device in imaging in high-dynamic-range scenarios.

[0004] CN117812480A discloses a method and circuit for controlling the timing of a TDI sensor with adjustable states, and proposes a method and circuit for controlling the timing of a TDI-type image sensor, which supports different working modes such as single-picture, continuous-picture, and self-detection. It can achieve variable integration time, which means that in areas where more signal accumulation is required (such as low-brightness areas), the integration time of the pixel row can be extended, while in high-brightness areas, the integration time can be shortened. This can improve the dynamic range and detail capture ability of the image, and enhance the adaptability of the image sensor to different working environments. It is further disclosed that:

[0005] Variable integration time can be achieved, which means that in areas where more signal accumulation is required (such as low-brightness areas), the integration time of the pixel row can be extended, while in high-brightness areas, the integration time can be shortened. This can improve the dynamic range and detail capture ability of the image, and enhance the adaptability of the image sensor to different working environments. However, the extension or shortening of its integration time is for the "pixel row", that is, the integration time is adjusted in units of pixel rows, rather than at the pixel level to independently adjust the integration time of each pixel. In addition, it does not mention how to control the integration time after the exposure time is configured, and this part of the content is the key to realizing the adjustment of the integration time.

[0006] The document "High Dynamic Range Image Sensor with Self Adapting Integrationtime in 3DTechnology" (DOI: 10.1109 / ICECS.2012.6463732) realizes that the integration time of macro pixels (a group of pixels composed of multiple pixels, usually a small NxN array with N2 pixels) can be adjusted to achieve large dynamic imaging. The solution uses the integrated signal voltage to compare and judge with a fixed threshold to achieve the control of the integration time. The integration time of each pixel changes continuously according to the target signal intensity. The integration time of each exposure needs to be read out from the pixel in time for imaging processing. This solution has the following shortcomings:

[0007] (1) The digital comparator is an analog voltage digital comparator, which has static power consumption, resulting in a very large overall power consumption of the pixel array circuit. Therefore, in order to balance the power consumption, this technical solution can generally only be used for macro-pixel-level integration time control. By reducing the number of digital comparators, the power consumption can be reduced to an acceptable level.

[0008] (2) In this scheme, the integral time value needs to be quantified and read out. In this scheme, a 3D stacked multi-chip design is adopted, and the transmission of the integral time value is relatively convenient. However, for a single-chip design, the transmission of the integral time value is difficult to achieve. Therefore, this scheme is not suitable for a single-chip readout circuit design. Summary of the invention

[0009] The technical problem to be solved by the present invention is to overcome the above-mentioned shortcomings and provide an infrared focal plane readout circuit and method with adjustable pixel-level integration time and easy monolithic integration, which has the ability to adjust the pixel-level integration time and can realize high dynamic range imaging within the same frame of the infrared focal plane detector.

[0010] The technical solution of the present invention is:

[0011] An infrared focal plane readout circuit with adjustable pixel-level integration time comprises an integration time counter module, a pixel readout unit circuit array module, a control logic circuit module, a column processing circuit and an output module; the pixel readout unit array module is composed of a plurality of readout unit circuit submodules arranged in parallel, the readout unit circuit submodule comprises an integration circuit, a memory and a comparator, the output signal of the memory is used as an input signal of the comparator, the output of the comparator is connected to the integration circuit and controls it to end the integration operation, and the output of the integration circuit is connected to the column processing circuit and the output module; the control logic circuit generates an integration start control signal and outputs it to the integration circuit in each pixel readout unit circuit submodule; the output of the integration time counter is connected to each pixel readout unit circuit and serves as the input signal of the comparator in the readout unit circuit.

[0012] Further, the comparator is a digital comparator, which can compare the value in the memory with the value output by the integration time counter. When the two values change from being unequal to being equal, the output of the comparator flips.

[0013] Further, a certain integration time value is set in the memory. Each time integration starts, the integration time counter is reset to zero and starts counting triggered by the input clock signal, and its output value gradually increases. When the output value of the integration time counter becomes the same as the value in the memory, the output signal of the comparator flips and controls the integration circuit to stop the integration operation, thereby realizing the control of the integration time. By respectively configuring certain values (which can be equal or unequal) in the memories of each pixel unit circuit, the integration time of each pixel can be controlled, and each pixel can be independently adjusted. In the imaging application of a high dynamic range scenario, for strongly radiated input pixels, the integration time can be adjusted shorter, while for weakly radiated input pixels, the integration time can be adjusted longer, so that the simultaneous detection and imaging of strong and weak targets within the same frame can be realized, achieving the imaging effect of high dynamic range.

[0014] Advantages of the present invention:

[0015] The present invention controls the integration time in the digital domain. The comparator uses a digital comparator, there is no static current, and the circuit power consumption is low. In addition, the present invention realizes the control by writing values from the outside of the chip to control the integration time. The integration time values of the pixel array are generated by an external system and do not need to be read out from the inside of the chip, which is more conducive to the design of a single chip. Compared with the current conventional infrared focal plane readout circuit, where the integration time of all pixels or pixel groups is uniformly adjusted and high dynamic range imaging within the same frame cannot be achieved, the present invention can realize independent adjustment of the pixel-level integration time. In the imaging application of a high dynamic range scenario, for strongly radiated input pixels, the integration time can be adjusted shorter, while for weakly radiated input pixels, the integration time can be adjusted longer, so that the simultaneous detection and imaging of strong and weak targets within the same frame can be realized, achieving the imaging effect of high dynamic range. Description of the Drawings

[0016] Figure 1 : Schematic block diagram of the infrared focal plane readout circuit of the present invention.

[0017] Figure 2 : Circuit schematic diagram of an implementation manner of the integration circuit in the pixel unit circuit of the present invention.

[0018] Figure 3 : Schematic diagram of the integration time control of the readout unit circuit of the infrared focal plane readout circuit with pixel-level integration time adjustment ability of the present invention. Detailed Embodiments

[0019] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] As Figure 1 shown, an infrared focal plane readout circuit with pixel-level integration time adjustment ability according to the present invention includes an integration time counter, a readout unit circuit array, a control logic circuit, a column processing circuit, and an output circuit module. The readout unit circuit array is an array composed of a large number of readout unit circuits; the readout unit circuit includes modules such as an integration circuit, a memory, and a comparator. The output signal of the memory serves as the input signal of the comparator, and the output of the comparator is connected to the integration circuit. The output of the integration time counter is connected to each readout unit circuit and serves as the input signal of the comparator in the readout unit circuit.

[0021] The integration time counter can be implemented by a binary counter.

[0022] The digital comparator can be implemented by a digital comparator that compares each bit separately or compares bit by bit in sequence.

[0023] The memory in the pixel readout unit circuit can be implemented by an SRAM memory.

[0024] For each column of pixels, the input terminals of all SRAM memories therein are short-circuited by data bits respectively to form a column input bus; for each row of pixels, all SRAM write control signals therein are short-circuited to form a row write control signal.

[0025] An encoder is used to address specific row pixels and select specific row pixels. For the selected row pixels, by sending a row write control signal pulse, the data on the column SRAM input buses can be written in parallel into the corresponding column SRAMs of the corresponding row pixels. The column SRAM column input buses of each column of pixels are independent of each other and can be independently configured with data.

[0026] One implementation of the integration circuit in the readout unit circuit is as Figure 2 shown.

[0027] The working principle of an infrared focal plane readout circuit with pixel-level integration time adjustment ability according to the present invention is as follows:

[0028] As Figure 2In the shown integrating circuit, two switches are respectively controlled by an integration start signal (INT) output by a control logic and an integration end signal (COMP) output by a digital comparator. The switches are turned on when the signal level is high and turned off when the signal level is low. The integration time counter is triggered to perform a counting operation by an input clock signal. A value corresponding to a specific integration time is configured in the memory. Before each integration starts, INT is at a high level and COMP is at a high level. At time t0, the control logic controls INT to jump to a low level, and the integration counter starts counting from a cleared state. As shown in Figure 3 , the integration starts. When the value output by the integration counter reaches the value in the pixel circuit memory, the signal (COMP) output by the digital comparator flips, controlling the integrating circuit to end the integration, as shown in Figure 3 at time t1. The length of the integration time is t1 - t0. By configuring different values for the memories of each readout unit circuit, different integration times can be controlled for each pixel to perform integration operations, realizing pixel-level integration time control.

[0029] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An infrared focal plane readout circuit with adjustable pixel-level integration time, characterized in that, It includes an integration time counter module, a pixel readout unit circuit array module, a control logic circuit module, a column processing circuit, and an output module; the pixel readout unit array module is composed of a number of readout unit circuit sub-modules arranged in parallel. Each readout unit circuit sub-module includes an integration circuit, a memory, and a comparator. The output signal of the memory serves as the input signal of the comparator. The output of the comparator is connected to the integration circuit and controls the integration circuit to stop integration. The output of the integration circuit is connected to the column processing circuit and the output module; the control logic circuit generates an integration start control signal and outputs it to the integration circuit in each pixel readout unit circuit sub-module; the output of the integration time counter is connected to each pixel readout unit circuit and serves as the input signal of the comparator in the readout unit circuit.

2. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 1, characterized in that: The comparator is a digital comparator, which is used to compare the value in the memory with the value output by the integration time counter. When the two values change from being unequal to being equal, the output of the comparator flips.

3. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 1, characterized in that: The adjustment of the pixel integration time is achieved by setting different integration time values in each memory.

4. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 1, characterized in that: At the start of each integration, the integration time counter is reset to zero and triggered to count by the input clock signal.

5. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 1, characterized in that: The memory has functions of off-chip data writing, data holding, and data output.

6. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 1, characterized in that: The memory uses an SRAM memory.

7. The infrared focal plane readout circuit with adjustable pixel-level integration time according to claim 6, characterized in that: For each column of pixels, all the SRAM memory input terminals therein are short-circuited by data bit to form a column input bus respectively; for each row of pixels, all the SRAM write control signals therein are short-circuited to form a row write control signal; One decoder is used to address specific row pixels and select specific row pixels; For the selected row pixels, a row write control signal pulse is sent to parallel write the data on each column SRAM input bus into the corresponding column SRAMs of the corresponding row pixels; The column input buses of each column of pixel SRAMs are independent of each other.

8. The infrared focal plane readout circuit with adjustable pixel-level integration time according to any one of claims 1-7, characterized in that: The integration circuit in the readout unit circuit includes two switches controlled by an integration start signal INT output by the control logic and an integration end signal COMP output by the digital comparator respectively; The integration time counter is triggered to perform a counting operation by the input clock signal; Specific integration time corresponding values are configured in the memory.

9. A method for adjusting the pixel-level integration time of an infrared focal plane readout circuit with adjustable pixel-level integration time according to any one of claims 1-8, characterized in that, It includes: The integration time counter is triggered to perform a counting operation by the input clock signal; When the exposure of each frame starts in the focal plane, the integration counter begins to count; When the output value of the integration counter reaches the integration time value set in the pixel circuit memory, the output signal of the digital comparator flips, controlling the integration circuit to end the integration; Different values are configured for the memories of each readout unit circuit, controlling each pixel readout power supply circuit to adopt different integration times.

10. The method for adjustable pixel-level integration time according to claim 9, wherein It further includes: According to the radiation intensity of the target in the scene on different pixels, the integration time values of each readout unit circuit are adjusted accordingly, so as to obtain the information of strong radiation targets and weak radiation targets simultaneously under the condition of ensuring that the device is not saturated within the same frame, and to achieve simultaneous imaging of strong and weak targets within one frame.

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